Charging circuit, electronic equipment and charging equipment

Abstract

The invention relates to the technical field of electronic circuits, in particular to a charging circuit, an electronic device and a charging device.The charging circuit comprises a first charging and logic control unit, a power switching unit and a power management chip, and the output end of the first charging and logic control unit is connected with the input end of a first charging channel of the power switching unit; the input end of the second charging channel is also connected with the first charging interface, and the output end of the first charging channel and the output end of the second charging channel are both connected with the charging end of the battery; the power management chip is used for controlling the first charging channel or the second charging channel to be conducted according to the interrupt signal so as to charge the battery, whether the second charging and logic control unit is connected to the first charging interface of the electronic equipment or not can be accurately detected, and different charging channels are selected to charge the battery according to the detection result. Therefore, the electronic equipment is adapted to the charging equipment with the second charging and logic control unit, and the suitability of the electronic equipment is improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a charging circuit, electronic device and charging equipment. Background Technology

[0002] With the widespread use of smartphones and the increasing demand from users for longer battery life, fast charging technology for smartphones has emerged as lithium battery technology has yet to achieve a breakthrough in improving energy density. It can replenish the battery in a short time, thus highlighting the increasing importance of fast charging technology.

[0003] Without revolutionary breakthroughs in battery materials and chemistry, improving charging technology for smart devices has become a major development direction. Among related technologies, increasing battery capacity and improving charging current are key solutions to charging problems. However, as battery charging power increases, heat generation becomes a significant issue. Some power adapters can place the charging and logic control unit on the adapter side, thus solving the heat problem during charging. However, existing charging circuits used in electronic devices cannot accurately identify the presence of the charging and logic control unit on the adapter side, thus failing to adaptably switch charging paths, resulting in poor compatibility. Summary of the Invention

[0004] This application provides a charging circuit, an electronic device, and a charging equipment to solve the technical problem in the related art where the charging circuit at the electronic device end cannot accurately identify whether there is a charging and logic control unit at the adapter end, resulting in poor adaptability.

[0005] In a first aspect, this application provides a charging circuit for use in an electronic device, wherein the electronic device is provided with a first charging interface, and the charging circuit includes a first charging and logic control unit, a power switching unit, and a power management chip. The input terminal of the first charging and logic control unit is connected to the first charging interface. The power switching unit includes a first charging channel and a second charging channel. The output terminal of the first charging and logic control unit is connected to the input terminal of the first charging channel of the power switching unit. The input terminal of the second charging channel of the power switching unit is also connected to the first charging interface. The output terminals of the first charging channel and the second charging channel are both connected to the charging terminal of the battery. The power management chip is connected to a detection pin on the first charging interface. The detection pin is used to detect whether a second charging and logic control unit is connected to the first charging interface, and outputs an interrupt signal according to the detection result. The power management chip is used to control the first charging channel or the second charging channel to be turned on according to the interrupt signal so as to charge the battery.

[0006] In one possible design, the charging circuit further includes a current detection module and a voltage detection module; The sampling terminal of the current detection module is connected to the second charging channel. The current detection module is used to detect the charging current flowing through the second charging channel. The power management chip is used to generate a corresponding current feedback adjustment signal according to the relationship between the charging current and the target charging current, and output the current feedback adjustment signal to the first charging and logic control unit or the second charging and logic control unit. The sampling end of the voltage detection module is connected to the charging end of the battery. The voltage detection module is used to detect the charging voltage of the charging end of the battery and send the charging voltage to the power management chip. The power management chip is used to monitor the charging voltage of the battery. The first charging and logic control unit or the second charging and logic control unit is used to output a corresponding charging current according to the current feedback adjustment signal.

[0007] In one possible design, the power switching unit includes a seventh PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth NMOS transistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a twenty-first resistor; The seventh PMOS transistor, the eighth NMOS transistor, the sixteenth resistor, the seventeenth resistor, and the eighteenth resistor constitute the first charging channel. The source of the seventh PMOS transistor is the input terminal of the first charging channel. The source of the seventh PMOS transistor is connected to the output terminal of the first charging and logic control unit and the first terminal of the sixteenth resistor. The drain of the seventh PMOS transistor is connected to the charging terminal of the battery. The gate of the seventh PMOS transistor is connected to the second terminal of the sixteenth resistor and the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the first terminal of the eighteenth resistor and a common ground. The second terminal of the eighteenth resistor is connected to the gate of the eighth NMOS transistor and the first terminal of the seventeenth resistor. The second terminal of the seventeenth resistor is used to receive a third enable signal, which is used to control the first charging channel to be turned on or off. The ninth PMOS transistor, the tenth NMOS transistor, the nineteenth resistor, the twentieth resistor, and the twenty-first resistor constitute the second charging channel. The source of the ninth PMOS transistor is the input terminal of the second charging channel. The source of the ninth PMOS transistor is connected to the first charging interface and the first terminal of the nineteenth resistor. The drain of the ninth PMOS transistor is also connected to the charging terminal of the battery. The gate of the ninth PMOS transistor is connected to the second terminal of the nineteenth resistor and the drain of the tenth NMOS transistor. The source of the tenth NMOS transistor is connected to the first terminal of the twenty-first resistor and a common ground. The second terminal of the twenty-first resistor is connected to the gate of the tenth NMOS transistor and the first terminal of the twenty-first resistor. The second terminal of the twenty-first resistor is used to receive a fourth enable signal, which is used to control the second charging channel to be turned on or off.

[0008] In one possible design, the first charging and logic control unit and the second charging and logic control unit have the same structure; The first charging and logic control unit includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, a constant current charging unit, and a main control unit; The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage. The output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to the input terminal of the first charging channel to output charging current to the first charging channel. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit and the second transistor unit to output corresponding charging currents. The current control unit is used to sample the input current at the input terminal of each transistor unit and output a corresponding current balancing control signal according to the input current, so as to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing. The voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value, so as to control the output charging voltage to be stable at the reference voltage value. The constant current charging unit is connected to the charging output terminal. The main control unit is also used to receive a pre-charge trigger signal fed back from the load terminal and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal. The constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0009] In one possible design, the control signal output pin of the main control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively, so as to output the control voltage signal to the first transistor unit and the second transistor unit, respectively. The input terminal of the current control unit is connected to the input terminal of the first transistor unit and the input terminal of the second transistor unit, respectively, and the output terminal of the current control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively, so as to output the current equalization control signal to the first transistor unit and the second transistor unit, respectively. The main control unit includes a charging detection pin, which is connected to the power input terminal to detect whether an external power source is connected to the power input terminal, and outputs a corresponding indication signal according to the detection result; and when the indication signal indicates that an external power source is connected, it controls the first transistor unit, the second transistor unit and the voltage regulation control unit to start working. The input terminals of the first transistor unit and the second transistor unit are both connected to the power input terminal, which is used to receive the input current from an external power source.

[0010] In one possible design, the first transistor unit includes a first transistor and a first NMOS transistor. The emitter of the first transistor is the input terminal of the first transistor unit, and the collector of the first transistor is the output terminal of the first transistor unit. The emitter of the first transistor is connected to the power input terminal, the base of the first transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is the control terminal of the first transistor unit, the source of the first NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the first NMOS transistor is connected to the power input terminal. The second transistor unit includes a second transistor and a second NMOS transistor. The emitter of the second transistor is the input terminal of the second transistor unit, and the collector of the second transistor is the output terminal of the second transistor unit. The emitter of the second transistor is connected to the power input terminal, the base of the second transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is the control terminal of the second transistor unit, the source of the second NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the second NMOS transistor is connected to the power input terminal. The first charging and logic control unit further includes a first resistor and a second resistor; a first end of the first resistor is connected to the power input terminal, and a second end of the first resistor is connected to the emitter of the first transistor; a first end of the second resistor is connected to the power input terminal, and a second end of the second resistor is connected to the emitter of the second transistor. The current control unit includes a first operational amplifier, a second operational amplifier, and a third operational amplifier; the non-inverting input terminal of the first operational amplifier is connected to the first terminal of the first resistor, the inverting input terminal of the first operational amplifier is connected to the second terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the third operational amplifier. The non-inverting input of the second operational amplifier is connected to the first end of the second resistor, the inverting input of the second operational amplifier is connected to the second end of the second resistor, and the output of the second operational amplifier is connected to the non-inverting input of the third operational amplifier; the output of the third operational amplifier is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively.

[0011] In one possible design, the constant current charging unit includes a first reference voltage generation chip, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth operational amplifier, and a third NMOS transistor. The enable terminal of the first reference voltage generation chip is connected to a first enable pin on the main control unit. The voltage output pin of the first reference voltage generation chip is connected to a first terminal of the sixth resistor. The second terminal of the sixth resistor is connected to both the non-inverting input terminal of the fourth operational amplifier and the first terminal of the seventh resistor. The second terminal of the seventh resistor is grounded. The output terminal of the fourth operational amplifier is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to the charging output terminal. The source of the third NMOS transistor is connected to both the first terminals of the eighth and tenth resistors. The second terminal of the eighth resistor is connected to the inverting input terminal of the fourth operational amplifier. The second terminal of the tenth resistor is grounded. The first reference voltage generation chip receives a first enable signal output by the main control unit and outputs a first reference voltage signal upon triggering the first enable signal. The voltage regulation control unit includes a second reference voltage generation chip, a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor, and a third PMOS transistor. The enable terminal of the second reference voltage generation chip is connected to a second enable pin on the main control unit. The voltage output pin of the second reference voltage generation chip is connected to the non-inverting input terminal of the fifth operational amplifier. The output terminal of the fifth operational amplifier is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the power supply pin on the first charging interface and the first terminal of the fourteenth resistor. The second terminal of the fourteenth resistor is connected to the inverting input terminal of the fifth operational amplifier. The main control unit is further configured to output a second enable signal to the second reference voltage generation chip when an external power supply is detected connected to the power input terminal. The second reference voltage generation chip is configured to output a second reference voltage signal triggered by the second enable signal.

[0012] Secondly, this application also provides an electronic device, which includes a charging circuit as described in any of the preceding claims.

[0013] Thirdly, this application also provides a charging device, which includes a charging base and a charging converter, wherein the charging base and the charging converter are pluggably connected via a compatible charging interface; The charging base is equipped with an AC-DC conversion module, which includes a rectifier and filter circuit, a high-frequency voltage converter, and a DC converter. The AC-DC conversion module is used to rectify and convert the input AC power. The charging converter is provided with a second charging interface, which is pluggably connected to the first charging interface on the electronic device; the charging converter is provided with a second charging and logic control unit, which is used to receive control signals fed back from the electronic device to process the DC power output by the AC-DC conversion module in order to output an appropriate charging voltage and charging current.

[0014] In one possible design, the second charging and logic control unit includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, a constant current charging unit, and a main control unit; The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage. The output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to the second charging interface to output charging current to the second charging interface. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit and the second transistor unit to output corresponding charging currents. The current control unit is used to sample the input current at the input terminal of each transistor unit and output a corresponding current balancing control signal according to the input current, so as to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing. The voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value, so as to control the output charging voltage to be stable at the reference voltage value. The constant current charging unit is connected to the charging output terminal. The main control unit is also used to receive a pre-charge trigger signal fed back from the load terminal and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal. The constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0015] The charging circuit provided in the first aspect is used in an electronic device. The charging circuit includes a first charging and logic control unit, a power switching unit, and a power management chip. The input terminal of the first charging and logic control unit is connected to a first charging interface on the electronic device. The power switching unit includes a first charging channel and a second charging channel. The output terminal of the first charging and logic control unit is connected to the input terminal of the first charging channel of the power switching unit. The input terminal of the second charging channel of the power switching unit is also connected to the first charging interface. The output terminals of both the first and second charging channels are connected to the charging terminals of the battery. The power management chip is connected to a detection pin on the first charging interface. The detection pin is used to detect whether a second charging and logic control unit is connected to the first charging interface, and outputs an interrupt signal based on the detection result. The power management chip is used to control the first charging channel or the second charging channel to be turned on according to the interrupt signal to charge the battery. Based on the charging circuit provided in this application, it is possible to accurately detect whether a second charging and logic control unit is connected to the first charging interface of the electronic device, and select different charging channels to charge the battery according to the detection result. This makes the electronic device compatible with charging devices having a second charging and logic control unit, improving the compatibility of the electronic device.

[0016] The beneficial effects provided by the other aspects and the various possible designs of the other aspects can be found in the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0017] Figure 1 A schematic diagram of the overall structure of the charging system provided for related technologies; Figure 2 This is a schematic diagram of the structure of a charging device provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the application scenario of the charging device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the power switching unit structure provided in this application; Figure 5 This is a schematic diagram of the current detection module structure provided in this application; Figure 6 This is a schematic diagram of the overall structure of the first charging and logic control unit provided in an embodiment of this application; Figure 7 A schematic diagram of the specific structure of the first charging and logic control unit provided in the embodiments of this application. Detailed Implementation

[0018] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0021] While current high-power fast charging technologies (such as the 100W solutions offered by mobile phone manufacturers) have achieved significant breakthroughs in charging speed, they are still constrained by high hardware costs and bulky adapters. In existing mainstream architectures, charging control chips are typically integrated inside electronic devices. However, both switching and linear charging schemes suffer from conversion efficiency bottlenecks, and power loss inevitably translates into Joule heat. Experimental data shows that when running high-load gaming applications at a room temperature of 25°C, the temperature rise of electronic devices is typically between 25°C and 35°C, resulting in a steady-state body temperature of 50°C to 55°C. This thermal effect is particularly pronounced in extreme conditions such as high temperatures outdoors in summer or when running demanding 3D games. Furthermore, the combined effect of the high current from the power management IC (PMIC) and the backlight driver module further exacerbates the heat buildup. Sustained high-temperature operating environments not only severely reduce the user's subjective interactive experience but also cause irreversible damage to the chip's thermal stability and overall lifecycle reliability.

[0022] Figure 1 Please refer to the overall structural diagram of the charging system provided for related technologies. Figure 1 As shown, the charging system for electronic devices provided by related technologies mainly includes: a first charging adapter 100, a first USB interface 101, a second USB interface 102, and a first charging management unit 103. The first USB interface 101 and the second USB interface 102 are connected via a Universal Serial Bus (USB). The AC-DC conversion module within the first charging adapter 100 converts 220V AC power into a constant 5V DC voltage output. This 5V voltage is then transmitted to the first charging management unit 103 via the USB cable. Upon receiving the 5V voltage, the first charging management unit 103 charges the battery under the control of a charging chip and a power management chip (PMIC). Currently, most electronic products on the market use existing charging solutions. However, with the increase in battery charging power, heat generation has become a technical problem. Some power adapters can place the charging and logic control units on the adapter side, thus solving the heat generation problem during charging of electronic devices.

[0023] This application proposes an innovative design concept based on modular circuit topology. At the circuit architecture level, the solution constructs the charging and logic control unit module as a parallel configuration of dual transistor units. Through the coordinated regulation of constant current source, constant voltage source, and differential amplifier feedback circuit, precise clamping and constant output of the total charging current are achieved. Furthermore, this solution designs the charging and logic control unit module as an externally separable module. This circuit architecture not only effectively reduces hardware costs but also significantly reduces heat dissipation of the terminal device during charging. This design has significant advantages in optimizing user interaction experience, extending device hardware lifespan, and enhancing system safety, ultimately providing a low-cost and high-efficiency thermal management solution for smart wearable devices (such as smartwatches and Bluetooth headsets) and other small consumer electronics terminals.

[0024] Figure 2 For a schematic diagram of a charging device provided in an embodiment of this application, please refer to [link / reference]. Figure 2 As shown, the charging device 20 includes a charging base 200 and a charging converter 201, which are pluggable and detachable through a compatible charging interface. In this way, in actual application scenarios, users can choose to use the charging converter 201 or not use the charging converter 201 depending on the type of electronic device.

[0025] For example, one end of the charging dock 200 is provided with a 220V AC power interface for connecting to AC power; at the same time, the other end of the charging dock 200 is provided with a first plug-in interface, and correspondingly, the charging converter 201 is also provided with a second plug-in interface adapted to the first plug-in interface. The charging dock 200 and the charging converter 201 can be plugged and detached through the first plug-in interface and the second plug-in interface; in other embodiments, the interface types of the first plug-in interface and the second plug-in interface can be selected from industrially commonly used POWER_IN interfaces, or USB Type-C interfaces, etc., without limitation, and technicians can choose the appropriate interface as needed.

[0026] The charging base 2000 includes an AC-DC conversion module 200, which comprises a rectifier and filter circuit, a high-frequency voltage converter, and a DC converter. The AC-DC conversion module 200 is used to rectify and convert the input AC mains power. Specifically, the rectifier and filter circuit can rectify the input AC mains power to obtain DC power, and then output 5V DC power through the electrical isolation and voltage conversion of the high-frequency voltage converter and the DC converter.

[0027] The charging converter 201 is equipped with a second charging interface, which can be plugged into and connected to the first charging interface on the electronic device. The interface types of the first and second charging interfaces can be selected according to different products. For example, for common electronic devices (such as mobile phones, tablets, etc.), the first and second charging interfaces can adopt the common USB Type-C interface; or for common battery packs or battery systems, the first and second charging interfaces can adopt the industrial-grade POWER_IN interface.

[0028] The charging converter 201 includes a second charging and logic control unit, which receives control signals from the electronic device and processes the DC power output from the AC-DC conversion module to output a suitable charging voltage and charging current. For detailed structure and function of this second charging and logic control unit, please refer to the explanations of the following embodiments.

[0029] In one embodiment, when the electronic device does not require the use of the charging converter 201, the user can choose to unplug the charging converter 201 from the charging dock 2000. This allows the DC power output from the charging dock 2000 to charge the electronic device, thus adapting to different charging devices and application scenarios.

[0030] Figure 3 For an illustration of an application scenario of the charging device provided in this application embodiment, please refer to [link / reference]. Figure 3 As shown, the Figure 3 This illustrates a scenario where, in addition to using the charging converter 201, the charging dock 2000 quickly charges electronic devices by connecting to the charging converter 201.

[0031] As can be seen, according to the charging device provided in this embodiment, the charging converter 201 is configured as a pluggable connection, which improves the adaptability of the charging device. When charging electronic devices, the second charging and logic control unit in the charging converter 201 can be used to quickly charge the electronic devices. While improving charging efficiency, the part that generates heat during charging can be transferred to the charger, thus saving space inside the electronic devices and avoiding the heat generation problem caused by charging. In addition, it also avoids the problem of the second charging and logic control unit interfering with the battery inside the electronic devices.

[0032] Please continue reading Figure 3As shown in the figure, this application embodiment also provides a charging circuit for use in an electronic device. The electronic device is provided with a first charging interface. The charging circuit includes a first charging and logic control unit 204, a power switching unit 205, and a power management chip 206. The input terminal of the first charging and logic control unit 204 is connected to the first charging interface. The power switching unit 205 includes a first charging channel and a second charging channel. The output terminal of the first charging and logic control unit 204 is connected to the input terminal of the first charging channel of the power switching unit 205. The input terminal of the second charging channel of the power switching unit 205 is also connected to the first charging interface. The output terminals of the first charging channel and the second charging channel are both connected to the charging terminal of the battery. The power management chip 206 is connected to the detection pin DET on the first charging interface. The detection pin DET is used to detect whether the second charging and logic control unit is connected to the first charging interface, and outputs an interrupt signal according to the detection result. The power management chip 206 is used to control the first charging channel or the second charging channel to be turned on according to the interrupt signal to charge the battery.

[0033] For example, when the detection pin DET detects that a charging converter 201 (second charging and logic control unit) is connected to the first charging interface of the electronic device, the output interrupt signal is pulled low, for example, the output interrupt signal is 0, and the power management chip 206 is used to control the second charging channel to be turned on according to the interrupt signal; when the detection pin DET detects that no charging converter 201 is connected to the first charging interface of the electronic device, the output interrupt signal is high, for example, the output interrupt signal is 1, and the power management chip 206 is used to control the first charging channel to be turned on according to the interrupt signal.

[0034] The charging circuit provided in this application can accurately detect whether a second charging and logic control unit is connected to the first charging interface of an electronic device, and select different charging channels to charge the battery according to the detection results, so that the electronic device is compatible with charging devices with a second charging and logic control unit, thereby improving the compatibility of the electronic device.

[0035] In one embodiment, the charging circuit further includes a current detection module 400 and a voltage detection module (not shown in the figure); the sampling terminal of the current detection module 400 is connected to the second charging channel, and the current detection module 400 is used to detect the charging current flowing through the second charging channel; the power management chip 206 is used to generate a corresponding current feedback adjustment signal according to the relationship between the charging current and the target charging current, and output the current feedback adjustment signal to the first charging and logic control unit 204 or the second charging and logic control unit; the sampling terminal of the voltage detection module is connected to the charging terminal of the battery, and the voltage detection module is used to detect the charging voltage of the battery charging terminal, and send the charging voltage to the power management chip 206, and the power management chip 206 is used to monitor the charging voltage of the battery; the first charging and logic control unit 204 or the second charging and logic control unit is used to output a corresponding charging current according to the current feedback adjustment signal.

[0036] In this embodiment, the charging current and charging voltage of the battery can be sampled in real time through the current detection module 400 and the voltage detection module. Then, the power management chip 206 can compare the sampled charging current and charging voltage with the set target charging current and target charging voltage, and output the corresponding feedback adjustment signal to adjust the appropriate charging current and charging voltage output by the first charging and logic control unit 204 or the second charging and logic control unit, so as to ensure the charging efficiency of the battery and the charging safety of the battery.

[0037] Figure 4 For a schematic diagram of the power switching unit structure provided in this application, please refer to [link / reference]. Figure 4 As shown, the power switching unit 205 provided in this embodiment includes a seventh PMOS transistor Q7, an eighth NMOS transistor Q8, a ninth PMOS transistor Q9, a tenth NMOS transistor Q10, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, and a twenty-first resistor R21.

[0038] in, Figure 4The seventh PMOS transistor Q7, the eighth NMOS transistor Q8, the sixteenth resistor R16, the seventeenth resistor R17, and the eighteenth resistor R18 form the first charging channel. The source of the seventh PMOS transistor Q7 is the input terminal POWER_A of the first charging channel. The source of the seventh PMOS transistor Q7 is connected to the output terminal of the first charging and logic control unit 204 and the first terminal of the sixteenth resistor R16. The drain of the seventh PMOS transistor Q7 is connected to the charging terminal of the battery. The gate of the seventh PMOS transistor Q7 is connected to the second terminal of the sixteenth resistor R16 and the drain of the eighth NMOS transistor Q8. The source of the eighth NMOS transistor Q8 is connected to the first terminal of the eighteenth resistor R18 and the common ground. The second terminal of the eighteenth resistor R18 is connected to the gate of the eighth NMOS transistor Q8 and the first terminal of the seventeenth resistor R17. The second terminal of the seventeenth resistor R17 is used to receive the third enable signal GPIO3, which is used to control the first charging channel to be turned on or off.

[0039] For example, when the output interrupt signal is 1, the power management chip 206 outputs the third enable signal GPIO3 at a high level. The third enable signal GPIO3 first controls the eighth NMOS transistor Q8 to turn on, and then pulls down the gate voltage of the seventh PMOS transistor Q7 to control the seventh PMOS transistor Q7 to turn on, and finally controls the first charging channel to turn on. At this time, the first charging and logic control unit 204 is connected to work. The first charging interface receives the 5V DC power output by the charging device to power the first charging and logic control unit 204. The first charging and logic control unit 204 charges the battery through the first charging channel.

[0040] in, Figure 4 The ninth PMOS transistor Q9, the tenth NMOS transistor Q10, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21 form the second charging channel. The source of the ninth PMOS transistor Q9 is the input terminal POWER_B of the second charging channel. The source of the ninth PMOS transistor Q9 is connected to the first charging interface and the first terminal of the nineteenth resistor R19. The drain of the ninth PMOS transistor Q9 is also connected to the charging terminal of the battery. The gate of the ninth PMOS transistor Q9 is connected to the second terminal of the nineteenth resistor R19 and the drain of the tenth NMOS transistor Q10. The source of the tenth NMOS transistor Q10 is connected to the first terminal of the twenty-first resistor R21 and the common ground. The second terminal of the twenty-first resistor R21 is connected to the gate of the tenth NMOS transistor Q10 and the first terminal of the twentieth resistor R20. The second terminal of the twentieth resistor R20 is used to receive the fourth enable signal GPIO4, which is used to control the second charging channel to be turned on or off.

[0041] For example, when the output interrupt signal is 0, the power management chip 206 outputs the fourth enable signal GPIO4 at a high level. The fourth enable signal GPIO4 first controls the tenth NMOS transistor Q10 to turn on, and then pulls down the gate voltage of the ninth PMOS transistor Q9 to control the ninth PMOS transistor Q9 to turn on, and finally controls the second charging channel to turn on. At this time, the first charging and logic control unit 204 is disconnected, and the first charging interface receives the 5V DC power output by the charging device to power the second charging and logic control unit. The second charging and logic control unit charges the battery through the second charging channel.

[0042] In one embodiment, the charging circuit further includes a 22nd resistor R22, which is a current sampling resistor connected in series in the branch where the second charging channel is located. The current detection module 400 determines the charging current flowing through the 22nd resistor R22 by sampling the voltage across the 22nd resistor R22.

[0043] Figure 5 For a schematic diagram of the current detection module provided in this application, please refer to [link / reference]. Figure 5 As shown, the current detection module provided in this embodiment includes a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a 26th resistor R26, and a 6th operational amplifier A6. The first end of the 23rd resistor R23 is connected to the first end of the 22nd resistor R22. The second end of the 23rd resistor R23 is connected to the first end of the 24th resistor R24 ​​and the non-inverting input of the 6th operational amplifier A6. The second end of the 24th resistor R24 ​​is grounded. The first end of the 25th resistor R25 is connected to the second end of the 22nd resistor R22. The second end of the 25th resistor R25 is connected to the inverting input of the 6th operational amplifier A6 and the first end of the 26th resistor R26. The second end of the 26th resistor R26 is connected to the output of the 6th operational amplifier A6 and the ADC sampling module of the power management chip 206.

[0044] The ADC module inside the power management module 206 is used to sample the output charging voltage value V of the current detection module 400. OUT To calculate the actual charging current I flowing into battery U4 VBAT—Charege For example, during charging, the actual charging current I... VBAT_Charege And the software preset charging current value I SW_SET In contrast, by dynamically adjusting the control voltage signal V_drive in real time through a negative feedback loop, the conduction state of the transistor unit circuit is changed to adjust the actual charging current value I. VBAT_Charege This makes the actual charging current I VBAT_Charege And the software-preset charging current value I SW_SETMaintain consistency to achieve a dynamic equilibrium.

[0045] Among them, V SENSE Used to detect the battery voltage, i.e., when the power management module 206 passes through V SENSE When the battery voltage is detected to be within a certain range (for example, the battery voltage is between 2.2V and 3.2V, which is the pre-charging stage), the charging enters the pre-charging stage, and the first enable signal GPIO1 is set to a high level to start the constant current charging unit; when the battery voltage is higher than a certain value, the charging enters the constant current charging stage, and GPIO1 is set to a low level to turn off the constant current charging unit and stop the pre-charging state.

[0046] More specifically, the principle behind the voltage amplification across the 22nd resistor R22 by the current detection module 400 is as follows: Based on the principles of virtual short and virtual open circuits of operational amplifiers, let R... 23 =R 25 R 24 =R 26， After calculation, we obtained:

[0047] Where: V R22 R is the voltage across resistor R22; 23 The resistance value of the twenty-third resistor is R. 25 The resistance value of the twenty-fifth resistor, R 24 The resistance value of the twenty-fourth resistor, R 26 This is the resistance value of the twenty-sixth resistor.

[0048] The charging current I flowing into the battery VBAT_Charege Converted into a voltage signal V across the twenty-second resistor R22 R22 and V R22 After amplification by R24 / R23 times by the sixth operational amplifier A6, the resulting output voltage V OUT The output voltage V OUT The input is sent to the ADC module unit of the power management module 206.

[0049] In this embodiment, the load is a battery with a voltage range of 2.5V-4.4V and a charging current I. VBAT_Charege Finally, a battery is installed, which then powers the entire system.

[0050] In this embodiment, the first charging and logic control unit 204 and the second charging and logic control unit have the same circuit structure. The circuit structure and function of the charging and logic control unit of this application will be described below using the first charging and logic control unit 204 as an example.

[0051] Figure 6 For a schematic diagram of the overall structure of the first charging and logic control unit provided in the embodiments of this application, please refer to [link / reference]. Figure 6 As shown, the charging circuit provided in this embodiment includes: a first transistor unit 31, a second transistor unit 32, a current control unit 33, a voltage regulation control unit 35, and a main control unit 34.

[0052] The input terminals of the first transistor unit 31 and the second transistor unit 32 are both used to receive input voltage. The output terminals of the first transistor unit 31 and the second transistor unit 32 are both connected to the charging output terminal S2, which is used to connect to the input terminal of the first charging channel to output charging current to the first charging channel. The main control unit 34 is used to receive current feedback adjustment signals and output corresponding control voltage signals V_drive according to the current feedback adjustment signals. The control voltage signal V_drive is used to control the first transistor unit 31 and the second transistor unit 32 to output corresponding charging currents. The current control unit 33 is used to sample the input current at the input terminals of each transistor unit and output corresponding current balancing control signals according to the input current to control the charging current output by the first transistor unit 31 and the second transistor unit 32 to achieve balancing. The voltage regulation control unit 35 is used to sample the battery voltage value output at the charging output terminal S2 and output corresponding voltage regulation control signals according to the relationship between the battery voltage value and the preset reference voltage value to control the output charging voltage to stabilize at the reference voltage value.

[0053] According to the charging circuit provided in this embodiment, when an external DC power is input, the first transistor unit 31 and the second transistor unit 32 work simultaneously. The main control unit 34 adjusts the output current of the first transistor unit 31 and the second transistor unit 32 according to the current feedback adjustment signal. At the same time, the current control unit 33 can control the output current values ​​of the first transistor unit 31 and the second transistor unit 32 to achieve balance. The voltage regulation control unit 35 can ensure that the output charging voltage is stable at the target value. In this way, a large charging current and a stable charging voltage can be provided to the electronic device in a balanced manner to ensure the charging speed of the electronic device, thereby realizing rapid power replenishment of the electronic device and solving the battery life problem of the electronic device.

[0054] In one embodiment of this application, the charging circuit further includes a constant current charging unit 36, which is connected to the charging output terminal S2; the main control unit 34 is also used to receive a pre-charge trigger signal fed back from the load terminal, and output a first enable signal to the constant current charging unit 36 ​​according to the pre-charge trigger signal; the constant current charging unit 36 ​​outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0055] Understandably, to protect battery lifespan, battery charging typically includes four stages: pre-charge, constant current charging, constant voltage charging, and trickle / pulses. The charging current is relatively small during the pre-charge and trickle / pulses stages. In this embodiment, to meet the requirements of low-current charging, the aforementioned constant current charging unit 36 ​​is provided. When the battery charging voltage is detected to be low, the main control unit 34 controls the constant current charging unit 36 ​​to operate, diverting a portion of the charging current to a smaller value. This ensures safe charging of the battery during the pre-charge and trickle / pulses stages, thereby guaranteeing battery lifespan.

[0056] In one embodiment of this application, the control signal output pin of the main control unit 34 is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively, so as to output the control voltage signal V_drive to the first transistor unit 31 and the second transistor unit 32, respectively. The control voltage signal V_drive is used to control the magnitude of the current output by the control terminal of the first transistor unit 31 and the second transistor unit 32, that is, the control voltage signal V_drive is used to control the magnitude of the first charging current I1 output by the first transistor unit 31 and the second charging current I2 output by the second transistor unit 32.

[0057] Among them, the main control unit 34 is the main control unit of the charging circuit in this embodiment. It can be a microcontroller unit (MCU) or other types of management chips with control functions.

[0058] In one embodiment of this application, the input terminal of the current control unit 33 is connected to the input terminal of the first transistor unit 31 and the input terminal of the second transistor unit 32, respectively, and the output terminal of the current control unit is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively, so as to output the current balancing control signal to the first transistor unit 31 and the second transistor unit 32, respectively. The current balancing control signal is mainly used to adjust the magnitude of the current flowing through the first transistor unit 31 and the second transistor unit 32, so that the magnitude of the two currents output by the first transistor unit 31 and the second transistor unit 32 is the same, so as to achieve the purpose of current balancing.

[0059] In one embodiment of this application, the input terminals of the first transistor unit 31 and the second transistor unit 32 are both connected to the power input terminal S1, which is used to receive the input current from an external power source. The main control unit 34 includes a charging detection pin, Power-EINT, which is connected to the power input terminal S1 via a third resistor R3 to detect whether an external power source is connected to the power input terminal S1. Based on the detection result, a corresponding indication signal is output. When the indication signal indicates that an external power source is connected, the first transistor unit 31, the second transistor unit 32, and the voltage regulation control unit 35 are controlled to start working, providing a relatively large charging current and a stable charging voltage to the electronic device in a balanced manner, thus ensuring the charging speed of the electronic device. Specifically, the charging detection pin Power-EINT of the main control unit 34 is a charging detection port. When there is a charging power output, the charging detection pin Power-EINT receives a 5V signal from the AC-DC conversion module, thus initiating the charging process of the entire circuit system.

[0060] Figure 7 For a detailed structural diagram of the first charging and logic control unit provided in the embodiments of this application, please refer to [link / reference]. Figure 7 As shown, in one embodiment of this application, the charging circuit further includes a first charging interface for connecting to an external charger; a power input terminal S1 for connecting the first charging interface and the input terminal POWER_A of the first charging channel; a charging output terminal S2 for connecting to the charging terminal of the battery; and a clock signal pin SCL and a data communication pin SDA of the main control unit 34 for connecting to the corresponding clock signal pin and data communication pin on the power management chip 206 for data communication.

[0061] Please continue reading Figure 7As shown, in one embodiment of this application, the first transistor unit 31 includes a first transistor Q1 and a first NMOS (N-Metal-Oxide-Semiconductor) transistor Q3. The emitter of the first transistor Q1 is the input terminal of the first transistor unit 31, and the collector of the first transistor Q1 is the output terminal of the first transistor unit 31. The emitter of the first transistor Q1 is connected to the power input terminal S1, the base of the first transistor Q1 is connected to the drain of the first NMOS transistor Q3, the source of the first NMOS transistor Q3 is the control terminal of the first transistor unit 31, and the source of the first NMOS transistor Q3 is connected to the output terminal of the current control unit 33 and the control signal of the main control unit 34, respectively. The output pins are connected as follows: the gate of the first NMOS transistor Q3 is connected to the power input terminal S1; the second transistor unit 32 includes a second transistor Q2 and a second NMOS transistor Q4. The emitter of the second transistor Q2 is the input terminal of the second transistor unit 32, and the collector of the second transistor Q2 is the output terminal of the second transistor unit 32. The emitter of the second transistor Q2 is connected to the power input terminal S1, the base of the second transistor Q2 is connected to the drain of the second NMOS transistor Q4, the source of the second NMOS transistor Q4 is the control terminal of the second transistor unit 32, and the source of the second NMOS transistor Q4 is connected to the output terminal of the current control unit 33 and the control signal output pin of the main control unit 34, respectively. The gate of the second NMOS transistor Q4 is connected to the power input terminal S1. In this embodiment, both the first transistor Q1 and the second transistor Q2 are PNP type transistors.

[0062] In one embodiment of this application, the charging circuit further includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the power input terminal S1, and the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the first end of the second resistor R2 is connected to the power input terminal S1, and the second end of the second resistor R2 is connected to the emitter of the second transistor Q2; the current control unit 33 includes a first operational amplifier A1, a second operational amplifier A2, and a third operational amplifier A3; the non-inverting input terminal of the first operational amplifier A1 is connected to the first end of the first resistor R1, the inverting input terminal of the first operational amplifier A1 is connected to the second end of the first resistor R1, and the output terminal of the first operational amplifier A1 is connected to the inverting input terminal of the third operational amplifier A3; the non-inverting input terminal of the second operational amplifier A2 is connected to the first end of the second resistor R2, the inverting input terminal of the second operational amplifier A2 is connected to the second end of the second resistor R2, and the output terminal of the second operational amplifier A2 is connected to the non-inverting input terminal of the third operational amplifier A3; the output terminal of the third operational amplifier A3 is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively.

[0063] In one embodiment, the charging circuit further includes a first diode D1, a fourth resistor R4, and a fifth resistor R5. The output terminal of the third operational amplifier A3 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the first terminals of both the fourth and fifth resistors R4 and R5. The second terminal of the fourth resistor R4 is connected to the source of the second NMOS transistor Q4, and the second terminal of the fifth resistor R5 is connected to the source of the first NMOS transistor Q3. The fourth resistor R4 and the fifth resistor R5 are used to adjust the current dynamics between the first transistor unit 31 and the second transistor unit 32 to be equal. The first diode D1 is used to isolate the output of the current control unit 33 and the control voltage signal V_drive output by the main control unit 34 to prevent mutual interference.

[0064] In one scenario, during the charging process, when a difference arises between the first charging current I1 of the first transistor unit 31 and the second charging current I2 of the second transistor unit 32, the gate-source voltage V of the first NMOS transistor Q3 and the second NMOS transistor Q4... GS The situation will be different. In order to keep the first charging current I1 and the second charging current I2 the same, the circuit will automatically adjust the voltage V between the drain and source of the two NMOS transistors through the fifth resistor R5 and the fourth resistor R4. GS This makes the base Ib current of the first NMOS transistor Q3 and the second NMOS transistor Q4 the same, ultimately keeping the first charging current I1 and the second charging current I2 the same and maintaining a dynamic balance.

[0065] Furthermore, the current control unit 33 is used to regulate and manage the charging current balance between the first transistor unit 31 and the second transistor unit 32, and can keep the charging current of the two transistor units basically consistent within a very short response time. Without the current control unit 33, the voltage drop would be different due to the inconsistent impedance of each charging branch during the charging process, which would eventually lead to reverse current flow between the transistor units and affect operation.

[0066] The first charging current I1 flows through the first resistor R1, and the voltage drop across the first resistor R1 is V. R1 The non-inverting and inverting input terminals of the first operational amplifier A1 are connected across the first resistor R1, and the voltage drop V across the first resistor R1 is... R1 By reducing the voltage V R1 After amplification, the output value of the first operational amplifier A1 is input to the inverting input of the third operational amplifier A3. Similarly, the charging current I2 flows through the second resistor R2, and the voltage drop across the second resistor R2 is V. R2The non-inverting and inverting input terminals of the second operational amplifier A2 are connected across the second resistor R2, and the voltage drop across the second resistor R2 is V. R2 By reducing the voltage V R2 After amplification, the output value of the second operational amplifier A2 is input to the non-inverting input terminal of the third operational amplifier A3. The third operational amplifier A3 adjusts the magnitudes of the first charging current I1 and the second charging current I2 through negative feedback by comparing the voltage values ​​across the amplified first resistor R1 and the second resistor R2, ultimately achieving a dynamic balance between the current values ​​of the first charging current I1 and the second charging current I2.

[0067] For transistors, the formula for the current flowing through each of the first transistor Q1 and the second transistor Q2 is: I EC =β×Ib Where β is the amplification factor of each transistor. In this embodiment, the amplification factors of the first transistor Q1 and the second transistor Q2 are the same. Ib is the current flowing through the first NMOS transistor Q3 and the second NMOS transistor Q4. Ib controls the current I flowing through the first transistor Q1 and the second transistor Q2. EC The magnitude of the current, Ib, depends on the conduction level of the first NMOS transistor Q3 and the second NMOS transistor Q4 in this embodiment.

[0068] In one embodiment of this application, please continue to refer to Figure 7 As shown, the constant current charging unit 36 ​​includes a first reference voltage generation chip U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fourth operational amplifier A4, and a third NMOS transistor Q5. The enable terminal of the first reference voltage generation chip U2 is connected to the first enable pin on the main control unit 34. The voltage output pin of the first reference voltage generation chip U2 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is connected to the non-inverting input terminal of the fourth operational amplifier A4 and the first end of the seventh resistor R7, respectively. The second end of the seventh resistor R7 is grounded. The fourth operational amplifier A4... The output terminal is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected to the gate of the third NMOS transistor Q5, the drain of the third NMOS transistor Q5 is connected to the charging output terminal S2, the source of the third NMOS transistor Q5 is connected to the first end of the eighth resistor R8 and the first end of the tenth resistor R10 respectively, the second end of the eighth resistor R8 is connected to the inverting input terminal of the fourth operational amplifier A4, and the second end of the tenth resistor R10 is grounded; the first reference voltage generation chip U2 is used to receive the first enable signal GPIO1 output by the main control unit 34, and output the first reference voltage signal under the trigger of the first enable signal GPIO1.

[0069] In one embodiment, when the first enable signal GPIO1 output by the main control unit 34 is high, the first reference voltage generation chip U2 is turned on and operates. The first reference voltage signal output by the first reference voltage generation chip U2 is VREF_OUT. VREF_OUT is divided by the series-connected sixth resistor R6 and seventh resistor R7, and the voltage after voltage division is used as the input voltage V at the non-inverting input terminal of the fourth operational amplifier A4. a4 In this embodiment, VREF_OUT is set to 2.5V. The input voltage V is obtained after voltage division by the sixth resistor R6 and the seventh resistor R7. a4 The voltage is 1V. At this time, if the voltage V at the positive input terminal of the fourth operational amplifier A4 is... a4 Greater than the negative input voltage V b4 Then the output of the fourth operational amplifier A4 continuously increases, the conduction level of the third NMOS transistor Q5 continuously increases, and the current I... SINK The voltage drop V across the tenth resistor R10 increases, causing it to increase. R10 Increase, voltage drop V R10 The voltage is input to the inverting input of the fourth operational amplifier A4 through the eighth resistor R8 until the voltage at the negative input terminal V... b4 and the positive input voltage V a4 If the currents are the same, the circuit remains balanced. At this time, the current I... SINK The value is I SINK = 1V / R10.

[0070] In one embodiment of this application, the voltage regulation control unit 35 includes a second reference voltage generation chip U3, a fifth operational amplifier A5, a thirteenth resistor R13, a fourteenth resistor R14, and a third PMOS transistor Q6. The enable terminal of the second reference voltage generation chip U3 is connected to the second enable pin on the main control unit 34, the voltage output pin of the second reference voltage generation chip U3 is connected to the non-inverting input terminal of the fifth operational amplifier A5, the output terminal of the fifth operational amplifier A5 is connected to the first terminal of the thirteenth resistor R13, the second terminal of the thirteenth resistor R13 is connected to the drain of the third PMOS transistor Q6, the source of the third PMOS transistor is connected to the power supply pin on the first charging interface 37 and the first terminal of the fourteenth resistor R14, and the second terminal of the fourteenth resistor R14 is connected to the inverting input terminal of the fifth operational amplifier A5. The main control unit 37 is also used to output a second enable signal GPIO2 to the second reference voltage generation chip U3 when an external power supply is detected to be connected to the power input terminal S1. The second reference voltage generation chip U3 is used to output a second reference voltage signal under the trigger of the second enable signal GPIO2.

[0071] Specifically, when the second enable signal GPIO2 output by the main control unit 37 is high, the second reference voltage generation chip U3 outputs a stable second reference voltage signal VREF_OUT_4V. The voltage value of VREF_OUT_4V is 4V, and it serves as the non-inverting input voltage of the fifth operational amplifier A5. The conduction level of the third PMOS transistor Q6 is adjusted and controlled through the operational amplifier's negative feedback to obtain a stable charging voltage VBAT_Charge, for example, VBAT_Charge = 4V. This charging voltage VBAT_Charge is connected to the positive terminal of the battery via a USB cable to charge the battery.

[0072] In one embodiment, when the charging adapter is connected to 220V AC mains power, the 5V voltage output by the AC-DC conversion module is connected to the power input port. The charging detection pin Power-EINT of the main control unit 34 is 5V (this Power-EINT signal is the system's charging detection interrupt signal, used to determine whether the charger is connected. If the charger is connected to AC mains power, Power-EINT is 5V, and the system displays a charging icon; if the charger is not connected to AC mains power, Power-EINT is 0V, and the system does not display a charging icon). After the system detects a valid interruption, it starts charging. The charging drive pin of the main control unit 34 outputs a control voltage signal V_drive, which turns on the first NMOS transistor Q3 and the second NMOS transistor Q4 simultaneously, making them operate in the variable resistance region of the NMOS transistors. The first transistor Q1 and the second transistor Q2 operate in the linear amplification region according to the voltage state. The emitter currents flowing through the first transistor Q1 and the second transistor Q2 are the first charging current I1 and the second charging current I2, respectively. According to the above formula, the functions of the first NMOS transistor Q3 and the second NMOS transistor Q4 are to adjust the emitter currents through the first transistor Q1 and the second transistor Q2 respectively, and ultimately control the actual charging current I. SUM size.

[0073] In this embodiment, the current relationship is I SUM =I1+I2; Additionally, I SUM = I SINK +I BAT_ Charge ; where I SUM It is the sum of the currents output by the first transistor unit 31 and the second transistor unit 32, I SINK I is the current flowing into the constant current charging unit 36 ​​when the constant current charging unit 36 ​​is turned on. BAT_ Charge It is the net current flowing into the battery, which is the actual charging current value.

[0074] After the system detects that the Power-EINT interrupt signal is valid, synchronously... Figure 3The power management chip 206 detects the battery voltage. If the battery voltage is between 2.2V and 3.2V, the system initiates a pre-charging process. At this time, the power management chip 206 transmits a command to the main control unit 34 through the I2C interface signals SDA and SCL. This command sets the first enable signal GPIO1 to a high level. When the first enable signal GPIO1 controlled by the main control unit 34 is high, the first reference voltage generation chip U2 is turned on and operates. The first reference voltage signal output by the first reference voltage generation chip U2 is VREF_OUT. The first reference voltage signal VREF_OUT is divided by the sixth resistor R6 and the seventh resistor R7 connected in series. The voltage after voltage division is used as the input voltage V of the non-inverting input terminal of the fourth operational amplifier A4. a4 In this embodiment, the first reference voltage signal VREF_OUT is set to 2.5V. After being divided by the sixth resistor R6 and the seventh resistor R7, the input voltage V... a4 It is 1V.

[0075] At this time, if the voltage V at the non-inverting input terminal of the fourth operational amplifier A4 a4 Greater than the negative input voltage V b4 As the output of the fourth operational amplifier A4 increases, the conduction level of the third NMOS transistor Q5 also increases, resulting in a current I... SINK The voltage drop V across the tenth resistor R10 increases, causing it to increase. R10 Get bigger, V R10 The voltage is input to the inverting input of the fourth operational amplifier A4 through the eighth resistor R8 until the voltage at the negative input terminal V... b4 and the positive input voltage V a4 If the currents are the same, the circuit remains balanced. At this time, the current I... SINK The value is I SINK = 1V / R10. In this embodiment, the current is I. SINK The pre-charge current value can be obtained by setting different values ​​for the tenth resistor R10, thus obtaining different I values. SINK The current value is used to obtain different pre-charge current values.

[0076] like Figure 3 The power management chip 206 detects that the battery voltage is greater than 3.2V and feeds this information back to the main control unit 34. The main control unit 34 then sets the first enable signal GPIO1 to a low level to control the first reference voltage generation chip U2 to turn off, and the system directly enters the constant current charging stage.

[0077] In one scenario, after the main control unit 34 detects that the interrupt signal Power-EINT is valid, it synchronously sets the output second enable signal GPIO2 to a high level, and the second reference voltage generation chip U3 outputs a stable voltage V.REF_OUT_4V V REF_OUT_4V The voltage is 4V, which serves as the non-inverting input voltage of the fourth operational amplifier A4. Through negative feedback adjustment by the voltage regulation control unit 35, the conduction level of the third PMOS transistor Q6 is controlled to obtain a stable VBAT_Charge voltage value of 4V. This voltage VBAT_Charge is transmitted to the positive terminal of the battery through the first charging channel, charging the battery.

[0078] If the software's preset charging current value is I SW_SET During actual charging, fluctuations in the output power of the charging adapter due to surges or other reasons, or sudden changes in the charging path impedance due to temperature variations, can affect the actual charging current I. BAT_ Charge When fluctuations occur, the ADC module of the power management chip 206 samples a change in the battery voltage at the battery terminal. It then sends this change in battery voltage to the main control unit 34 via a communication signal line. The main control unit 34 adjusts the control voltage signal V_drive output from the signal pin through internal negative feedback, thereby dynamically adjusting the actual charging current I. SUM Based on the above, we can further divide the situation into the following two categories: Scenario 1: If the actual charging current value I BAT_ Charge The charging current value I is greater than the software preset value. SW_SET Then, through negative feedback, the system will increase the voltage value of the control voltage signal V_drive. At this time, the gate-source voltage difference Vgs = Vg - Vs between the first NMOS transistor Q3 and the second NMOS transistor Q4 will decrease. Since the gate-source voltage difference Vgs decreases, the conduction degree of the first NMOS transistor Q3 and the second NMOS transistor Q4 will decrease, and the corresponding on-resistance Rds will increase, thereby reducing the base current Ib. According to the above formula, the current I between the emitter and collector of the first transistor Q1 and the second transistor Q2 will increase. EC It will decrease. Ultimately, the actual charging current of the circuit in this embodiment will decrease and eventually adjust to I. BAT_ Charge =I SW_SET Until then, the control voltage signal V_drive voltage value no longer changes and reaches dynamic equilibrium.

[0079] Scenario 2: If the actual charging current value I BAT_ Charge Less than the software-preset charging current value I SW_SETThen, through negative feedback, the system will lower the voltage value of the control voltage signal V_drive. At this time, the gate-source voltage difference Vgs = Vg - Vs of the first NMOS transistor Q3 and the second NMOS transistor Q4 will increase. Since the gate-source voltage difference Vgs increases, the conduction degree of the first NMOS transistor Q3 and the second NMOS transistor Q4 will be enhanced, and the corresponding on-resistance Rds will decrease, thereby increasing the base current Ib. According to formula (1), the current I between the emitter and collector of the first transistor Q1 and the second transistor Q2 will increase. EC It will increase; ultimately, the actual charging current of the circuit in this embodiment will increase, and will eventually adjust to I. BAT_ Charge =I SW_SET The control voltage signal V_drive voltage value no longer changes and reaches dynamic equilibrium.

[0080] In one scenario, during the charging process, when a difference arises between the first charging current I1 of the first transistor unit 31 and the second charging current I2 of the second transistor unit 32, the gate-source voltage VGS of the first NMOS transistor Q3 and the second NMOS transistor Q4 will be different. In order to keep the first charging current I1 and the second charging current I2 the same, the circuit will automatically adjust the gate-source voltage difference Vgs of the first NMOS transistor Q3 and the second NMOS transistor Q4 through the fifth resistor R5 and the fourth resistor R4, so that the base current Ib of the first NMOS transistor Q3 and the second NMOS transistor Q4 are the same, and finally keep the first charging current I1 and the second charging current I2 the same and maintain a dynamic balance state.

[0081] Furthermore, the first charging current I1 flows through the first resistor R1, and the voltage drop across the first resistor R1 is V. R1 The non-inverting and inverting input terminals of the first operational amplifier A1 are connected across the first resistor R1 to sample the voltage drop V across the first resistor R1. R1 By reducing the voltage V R1 After amplification, the output value of the first operational amplifier A1 is input to the inverting input of the third operational amplifier A3. Similarly, the second charging current I2 flows through the second resistor R2, and the voltage drop across the second resistor R2 is V. R2 The non-inverting and inverting input terminals of the second operational amplifier A2 are connected across the second resistor R2 to sample the voltage drop V across the second resistor R2. R2 By reducing the voltage V R2 After amplification, the output value of the second operational amplifier A2 is input to the non-inverting input terminal of the third operational amplifier A3. The third operational amplifier A3 adjusts the currents of the first charging current I1 and the second charging current I2 through negative feedback by comparing the voltage values ​​across the amplified first resistor R1 and the second resistor R2, and finally makes the current values ​​of the first charging current I1 and the second charging current I2 dynamically balanced.

[0082] It is understandable that since the circuit structure of the second charging and logic control unit is exactly the same as that of the first charging and logic control unit 204, it will not be described again here.

[0083] When a second charging and logic control unit is detected at the charger end, the power management chip 206 outputs a fourth enable signal GPIO4 to control the second charging channel to turn on. At this time, the power management chip 206 establishes a communication connection with the main control unit in the second charging and logic control unit to control the second charging and logic control unit to output an appropriate charging voltage and charging current to the battery. In this way, the first charging and logic control unit 204 inside the electronic device is in a disconnected state. This reduces the impact of the heat generated by the first charging and logic control unit 204 during charging, that is, the heat dissipation source is transferred to the outside of the electronic device. This physical heat source isolation strategy significantly suppresses the internal heat dissipation of the electronic device during the charging cycle, thereby greatly optimizing the user interaction experience. At the same time, it avoids the technical problem of electromagnetic interference caused by the first charging and logic control unit 204 when it is working, making this solution suitable for precision instruments or sensitive electronic devices with strict requirements for electromagnetic noise environment.

[0084] This application provides a power adapter, which includes a charging circuit as provided in any of the above embodiments; thus, the power adapter provided in this embodiment is as follows: Figure 2As shown, the charging dock 2000 and charging converter 201 in the power adapter provided in this embodiment can be integrated or separate designs. The charging converter 201 is provided with a second charging and logic control unit, which includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, a constant current charging unit, and a main control unit. The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage, and the output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to the second charging interface to output charging current to the second charging interface. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit. The first transistor unit and the second transistor unit output corresponding charging currents; the current control unit is used to sample the input current at the input terminal of each transistor unit, and output a corresponding current balancing control signal according to the input current to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing; the voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value to control the output charging voltage to stabilize at the reference voltage value; the constant current charging unit is connected to the charging output terminal; the main control unit is also used to receive the pre-charge trigger signal fed back from the load terminal, and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal; the constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0085] The circuit structure and function of the second charging and logic control unit can be referred to the first charging and logic control unit 204 above. The power adapter can provide a stable and balanced charging current for electronic devices, while reducing the heat generated by the device during charging, improving the user experience and extending the service life of electronic devices.

[0086] It should be noted that the charging circuit provided in this application can be applied to electronic devices to provide a stable and balanced charging current for the battery, and the dual-output can increase the charging current value to improve the charging speed; at the same time, the charging circuit provided in this embodiment can also be applied to power adapters, so that the power adapter can provide a stable and balanced charging current for electronic devices, while reducing the heat generated by the device during charging.

[0087] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charging circuit for use in an electronic device, wherein the electronic device is provided with a first charging interface, characterized in that, The charging circuit includes a first charging and logic control unit, a power switching unit, and a power management chip. The input terminal of the first charging and logic control unit is connected to the first charging interface. The power switching unit includes a first charging channel and a second charging channel. The output terminal of the first charging and logic control unit is connected to the input terminal of the first charging channel of the power switching unit. The input terminal of the second charging channel of the power switching unit is also connected to the first charging interface. The output terminals of the first charging channel and the second charging channel are both connected to the charging terminal of the battery. The power management chip is connected to a detection pin on the first charging interface. The detection pin is used to detect whether a second charging and logic control unit is connected to the first charging interface, and outputs an interrupt signal according to the detection result. The power management chip is used to control the first charging channel or the second charging channel to be turned on according to the interrupt signal so as to charge the battery.

2. The charging circuit according to claim 1, characterized in that, The charging circuit also includes a current detection module and a voltage detection module; The sampling end of the current detection module is connected to the second charging channel. The current detection module is used to detect the charging current flowing through the second charging channel. The power management chip is used to generate a corresponding current feedback adjustment signal based on the relationship between the charging current and the target charging current, and output the current feedback adjustment signal to the first charging and logic control unit or the second charging and logic control unit. The sampling end of the voltage detection module is connected to the charging end of the battery. The voltage detection module is used to detect the charging voltage of the charging end of the battery and send the charging voltage to the power management chip. The power management chip is used to monitor the charging voltage of the battery. The first charging and logic control unit or the second charging and logic control unit is used to output a corresponding charging current according to the current feedback adjustment signal.

3. The charging circuit according to claim 2, characterized in that, The power switching unit includes a seventh PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth NMOS transistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a twenty-first resistor; The seventh PMOS transistor, the eighth NMOS transistor, the sixteenth resistor, the seventeenth resistor, and the eighteenth resistor constitute the first charging channel. The source of the seventh PMOS transistor is the input terminal of the first charging channel. The source of the seventh PMOS transistor is connected to the output terminal of the first charging and logic control unit and the first terminal of the sixteenth resistor. The drain of the seventh PMOS transistor is connected to the charging terminal of the battery. The gate of the seventh PMOS transistor is connected to the second terminal of the sixteenth resistor and the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the first terminal of the eighteenth resistor and a common ground. The second terminal of the eighteenth resistor is connected to the gate of the eighth NMOS transistor and the first terminal of the seventeenth resistor. The second terminal of the seventeenth resistor is used to receive a third enable signal, which is used to control the first charging channel to be turned on or off. The ninth PMOS transistor, the tenth NMOS transistor, the nineteenth resistor, the twentieth resistor, and the twenty-first resistor constitute the second charging channel. The source of the ninth PMOS transistor is the input terminal of the second charging channel. The source of the ninth PMOS transistor is connected to the first charging interface and the first terminal of the nineteenth resistor. The drain of the ninth PMOS transistor is also connected to the charging terminal of the battery. The gate of the ninth PMOS transistor is connected to the second terminal of the nineteenth resistor and the drain of the tenth NMOS transistor. The source of the tenth NMOS transistor is connected to the first terminal of the twenty-first resistor and a common ground. The second terminal of the twenty-first resistor is connected to the gate of the tenth NMOS transistor and the first terminal of the twenty-first resistor. The second terminal of the twenty-first resistor is used to receive a fourth enable signal, which is used to control the second charging channel to be turned on or off.

4. The charging circuit according to claim 3, characterized in that, The first charging and logic control unit and the second charging and logic control unit have the same structure; The first charging and logic control unit includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, a constant current charging unit, and a main control unit; The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage. The output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to the input terminal of the first charging channel to output charging current to the first charging channel. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit and the second transistor unit to output corresponding charging currents. The current control unit is used to sample the input current at the input terminal of each transistor unit and output a corresponding current balancing control signal according to the input current, so as to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing. The voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value, so as to control the output charging voltage to be stable at the reference voltage value. The constant current charging unit is connected to the charging output terminal. The main control unit is also used to receive a pre-charge trigger signal fed back from the load terminal and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal. The constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

5. The charging circuit according to claim 4, characterized in that, The control signal output pin of the main control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit respectively, so as to output the control voltage signal to the first transistor unit and the second transistor unit respectively; The input terminal of the current control unit is connected to the input terminal of the first transistor unit and the input terminal of the second transistor unit, respectively, and the output terminal of the current control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively, so as to output the current equalization control signal to the first transistor unit and the second transistor unit, respectively. The main control unit includes a charging detection pin, which is connected to the power input terminal to detect whether an external power source is connected to the power input terminal, and outputs a corresponding indication signal according to the detection result; and when the indication signal indicates that an external power source is connected, it controls the first transistor unit, the second transistor unit and the voltage regulation control unit to start working. The input terminals of the first transistor unit and the second transistor unit are both connected to the power input terminal, which is used to receive the input current from an external power source.

6. The charging circuit according to claim 5, characterized in that, The first transistor unit includes a first transistor and a first NMOS transistor. The emitter of the first transistor is the input terminal of the first transistor unit, and the collector of the first transistor is the output terminal of the first transistor unit. The emitter of the first transistor is connected to the power input terminal, the base of the first transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is the control terminal of the first transistor unit, the source of the first NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the first NMOS transistor is connected to the power input terminal. The second transistor unit includes a second transistor and a second NMOS transistor. The emitter of the second transistor is the input terminal of the second transistor unit, and the collector of the second transistor is the output terminal of the second transistor unit. The emitter of the second transistor is connected to the power input terminal, the base of the second transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is the control terminal of the second transistor unit, the source of the second NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the second NMOS transistor is connected to the power input terminal. The first charging and logic control unit further includes a first resistor and a second resistor; a first end of the first resistor is connected to the power input terminal, and a second end of the first resistor is connected to the emitter of the first transistor; a first end of the second resistor is connected to the power input terminal, and a second end of the second resistor is connected to the emitter of the second transistor. The current control unit includes a first operational amplifier, a second operational amplifier, and a third operational amplifier; the non-inverting input terminal of the first operational amplifier is connected to the first terminal of the first resistor, the inverting input terminal of the first operational amplifier is connected to the second terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the third operational amplifier. The non-inverting input of the second operational amplifier is connected to the first end of the second resistor, the inverting input of the second operational amplifier is connected to the second end of the second resistor, and the output of the second operational amplifier is connected to the non-inverting input of the third operational amplifier; the output of the third operational amplifier is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively.

7. The charging circuit according to claim 6, characterized in that, The constant current charging unit includes a first reference voltage generation chip, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth operational amplifier, and a third NMOS transistor. The enable terminal of the first reference voltage generation chip is connected to a first enable pin on the main control unit. The voltage output pin of the first reference voltage generation chip is connected to a first terminal of the sixth resistor. The second terminal of the sixth resistor is connected to both the non-inverting input terminal of the fourth operational amplifier and the first terminal of the seventh resistor. The second terminal of the seventh resistor is grounded. The output terminal of the fourth operational amplifier is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to the charging output terminal. The source of the third NMOS transistor is connected to both the first terminals of the eighth and tenth resistors. The second terminal of the eighth resistor is connected to the inverting input terminal of the fourth operational amplifier. The second terminal of the tenth resistor is grounded. The first reference voltage generation chip receives a first enable signal output by the main control unit and outputs a first reference voltage signal upon triggering the first enable signal. The voltage regulation and control unit includes a second reference voltage generation chip, a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor, and a third PMOS transistor. The enable terminal of the second reference voltage generation chip is connected to the second enable pin on the main control unit. The voltage output pin of the second reference voltage generation chip is connected to the non-inverting input terminal of the fifth operational amplifier. The output terminal of the fifth operational amplifier is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the power supply pin on the first charging interface and the first terminal of the fourteenth resistor. The second terminal of the fourteenth resistor is connected to the inverting input terminal of the fifth operational amplifier. The main control unit is further configured to output a second enable signal to the second reference voltage generation chip when an external power supply is detected to be connected to the power input terminal; the second reference voltage generation chip is configured to output a second reference voltage signal when triggered by the second enable signal.

8. An electronic device, characterized in that, The electronic device includes a charging circuit as described in any one of claims 1-7.

9. A charging device, characterized in that, The charging device includes a charging base and a charging converter, which are pluggable and detachable connected via a compatible charging interface. The charging base is equipped with an AC-DC conversion module, which includes a rectifier and filter circuit, a high-frequency voltage converter, and a DC converter. The AC-DC conversion module is used to rectify and convert the input AC power. The charging converter is provided with a second charging interface, which is pluggably connected to the first charging interface on the electronic device; the charging converter is provided with a second charging and logic control unit, which is used to receive control signals fed back from the electronic device to process the DC power output by the AC-DC conversion module in order to output an appropriate charging voltage and charging current.

10. The charging device according to claim 9, characterized in that, The second charging and logic control unit includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, a constant current charging unit, and a main control unit; The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage. The output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to the second charging interface to output charging current to the second charging interface. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit and the second transistor unit to output corresponding charging currents. The current control unit is used to sample the input current at the input terminal of each transistor unit and output a corresponding current balancing control signal according to the input current, so as to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing. The voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value, so as to control the output charging voltage to be stable at the reference voltage value. The constant current charging unit is connected to the charging output terminal. The main control unit is also used to receive a pre-charge trigger signal fed back from the load terminal and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal. The constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

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