High-speed interstage gain amplifier based on source driving

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed interstage gain amplifier based on source driving. The circuit comprises an input stage driven by a push-pull source electrode, a variable impedance module and a push-pull output stage. According to the push-pull type source electrode driving input stage, the four independent buffers are used for driving the source electrodes of the input transistors respectively, the transconductance of the input stage is improved to be four times that of a traditional scheme, and higher bandwidth and speed are achieved. Meanwhile, the input stage avoids the problem that the slew rate is limited by the current of the input stage in the traditional scheme, so that a higher slew rate can be realized. The impedance of the variable impedance module is relatively low in a static state, so that a relatively far secondary pole is realized, and the phase margin of the amplifier is ensured. When the input swing is large, the module realizes high impedance, and the grid voltage swing of the output stage is improved, so that the output current is expanded, and the overall speed of the amplifier is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a high-speed interstage gain amplifier based on source-driven operation. Background Technology

[0002] With the rapid development of modern wireless communication, autonomous driving, and satellite navigation, high-speed analog-to-digital converters (ADCs) are becoming increasingly important. Due to their parallel operation characteristics, pipelined ADCs are particularly well-suited for these applications. As a key module in a pipelined ADC, the speed and power consumption of the interstage gain amplifier determine the performance of the entire ADC system.

[0003] Traditional interstage gain amplifiers employ a two-stage topology: a first-stage sleeve amplifier and a second-stage common-source output amplifier, to achieve high DC gain and a wide output swing. However, this structure requires a very high supply voltage due to the stacking of five or more transistors between power and ground. Furthermore, the amplifier's high internal impedance necessitates the addition of Miller compensation capacitors to ensure phase margin, preventing the achievement of high speeds at lower power consumption and limiting its applications. Summary of the Invention

[0004] To address the issues of low speed and high power consumption in traditional interstage gain amplifiers, this invention proposes a high-speed interstage gain amplifier based on source-driven technology, such as... Figure 1 As shown. This invention employs input-stage source-driven technology, using a buffer to drive the source of the input transistor, effectively increasing the input transconductance and significantly increasing the maximum current of the input stage, thereby improving the overall small-signal speed and slew rate. Simultaneously, both the input and output stages of this invention adopt a push-pull architecture, increasing the transconductance by four times under the same power consumption, significantly improving speed. Furthermore, this invention removes all tail-current transistors, avoiding the problem of limited slew rate, and ensures output common-mode robustness through local common-mode negative feedback.

[0005] In addition, to address the issue of amplifier phase margin, this invention introduces a variable resistor module between the input and output stages. This variable resistor has a small impedance during static and small swing conditions, resulting in a larger secondary pole of the amplifier, thus ensuring phase margin and stability. During large signal conditions, the impedance value is larger and provides additional gain, thereby accelerating the establishment of a large swing and improving overall performance.

[0006] The technical solution of this invention is:

[0007] A high-speed interstage gain amplifier based on source-driven technology includes a first NMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth PMOS transistor M20, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0008] The gate of the first NMOS transistor M1 and the gate of the second PMOS transistor M2 are connected to the positive terminal of the differential input signal. The source of the first NMOS transistor M1 is connected to the output of the first buffer B1, the source of the second PMOS transistor M2 is connected to the output of the second buffer B2, and the drain of the first NMOS transistor M1 and the drain of the second PMOS transistor M2 are connected to the gate of the fifth NMOS transistor M5.

[0009] The gate of the third NMOS transistor M3, the gate of the fourth PMOS transistor M4, the input of the first buffer B1, the input of the second PMOS transistor M2, the input of the third buffer B3, and the input of the fourth buffer B4 are connected to the negative terminal of the differential input signal; the source of the third NMOS transistor M3 is connected to the output of the third buffer B3, the source of the fourth PMOS transistor M4 is connected to the output of the fourth buffer B4, and the drain of the third NMOS transistor M3 and the drain of the fourth PMOS transistor M4 are connected to the gate of the ninth NMOS transistor M9.

[0010] The gate of the fifth NMOS transistor M5 is connected to the gate of the eighth PMOS transistor M8. The source of the fifth NMOS transistor M5 is grounded, and the source of the eighth PMOS transistor M8 is connected to the power supply. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6. The drain of the eighth PMOS transistor M8 is connected to the source of the seventh PMOS transistor M7. The drains of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected together. The gates of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected to the drain of the tenth NMOS transistor M10.

[0011] The gate of the ninth NMOS transistor M9 and the gate of the twelfth PMOS transistor M12 are connected together. The source of the ninth NMOS transistor M9 is grounded. The source of the twelfth PMOS transistor M12 is connected to the power supply. The drain of the ninth NMOS transistor M9 is connected to the source of the tenth NMOS transistor M10. The drain of the twelfth PMOS transistor M12 is connected to the source of the eleventh PMOS transistor M11. The drains of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected together. The gates of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected to the drain of the sixth NMOS transistor M6.

[0012] The gate of the thirteenth NMOS transistor M13 is connected to the gate of the fourteenth PMOS transistor M14 through the first capacitor C1 and the second capacitor C2. The source of the thirteenth NMOS transistor M13 is grounded, and the source of the fourteenth PMOS transistor M14 is connected to the power supply. The drains of the thirteenth NMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth NMOS transistor M15, and the sixteenth PMOS transistor M16 are connected together. The gates of the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 are connected together and simultaneously connected to the common-mode output voltage. The source of the fifteenth NMOS transistor M15 is grounded, and the source of the sixteenth PMOS transistor M16 is connected to the power supply.

[0013] The gate of the seventeenth NMOS transistor M17 is connected to the gate of the eighteenth PMOS transistor M18 through the third capacitor C3 and the fourth capacitor C4. The source of the seventeenth NMOS transistor M17 is grounded, and the source of the eighteenth PMOS transistor M18 is connected to the power supply. The drains of the seventeenth NMOS transistor M17, the eighteenth PMOS transistor M18, the nineteenth NMOS transistor M19, and the twentieth PMOS transistor M20 are connected together. The gates of the nineteenth NMOS transistor M19 and the twentieth PMOS transistor M20 are connected together and simultaneously connected to the common-mode output voltage. The source of the nineteenth NMOS transistor M19 is grounded, and the source of the twentieth PMOS transistor M20 is connected to the power supply.

[0014] The beneficial effects of this invention are as follows:

[0015] This invention employs a push-pull input source driving technique, using first to fourth buffers B1-B4 to drive the sources of first to fourth transistors M1-M4 respectively, thereby increasing the transconductance of the input stage to four times that of conventional schemes, achieving higher bandwidth and speed. The transconductance of the input stage can be expressed as...

[0016]

[0017] in, This represents the equivalent transconductance of the input stage. and These represent the transconductance of NMOS and PMOS, respectively. and These represent positive and negative input signals, respectively.

[0018] This invention avoids the problem of slew rate being limited by the input stage current in traditional solutions by removing the tail current source. With large-swing input signals, since there is no fixed tail current source, the amplifier's input stage current is no longer limited by the current source, thus enabling a larger slew rate and improving amplifier speed.

[0019] This invention designs a variable impedance module, namely transistors M5-M8 and transistors M9-M10. When the input swing is small, i.e., in the static state, this module has a low impedance, thus achieving a farther secondary pole and ensuring the phase margin of the amplifier. When the input swing is large, due to the disruption of the negative feedback loop, this module achieves a higher impedance, increasing the gate voltage swing of the output stage, thereby expanding the output current and improving the slew rate and speed. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the specific circuit structure of a high-speed interstage gain amplifier based on source-driven technology proposed in this invention in an embodiment.

[0021] Figure 2 This is a simulation diagram of the slew rate of the high-speed interstage gain amplifier based on source-driven technology of the present invention.

[0022] Figure 3 This is a simulation diagram of the settling time of the high-speed interstage gain amplifier based on source-driven technology according to the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0024] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. For example, "first connection terminal" and "second connection terminal" of a capacitor and resistor simply refer to two connection terminals of the capacitor and resistor, and the first connection terminal and the second connection terminal can be interchanged.

[0025] like Figure 1As shown, this invention proposes a high-speed interstage gain amplifier based on source-driven technology, comprising a first NMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth PMOS transistor M20, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. Wherein,

[0026] The gate of the first NMOS transistor M1 and the gate of the second PMOS transistor M2 are connected together as an input terminal. The source of the first NMOS transistor M1 is connected to the output of the first buffer B1, the source of the second PMOS transistor M2 is connected to the output of the second buffer B2, and the drain of the first NMOS transistor M1 and the drain of the second PMOS transistor M2 are connected together and both are connected to the gate of the fifth NMOS transistor M5.

[0027] The gate of the third NMOS transistor M3 and the gate of the fourth PMOS transistor M4 are connected together as an input terminal. The source of the third NMOS transistor M3 is connected to the output of the first buffer B3, the source of the fourth PMOS transistor M4 is connected to the output of the second buffer B4, and the drain of the third NMOS transistor M3 and the drain of the fourth PMOS transistor M4 are connected together and connected to the gate of the ninth NMOS transistor M9.

[0028] The gate of the fifth NMOS transistor M5 is connected to the gate of the eighth PMOS transistor M8. The source of the fifth NMOS transistor M5 is grounded, and the source of the eighth PMOS transistor M8 is connected to the power supply. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6, and the drain of the eighth PMOS transistor M8 is connected to the source of the seventh PMOS transistor M7. The drains of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected together. The gates of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected together and connected to the drain of the tenth NMOS transistor M10.

[0029] The gate of the ninth NMOS transistor M9 and the gate of the twelfth PMOS transistor M12 are connected together. The source of the ninth NMOS transistor M9 is grounded. The source of the twelfth PMOS transistor M12 is connected to the power supply. The drain of the ninth NMOS transistor M9 is connected to the source of the tenth NMOS transistor M10. The drain of the twelfth PMOS transistor M12 is connected to the source of the eleventh PMOS transistor M11. The drains of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected together. The gates of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected together and connected together to the drain of the sixth NMOS transistor M6.

[0030] The gate of the thirteenth NMOS transistor M13 is connected to the gate of the fourteenth PMOS transistor M14 through the first capacitor C1 and the second capacitor C2. The source of the thirteenth NMOS transistor M13 is grounded, and the source of the fourteenth PMOS transistor M14 is connected to the power supply. The drains of the thirteenth NMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth NMOS transistor M15, and the sixteenth PMOS transistor M16 are connected together. The gates of the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 are connected together and simultaneously connected to the common-mode output voltage. The source of the fifteenth NMOS transistor M15 is grounded, and the source of the sixteenth PMOS transistor M16 is connected to the power supply.

[0031] The gate of the seventeenth NMOS transistor M17 is connected to the gate of the eighteenth PMOS transistor M18 through the third capacitor C3 and the fourth capacitor C4. The source of the seventeenth NMOS transistor M17 is grounded, and the source of the eighteenth PMOS transistor M18 is connected to the power supply. The drains of the seventeenth NMOS transistor M17, the eighteenth PMOS transistor M18, the nineteenth NMOS transistor M19, and the twentieth PMOS transistor M20 are connected together. The gates of the nineteenth NMOS transistor M19 and the twentieth PMOS transistor M20 are connected together and simultaneously connected to the common-mode output voltage. The source of the nineteenth NMOS transistor M19 is grounded, and the source of the twentieth PMOS transistor M20 is connected to the power supply.

[0032] The cutoff frequency of the high-pass circuit formed by the first capacitor C1 and the first resistor R1 is less than 1 / 100 of the open-loop GBW of the interstage gain amplifier. The cutoff frequency of the high-pass circuit formed by the second capacitor C2 and the second resistor R2 is less than 1 / 100 of the open-loop GBW of the interstage gain amplifier. The cutoff frequency of the high-pass circuit formed by the third capacitor C3 and the third resistor R3 is less than 1 / 100 of the open-loop GBW of the interstage gain amplifier. The cutoff frequency of the high-pass circuit formed by the fourth capacitor C4 and the fourth resistor R4 is less than 1 / 100 of the open-loop GBW of the interstage gain amplifier.

[0033] This invention proposes a push-pull input stage transistor source driving technology, which uses the first to fourth buffers B1-B4 to drive the sources of the first to fourth transistors M1-M4 respectively, thereby increasing the transconductance of the input stage to four times that of the traditional scheme, achieving higher bandwidth and speed.

[0034] This invention avoids the problem of slew rate being limited by input stage current in traditional solutions. Under large-slew input signals, since the tail current source is removed, the amplifier's input stage current is no longer limited by the current source, thereby achieving a larger slew rate and improving amplifier speed.

[0035] This invention introduces a variable impedance circuit module, namely transistors M5-M8 and M9-12, between the input and output stages, avoiding the use of large-area Miller capacitors and further improving amplifier speed. This module exhibits low impedance during the quiescent phase (small input swing), achieving a wider secondary pole and ensuring phase margin. During the quiescent phase (large input swing), the module achieves higher impedance due to the disruption of the negative feedback loop, increasing the gate voltage swing of the output stage, thereby expanding the output current and improving slew rate and speed.

[0036] The transistors in this invention are biased in the subthreshold region, which further improves speed and efficiency.

[0037] See Figure 2 As shown, the amplifier slew rate was tested at five different process angles. This invention enables a rapid rise in output voltage, with a slew rate of 16100 V / µs at the TT process angle, demonstrating the effectiveness of the slew rate and speed enhancement techniques.

[0038] See Figure 3 As shown, the amplifier settling time was tested under five different process corners. The settling time of this invention under the TT process corner was 180 ps, ​​with a static power consumption of 4.5 mW and a load capacitance of 600 fF. Furthermore, the settling speed under the worst process corner (SS / 0.95 V / −40 °C) was less than 30% lower than that under the TT process corner, demonstrating the effectiveness of this invention.

[0039] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-speed interstage gain amplifier based on source-driven technology, comprising a first NMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth PMOS transistor M20, a first buffer B1, a second buffer B2, a third buffer B3, a fourth buffer B4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; wherein, The gate of the first NMOS transistor M1 and the gate of the second PMOS transistor M2 are connected to the positive terminal of the differential input signal. The source of the first NMOS transistor M1 is connected to the output of the first buffer B1, the source of the second PMOS transistor M2 is connected to the output of the second buffer B2, and the drain of the first NMOS transistor M1 and the drain of the second PMOS transistor M2 are connected to the gate of the fifth NMOS transistor M5. The gate of the third NMOS transistor M3, the gate of the fourth PMOS transistor M4, the input of the first buffer B1, the input of the second PMOS transistor M2, the input of the third buffer B3, and the input of the fourth buffer B4 are connected to the negative terminal of the differential input signal; the source of the third NMOS transistor M3 is connected to the output of the third buffer B3, the source of the fourth PMOS transistor M4 is connected to the output of the fourth buffer B4, and the drain of the third NMOS transistor M3 and the drain of the fourth PMOS transistor M4 are connected to the gate of the ninth NMOS transistor M9. The gate of the fifth NMOS transistor M5 is connected to the gate of the eighth PMOS transistor M8. The source of the fifth NMOS transistor M5 is grounded, and the source of the eighth PMOS transistor M8 is connected to the power supply. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6. The drain of the eighth PMOS transistor M8 is connected to the source of the seventh PMOS transistor M7. The drains of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected together. The gates of the sixth NMOS transistor M6 and the seventh PMOS transistor M7 are connected to the drain of the tenth NMOS transistor M10. The gate of the ninth NMOS transistor M9 and the gate of the twelfth PMOS transistor M12 are connected together. The source of the ninth NMOS transistor M9 is grounded. The source of the twelfth PMOS transistor M12 is connected to the power supply. The drain of the ninth NMOS transistor M9 is connected to the source of the tenth NMOS transistor M10. The drain of the twelfth PMOS transistor M12 is connected to the source of the eleventh PMOS transistor M11. The drains of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected together. The gates of the tenth NMOS transistor M10 and the eleventh PMOS transistor M11 are connected to the drain of the sixth NMOS transistor M6. The gate of the thirteenth NMOS transistor M13 is connected to the gate of the fourteenth PMOS transistor M14 through the first capacitor C1 and the second capacitor C2. The source of the thirteenth NMOS transistor M13 is grounded, and the source of the fourteenth PMOS transistor M14 is connected to the power supply. The drains of the thirteenth NMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth NMOS transistor M15, and the sixteenth PMOS transistor M16 are connected together. The gates of the fifteenth NMOS transistor M15 and the sixteenth PMOS transistor M16 are connected together and simultaneously connected to the common-mode output voltage. The source of the fifteenth NMOS transistor M15 is grounded, and the source of the sixteenth PMOS transistor M16 is connected to the power supply. The gate of the seventeenth NMOS transistor M17 is connected to the gate of the eighteenth PMOS transistor M18 through the third capacitor C3 and the fourth capacitor C4. The source of the seventeenth NMOS transistor M17 is grounded, and the source of the eighteenth PMOS transistor M18 is connected to the power supply. The drains of the seventeenth NMOS transistor M17, the eighteenth PMOS transistor M18, the nineteenth NMOS transistor M19, and the twentieth PMOS transistor M20 are connected together. The gates of the nineteenth NMOS transistor M19 and the twentieth PMOS transistor M20 are connected together and simultaneously connected to the common-mode output voltage. The source of the nineteenth NMOS transistor M19 is grounded, and the source of the twentieth PMOS transistor M20 is connected to the power supply.

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