Device and method for detecting burst signal of navigation management receiving channel

Abstract

The invention discloses a device for detecting burst signals of a navigation management receiving channel, and relates to the technical field of navigation management application. The equipment comprises a field programmable gate array (FPGA) which is connected with an analog-to-digital converter of the navigation management equipment and used for processing digital intermediate frequency signals output by the analog-to-digital converter of the navigation management equipment so as to obtain time domain information and frequency domain information of burst signals in the digital intermediate frequency signals, and the FPGA is the FPGA of the navigation management equipment; and the display module unit is connected with the FPGA and is used for receiving and displaying the time domain information and the frequency domain information of the burst signal. According to the method, the receiving channel problem can be quickly positioned by design and testing personnel, and the receiving channel signal monitoring efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of air traffic control application technology, specifically to an air traffic control receiving channel burst signal detection device and method. Background Technology

[0002] With the development of wireless communication, especially the emergence of software-defined radio, superheterodyne receivers are being used more and more widely in the field of air traffic control communication, and the need for rapid monitoring of analog and digital receiving channels is becoming more and more urgent.

[0003] Traditional testing methods primarily rely on intermediate frequency (IF) measurements (spectrum analyzer testing) and digital signal observation (logic probe observation). These methods are cumbersome, and setting up the test environment is extremely resource-intensive. For example, traditional methods for detecting burst signals in the receiver channel require specialized equipment, such as a spectrum analyzer or oscilloscope, to acquire the input signal. Testing analog-to-digital sampling channels requires computer equipment with specialized software for acquisition, which is expensive, difficult to set up, and involves complex wiring. After the module assembly is complete, testing may become even more challenging and inefficient, and the raw test data is difficult to save synchronously. Summary of the Invention

[0004] This invention addresses the problems of complex detection methods, high testing costs, and low efficiency in detecting burst signals in the receiving channel of a superheterodyne receiver. It provides a time-domain and frequency-domain detection device and method for burst signals in the receiving channel of air traffic control, which facilitates designers and testers in quickly locating problems in the receiving channel and improves the efficiency of receiving channel signal monitoring.

[0005] The present invention is achieved through the following technical solution.

[0006] In a first aspect, the present invention provides a burst signal detection device for air traffic control receiving channels, the device comprising:

[0007] A field-programmable gate array (FPGA) is connected to an analog-to-digital converter (ADC) in the air traffic control equipment. It is used to process the digital intermediate frequency (IF) signal output by the ADC of the air traffic control equipment to obtain the time-domain and frequency-domain information of burst signals in the digital IF signal. The FPGA is the FPGA of the air traffic control equipment.

[0008] The display module unit, connected to the FPGA, is used to receive and display the time-domain and frequency-domain information of the burst signal.

[0009] In some embodiments, the FPGA includes: a burst signal detection unit, wherein the burst signal detection unit includes:

[0010] The data processing module is connected to the analog-to-digital converter of the air traffic control equipment and is used to process the digital intermediate frequency signal output by the analog-to-digital converter to obtain the frequency domain information of the digital intermediate frequency signal.

[0011] The window energy calculation module is connected to the analog-to-digital converter of the air traffic control equipment and is used to calculate the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter using the double sliding window method.

[0012] The decision module, connected to the window energy calculation module, is used to perform burst signal detection based on the window energy value to generate a burst signal detection flag signal, wherein the burst signal detection flag signal is used to indicate valid buffered output data;

[0013] The data caching module is connected to the analog-to-digital converter, the data processing module, and the decision module, respectively, and is used to cache and output the time-domain information and frequency-domain information of the burst signal in the digital intermediate frequency signal under the indication of the burst signal detection flag signal and the frequency-domain information of the digital intermediate frequency signal.

[0014] In some embodiments, the dual sliding window method includes employing a first window and a second window, the first window and the second window being relatively stationary. The digital intermediate frequency signal first enters the first window and then enters the second window. The decision module performs burst signal detection based on the following formula:

[0015] m[n] = EA[n] / EB[n];

[0016] Where EA[n] represents the energy value of the nth first window A; EB[n] represents the energy value of the nth second window B;

[0017] Wherein, when m[n] is greater than the preset threshold, a maximum value detection is performed on m[n], and the detection of the maximum value is considered to be the start time of the detected signal; when the decision value m[n] is less than the preset threshold, a minimum value detection is performed on m[n], and the detection of the minimum value is considered to be the end time of the detected signal. The effective period of the burst signal detection flag signal corresponds to the start time to the end time.

[0018] In some embodiments, the FPGA further includes: a power calibration and compensation unit connected to the analog-to-digital converter of the air traffic control equipment, used to perform power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

[0019] In some embodiments, the data processing module is further configured to:

[0020] Perform a Fast Fourier Transform on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal and obtain the frequency search value corresponding to the maximum amplitude.

[0021] In some embodiments, the time-domain and frequency-domain information of the burst signal is transmitted to the display module unit via a serial port for signal feature display and signal compliance determination.

[0022] Secondly, this invention provides a method for detecting burst signals in an air traffic control receiving channel, the method comprising:

[0023] The digital intermediate frequency (IF) signal output by the analog-to-digital converter of the air traffic control equipment is processed by a field-programmable gate array (FPGA) to obtain the time-domain and frequency-domain information of burst signals in the digital IF signal. The FPGA is the FPGA of the air traffic control equipment.

[0024] The display module unit receives and displays the time-domain and frequency-domain information of the burst signal.

[0025] In some embodiments, the FPGA includes: a burst signal detection unit, which includes: a data processing module, a window energy calculation module, a decision module, and a data buffer module, wherein...

[0026] The data processing module processes the digital intermediate frequency signal output by the analog-to-digital converter to obtain the frequency domain information of the digital intermediate frequency signal.

[0027] The window energy calculation module calculates the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter using the double sliding window method.

[0028] The decision module performs burst signal detection based on the window energy value to generate a burst signal detection flag signal, wherein the burst signal detection flag signal is used to indicate valid buffered output data.

[0029] The data caching module, under the guidance of the burst signal detection flag signal and the frequency domain information of the digital intermediate frequency signal, caches and outputs the time domain information and frequency domain information of the burst signal in the digital intermediate frequency signal.

[0030] In some embodiments, the FPGA further includes a power calibration and compensation unit, wherein the power calibration and compensation unit performs power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

[0031] In some embodiments, the data processing module performs a fast Fourier transform on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal and obtain the frequency search value corresponding to the maximum amplitude.

[0032] Compared with existing technologies, this invention has the following advantages and beneficial effects: Based on the Fast Fourier Transform and dual sliding window detection method, through data caching and interface adaptation transmission, the time domain and frequency domain information of burst signals are directly displayed on the monitor, which facilitates designers and testers to quickly locate receiving channel problems and improves the efficiency of receiving channel signal monitoring; furthermore, using the method of this invention, technicians can directly obtain the amplitude and frequency domain information of the intermediate frequency signal, including the original digital signal of the current intermediate frequency, without using a spectrum analyzer and oscilloscope, providing a solution for quickly locating receiving channel problems and improving work efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a burst signal detection device for an air traffic control receiving channel according to an embodiment of the present invention.

[0035] Figure 2 This is a structural block diagram of a burst signal detection unit according to an embodiment of the present invention.

[0036] Figure 3 The process for acquiring and caching time-domain and frequency-domain information according to an embodiment of the present invention is illustrated.

[0037] Figure 4 This is a structural block diagram of a display module unit according to an embodiment of the present invention.

[0038] Figure 5 This is a flowchart of a method for detecting burst signals in an air traffic control receiving channel according to an embodiment of the present invention.

[0039] Figure 6 This is a procedure for detecting burst signals in the air traffic control receiving channel according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] This invention addresses the radio frequency signal receiving link, providing a convenient and clear way to detect whether the time-domain and frequency-domain characteristics of the receiving channel meet design requirements during the R&D, small-batch production, and mass production stages. This can be achieved by using the inherent hardware of the functional device in conjunction with an external low-cost display device, following a fixed software protocol, to display the time-domain and frequency-domain characteristics of the input burst signal. This solution ensures that throughout the product lifecycle, design and testing personnel can easily and quickly troubleshoot or confirm compliance with receiving channel requirements, improving R&D efficiency, fault diagnosis efficiency, and saving on instrument usage and human resource costs.

[0042] The superheterodyne receiving channel consists of a superheterodyne receiver input analog link and an analog-to-digital (AD) sampling channel. After passing through the superheterodyne receiving channel, the acquired intermediate frequency digital signal is sent to the device of this invention for burst signal time-domain and frequency-domain detection. The burst signal time-domain and frequency-domain detection of the superheterodyne receiving channel of this invention is to detect the conformity between the superheterodyne receiver input channel analog link and the input AD sampling channel link.

[0043] On the one hand, the present invention provides a device for detecting burst signals in air traffic control receiving channels. Figure 1 This is a schematic diagram of a burst signal detection device for an air traffic control receiving channel according to an embodiment of the present invention. (Reference) Figure 1 The air traffic control receiver channel burst signal detection device includes: a field programmable gate array (FPGA) and a display module unit.

[0044] A field-programmable gate array (FPGA) is connected to the analog-to-digital converter (ADC) of the air traffic control equipment to process the digital intermediate frequency (IF) signal output by the ADC to obtain the time-domain and frequency-domain information of burst signals in the IF signal.

[0045] The display module unit, connected to the FPGA, is used to receive and display the time-domain and frequency-domain information of burst signals.

[0046] The air traffic control receiving channel burst signal detection device of the present invention can be implemented using an existing logic device (FPGA) residing in the air traffic control function software, plus a display module unit. Considering the abundant resources of large-scale logic devices currently available, the core algorithms are implemented using the existing hardware of the function device. Once implemented, it can be used in all projects as a CBB (General Logic Module), eliminating the need for further R&D costs. For the convenience of the display module unit, it connects to the function device using a general-purpose debugging serial port or network port. When it is necessary to observe the characteristics of the intermediate frequency (IF) signal, the display module unit can be connected to complete the observation of the IF signal, directly displaying the amplitude and frequency domain information of the IF signal (including the original digital signal of the current IF). This provides a solution for quickly locating the receiving channel and improves work efficiency.

[0047] The following detailed description, with reference to the accompanying drawings, describes the various structures of the burst signal detection equipment for the air traffic control receiving channel.

[0048] Figure 2 This is a structural block diagram of a burst signal detection unit according to an embodiment of the present invention. (Refer to...) Figure 2 In some embodiments, the FPGA includes a burst signal detection unit, wherein the burst signal detection unit includes a data processing module, a window energy calculation module, a decision module, and a data buffer module.

[0049] The data processing module is connected to the analog-to-digital converter of the air traffic control equipment. It uses FFT (Fast Fourier Transform) to convert the signal output by the analog-to-digital converter from a time-domain signal to a frequency-domain signal and processes it to obtain the frequency domain information of the digital intermediate frequency signal.

[0050] The window energy calculation module is connected to the analog-to-digital converter of the air traffic control equipment. It is used to calculate the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter, using the double sliding window method.

[0051] The decision module, connected to the window energy calculation module, is used to perform burst signal detection based on the window energy value to generate a burst signal detection flag signal, which is used to indicate valid buffered output data.

[0052] The data caching module, connected to the analog-to-digital converter, the data processing module, and the decision module respectively, is used to cache and output the time-domain and frequency-domain information of the burst signal in the digital intermediate frequency signal under the indication of the frequency domain information of the burst signal detection flag signal and the digital intermediate frequency signal.

[0053] Currently, methods for detecting burst signals are generally divided into two main categories: time-domain detection algorithms and frequency-domain detection algorithms. Time-domain algorithms mainly include detection algorithms based on energy and correlation functions, while frequency-domain detection algorithms mainly include detection algorithms based on amplitude spectrum and spectral correlation functions. Frequency-domain detection algorithms are generally computationally complex, while time-domain detection algorithms are simple, fast, and computationally inexpensive. The burst signal detection method in this invention is implemented at the intermediate frequency (IF) and uses a double sliding window method in the time domain for burst signal detection.

[0054] The basic principle of the double sliding window method is as follows: Windows A and B are of the same length and are relatively stationary. The signal first enters window A and then sequentially enters window B. Let EA represent the energy value of window A and EB represent the energy value of window B. The decision statistic is:

[0055] m[n] = EA[n] / EB[n];

[0056] A threshold value Th is preset for the burst signal. When the decision quantity m[n] is greater than the threshold value Th, a maximum value detection is performed on the decision quantity m[n]. The start time of the detected signal is considered when the maximum value is detected. During the effective period of the burst signal flag, if the decision quantity m[n] is less than the threshold value Th, a minimum value detection is performed on the decision quantity m[n]. The end time of the detected signal is considered when the minimum value is detected. The effective period of the burst signal detection flag corresponds to the start time to the end time.

[0057] The working process of the sudden signal detection unit is as follows: First, the digital intermediate frequency signal output from the analog-to-digital converter of the air traffic control equipment is sent to the window energy calculation module to calculate the energy values ​​of two windows; then, the window energy values ​​are sent to the decision module to generate a sudden signal detection flag signal. The sudden signal detection flag corresponds to the buffered data, and the buffered output data is only valid when the flag is valid.

[0058] In some embodiments, the FPGA further includes a power calibration and compensation unit connected to the analog-to-digital converter of the air traffic control equipment, for performing power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

[0059] For example, in order to obtain the accurate intermediate frequency (IF) power value of the receiving channel and avoid errors caused by differences in AD channel circuitry and link impedance, a calibrated spectrum analyzer needs to be used to calibrate the IF power value when using a specific device for the first time. Assuming the measured input analog link IF power value is denoted as P1, and the IF amplitude value obtained after performing an FFT transformation on the acquired AD signal in the logic device is denoted as U2, the compensation value ΔP is calculated as follows:

[0060] ΔP = P1 - 20 * log10(U2);

[0061] Considering that different air traffic control devices may use different AD links, the calculated compensation value is written into the FPGA. After compensation, the test power values ​​of the burst signal detection devices in the time and frequency domains are the standard values.

[0062] In some embodiments, the data processing module is further configured to: perform a fast Fourier transform on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal, and obtain the frequency search value corresponding to the maximum amplitude.

[0063] For example, data caching begins at the trigger point. See [link to transformation and caching process] for details. Figure 3 In this process, the intermediate frequency signal is used to detect burst signals in the time domain and to perform spectrum analysis in the frequency domain. The information of the burst signal in the frequency and time domains is then cached.

[0064] In some embodiments, the time-domain and frequency-domain information of the burst signal is transmitted to the display module unit via a serial port for signal feature display and signal compliance determination.

[0065] Figure 4 This is a structural block diagram of a display module unit according to an embodiment of the present invention. (Refer to...) Figure 4 In addition to the original functional software residing in a programmable logic device (FPGA), the detection device of the present invention only adds a display module unit. The display module unit may include a processor (ARM or microcontroller), a small memory, and a display. The acquired data may be selectively stored in the memory or not. The acquired signal is directly discarded after analysis. The signal processing algorithm is executed in the programmable logic device. After execution, it is sent to the interface adapter display module for display via serial port or network port and supports the option of whether to store the data.

[0066] After the original data is transmitted and processed, the time domain and frequency domain information data are transmitted to the display module unit via serial port. The following example uses a sampling rate Fs of 100MHz for channel acquisition to illustrate the spectral resolution and transmission rate.

[0067] Assuming the minimum frequency resolution is Fmin, when collecting 8192 points, the minimum frequency resolution is: Fmin = Fs / N = 100MHz / 8192 = 12.2kHz. Each point contains 16 bits of data, meaning each point occupies 2 bytes of memory (1 byte = 8 bits). Therefore, the buffer needs 8192 * 2 = 16384 bytes. Using a debug serial port with a transmission rate of 115200 MHz and parity check, sending one frame of data includes 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit. Therefore, sending 16384 bytes of data requires sending 16384 * 11 bits of data. The data transmission time is: 16384 * 11 bits / 115200 = 1.564444 seconds.

[0068] Since frequency and time domain information needs to be sent, the transmission time is 3.128888s. When the serial port level is configured for RS422 transmission, the rate can be changed to 1M, and the transmission time will only be 360.45ms, which meets the requirements of conventional test applications.

[0069] Once the calculation results are transmitted to the display module, the display module shows the positions of the five frequency points with the highest amplitude values ​​in the current signal, along with their corresponding amplitude values. Designers or testers can then further analyze the results. Simultaneously, the frequency and time domain waveforms are displayed in upper and lower sections to facilitate observation of any anomalies in the digital signal, such as sampling conditions exhibiting metastable characteristics.

[0070] Then, based on the characteristics of the frequency signal received by the product channel, the signal compliance judgment is completed.

[0071] The low-cost air traffic control receiver channel burst signal detection device of the present invention, based on the original programmable logic device with resident functional software, only adds a processor, a small memory and a display. Excluding the original programmable logic device, the total cost is less than two hundred yuan, which greatly reduces the detection cost.

[0072] This invention, through data caching and interface adaptation transmission, directly displays the time and frequency domain information of burst signals on a monitor, facilitating designers and testers to quickly locate receiving channel problems and improving the efficiency of receiving channel signal monitoring. Furthermore, using the method of this invention, technicians can directly obtain the amplitude and frequency domain information of the intermediate frequency (IF) signal, including the raw digital signal of the current IF, providing a solution for quickly locating the receiving channel and improving work efficiency.

[0073] On the other hand, the present invention provides a flowchart of a method for detecting burst signals in an air traffic control receiving channel. Figure 5 This is a flowchart of a method for detecting burst signals in an air traffic control receiving channel according to an embodiment of the present invention. (Reference) Figure 5The method for detecting burst signals in the air traffic control receiving channel includes: S10 and S20.

[0074] In S10, the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment is processed by a field-programmable gate array (FPGA) to obtain the time-domain and frequency-domain information of burst signals in the digital intermediate frequency signal. The FPGA is the FPGA of the air traffic control equipment.

[0075] In S20, the time-domain and frequency-domain information of the burst signal is received and displayed through the display module unit.

[0076] In some embodiments, the FPGA includes a burst signal detection unit, which includes a data processing module, a window energy calculation module, a decision module, and a data buffer module.

[0077] The data processing module processes the digital intermediate frequency signal output by the analog-to-digital converter to obtain the frequency domain information of the digital intermediate frequency signal.

[0078] The window energy calculation module calculates the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter using the double sliding window method.

[0079] The decision module performs burst signal detection based on the window energy value to generate a burst signal detection flag signal, which is used to indicate valid buffered output data.

[0080] The data caching module, under the guidance of the frequency domain information of the burst signal detection flag signal and the digital intermediate frequency signal, caches and outputs the time domain information and frequency domain information of the burst signal in the digital intermediate frequency signal.

[0081] In some embodiments, the FPGA further includes a power calibration and compensation unit, wherein the power calibration and compensation unit performs power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

[0082] In some embodiments, the data processing module performs a fast Fourier transform on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal and obtain the frequency search value corresponding to the maximum amplitude.

[0083] Figure 6This is a procedure for detecting burst signals in the air traffic control receiving channel according to an embodiment of the present invention. The detection process includes steps 1 to 7. Specifically, in step 1, burst signal detection of the superheterodyne receiving channel is performed; in step 2, signal power calibration compensation is acquired; in step 3, time-domain and frequency-domain information after threshold decision is acquired and cached; in step 4, the detection results are transmitted to the display module unit via a serial port; in step 5, signal characteristics are displayed; in step 6, signal compliance determination is performed; and in step 7, main cost accounting is conducted.

[0084] Other implementation details of this method for detecting burst signals in the air traffic control receiver channel can be found in the above description of the equipment for detecting burst signals in the air traffic control receiver channel, and will not be repeated here.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A device for detecting burst signals in an air traffic control receiving channel, characterized in that, The device includes: A field-programmable gate array (FPGA) is connected to the analog-to-digital converter (ADC) of the air traffic control equipment. It is used to process the digital intermediate frequency (IF) signal output by the ADC of the air traffic control equipment to obtain the time-domain and frequency-domain information of burst signals in the digital IF signal. The FPGA is the FPGA of the air traffic control equipment. The display module unit, connected to the FPGA, is used to receive and display the time-domain and frequency-domain information of the burst signal.

2. The device according to claim 1, characterized in that, The FPGA includes: a burst signal detection unit, wherein the burst signal detection unit includes: The data processing module is connected to the analog-to-digital converter of the air traffic control equipment and is used to process the digital intermediate frequency signal output by the analog-to-digital converter to obtain the frequency domain information of the digital intermediate frequency signal. The window energy calculation module is connected to the analog-to-digital converter of the air traffic control equipment and is used to calculate the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter using the double sliding window method. The decision module, connected to the window energy calculation module, is used to perform burst signal detection based on the window energy value to generate a burst signal detection flag signal, wherein the burst signal detection flag signal is used to indicate valid buffered output data; The data caching module is connected to the analog-to-digital converter, the data processing module, and the decision module, respectively, and is used to cache and output the time-domain information and frequency-domain information of the burst signal in the digital intermediate frequency signal under the indication of the burst signal detection flag signal and the frequency-domain information of the digital intermediate frequency signal.

3. The device according to claim 2, characterized in that, The dual sliding window method includes using a first window and a second window, which are relatively stationary. The digital intermediate frequency signal first enters the first window and then the second window. The decision module performs burst signal detection based on the following formula: m[n] = EA[n] / EB[n]; Where EA[n] represents the energy value of the nth first window A; EB[n] represents the energy value of the nth second window B; Wherein, when m[n] is greater than the preset threshold, a maximum value detection is performed on m[n], and the detection of the maximum value is considered to be the start time of the detected signal; when the decision value m[n] is less than the preset threshold, a minimum value detection is performed on m[n], and the detection of the minimum value is considered to be the end time of the detected signal. The effective period of the burst signal detection flag signal corresponds to the start time to the end time.

4. The device according to claim 2 or 3, characterized in that, The FPGA further includes a power calibration and compensation unit, which is connected to the analog-to-digital converter of the air traffic control equipment, and is used to perform power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

5. The device according to claim 2, characterized in that, The data processing module is further used for: A fast Fourier transform is performed on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal and to obtain the frequency search value corresponding to the maximum amplitude.

6. The device according to claim 1, characterized in that, The time-domain and frequency-domain information of the burst signal is transmitted to the display module unit via a serial port for signal feature display and signal compliance determination.

7. A method for detecting burst signals in an air traffic control receiver channel, characterized in that, The method includes: The digital intermediate frequency (IF) signal output by the analog-to-digital converter of the air traffic control equipment is processed by a field-programmable gate array (FPGA) to obtain the time-domain and frequency-domain information of burst signals in the digital IF signal. The FPGA is the FPGA of the air traffic control equipment. The display module unit receives and displays the time-domain and frequency-domain information of the burst signal.

8. The method according to claim 7, characterized in that, The FPGA includes a burst signal detection unit, which further includes a data processing module, a window energy calculation module, a decision module, and a data buffer module. The data processing module processes the digital intermediate frequency signal output by the analog-to-digital converter to obtain the frequency domain information of the digital intermediate frequency signal. The window energy calculation module calculates the window energy value based on the digital intermediate frequency signal output by the analog-to-digital converter using the double sliding window method. The decision module performs burst signal detection based on the window energy value to generate a burst signal detection flag signal, wherein the burst signal detection flag signal is used to indicate valid buffered output data. The data caching module, under the guidance of the burst signal detection flag signal and the frequency domain information of the digital intermediate frequency signal, caches and outputs the time domain information and frequency domain information of the burst signal in the digital intermediate frequency signal.

9. The method according to claim 8, characterized in that, The FPGA further includes a power calibration and compensation unit, wherein the power calibration and compensation unit performs power calibration and compensation on the digital intermediate frequency signal output by the analog-to-digital converter of the air traffic control equipment based on a predetermined compensation value.

10. The method according to claim 8, characterized in that, The data processing module performs a Fast Fourier Transform on the digital intermediate frequency signal to obtain the frequency domain information of the digital intermediate frequency signal and obtain the frequency search value corresponding to the maximum amplitude.

Images