Silicon carbide diode structure, chip structure and preparation method thereof

Abstract

The invention discloses a silicon carbide diode structure, a chip structure and a preparation method thereof. Each of the diode structure and the chip structure comprises a cathode metal and an N + type silicon carbide substrate above the cathode metal, and a first N-type silicon carbide epitaxial layer, a second N-type silicon carbide epitaxial layer and a P + type shielding region are sequentially arranged above the N + type silicon carbide substrate; one end, far away from the N + type silicon carbide substrate, of the second N-type silicon carbide epitaxial layer is provided with a longitudinal step groove, the longitudinal step groove penetrates through the second N-type silicon carbide epitaxial layer and a part of the first N-type silicon carbide epitaxial layer, and the side wall and the bottom of the step groove are coated by anode metal. The chip structure further comprises a plurality of cellular structures which are provided with the layers and are different in structure. According to the invention, under the condition of not increasing the area of an active region chip, the Schottky contact area can be obviously increased, the conduction loss of the device is reduced, and the anti-surge capability of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a silicon carbide diode structure, chip structure, and its fabrication method. Background Technology

[0002] Silicon carbide, as a wide bandgap semiconductor material, has advantages such as high critical breakdown electric field strength, high saturated electron mobility, and high thermal conductivity, giving it a significant material advantage in the field of power electronic devices.

[0003] Compared to conventional silicon and germanium diodes, silicon carbide diodes offer advantages such as high voltage resistance, high temperature resistance, and high electric field strength, leading to their increasingly wide range of applications. However, conventional silicon carbide diodes also have significant drawbacks: due to their wide bandgap, they exhibit a high forward voltage drop (Vf), requiring a higher forward voltage to conduct, resulting in lower switching efficiency and higher energy consumption.

[0004] Figure 1 This is a cross-sectional view of a traditional Schottky diode. (Example:) Figure 1 As shown, traditional Schottky diodes only form a Schottky structure on their surface. Furthermore, to improve the reverse breakdown voltage and leakage current of traditional Schottky diodes, a P+ type shielding region is typically injected. The introduction of the P+ type shielding region reduces the Schottky area, which increases the on-state voltage drop and thus the power consumption of the device. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a silicon carbide diode structure, a chip structure, and a method for fabricating the same. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a silicon carbide diode structure, which, along a first direction, comprises: Cathode metal; An N+ type substrate is located on the upper surface of the cathode metal; The first N-type silicon carbide epitaxial layer is located on the upper surface of the N+ type substrate; The first P+ type shielding structure is formed on the upper surface and inside of the first N-type silicon carbide epitaxial layer, and includes a plurality of shielding regions spaced apart along the second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along the third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction and the second direction are in the same horizontal plane and perpendicular to each other. The second N-type silicon carbide epitaxial layer is located on the upper surface of the first N-type silicon carbide epitaxial layer; Multiple stepped trenches, each stepped trench comprising a first trench and a second trench that are interconnected, each stepped trench being located in a shielded area and extending along the third direction; The first anode metal includes a Schottky metal layer located on the upper surface of the second N-type silicon carbide epitaxial layer and on the sidewalls of each stepped trench; The second anode metal is located on the upper surface of the first anode metal.

[0006] This invention also provides a method for fabricating a silicon carbide diode structure, comprising: S10. Select silicon carbide substrate as N+ type substrate; S11. A first N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the N+ type substrate; S12. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer. An ion implantation window is etched by photolithography and etching using a mask template with a first design pattern. A first P+ type shielding structure is formed by ion implantation, which is located on the upper surface and inside the first N-type silicon carbide epitaxial layer. Then, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along a second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along a third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction is in the same horizontal plane as the second direction and is perpendicular to each other. S13. A second N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer; S14. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer. A first trench extending along the third direction is etched in each shielded area by photolithography and etching processes. Then the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending along the third direction on the first trench. The interconnected first trench and second trench constitute a stepped trench. S15. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer and the sidewalls of each stepped trench to form a first anode metal; S16. Deposit a second anode metal on the upper surface of the Schottky metal layer; S17. Thin the lower surface of the N+ type substrate and fabricate cathode metal on the lower surface of the N+ type substrate.

[0007] The present invention also provides a silicon carbide diode chip structure, comprising: a plurality of spaced first cell structures, each first cell structure being a silicon carbide diode structure as described in any one of claims 1 to 3, and the plurality of spaced first cell structures forming a plurality of rows of first cell structures arranged along the third direction, each row of first cell structures containing at least two first cell structures spaced apart along the second direction.

[0008] This invention also provides a method for fabricating a silicon carbide diode chip structure, comprising: S20. Silicon carbide substrate is selected as N+ type substrate; S21. A first N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the N+ type substrate; S22. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer. An ion implantation window is etched using a mask template with a first design pattern, a second design pattern, and a third design pattern through photolithography and etching processes. A first P+ type shielding structure, a second P+ type shielding structure, and a plurality of third P+ type shielding regions are formed simultaneously on the upper surface and inside the first N-type silicon carbide epitaxial layer through ion implantation. Then, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along a second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along a third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction is in the same horizontal plane as the second direction and is perpendicular to each other. The second P+ type shielding structure includes a plurality of second P+ type shielding regions arranged along the second direction and extending along the third direction. Each third P+ type shielding region extends along the second direction and connects to every two adjacent second P+ type shielding regions in the third direction. S23. A second N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer; S24. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer. A first trench extending along the third direction is etched by photolithography and etching processes. Then, the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending along the third direction on the first trench. The interconnected first trench and second trench constitute a stepped trench. Each shielding region has a stepped trench extending along the third direction, and each second P+ type shielding region has a stepped trench extending along the third direction. Furthermore, after the stepped trench in any one of the two adjacent second P+ type shielding regions in the third direction extends along the third direction to the third P+ type shielding region, it communicates with the stepped trench in the other second P+ type shielding region. S25. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer and the sidewalls of each stepped trench to form a first anode metal; S26. Deposit a second anode metal on the upper surface of the Schottky metal layer; S27. Thin the lower surface of the N+ type substrate and fabricate cathode metal on the lower surface of the N+ type substrate to obtain a silicon carbide diode chip structure containing three different cell structures.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) This invention forms a stepped trench structure, and a Schottky structure is formed on the lower surface and sidewalls of the entire stepped trench, as well as on the surface of the second N-type epitaxial layer without the stepped trench. Introducing the stepped trench significantly increases the Schottky area of ​​the device, reducing the on-state voltage drop while keeping the chip area constant, thereby improving the switching efficiency of the silicon carbide diode. Furthermore, the structure of this invention also introduces a P+ type shielding region to increase the reverse breakdown voltage and reduce the leakage current of the device. However, since the P+ type shielding structure in the silicon carbide diode structure of this invention includes multiple shielding regions spaced apart along a second direction, and each shielding region contains multiple first P+ type shielding regions spaced apart along a third direction, with the first P+ type shielding regions in adjacent shielding regions staggered along the second direction, the P+ type shielding region in the silicon carbide diode structure of this invention is a discontinuous periodic structure. By introducing a discontinuous periodic P+ type shielding region structure, this invention can reduce the loss of Schottky area while meeting the device breakdown voltage, thereby reducing the on-state voltage drop and thus reducing the power consumption of the device.

[0010] 2) Under normal operating conditions, current flows through the Schottky region (the contact area between the Schottky metal and the second N-type silicon carbide epitaxial layer). The Schottky region is electronically conductive. When a surge current occurs in the system, the Schottky region will generate a larger voltage drop, leading to severe heat generation and potentially burning out the device. The silicon carbide diode chip structure proposed in this invention includes different cell structures arranged in a specific manner, further improving the chip's surge current carrying capacity. Furthermore, it can better absorb large surge current impacts when the chip faces them. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of a traditional Schottky diode. Figure 2 These are schematic diagrams of the planar structure and cross-sectional structure in different directions of a silicon carbide diode structure provided in the embodiments of the present invention; Figure 3This is a schematic diagram of the planar structure of the silicon carbide diode chip structure provided in the embodiments of the present invention and the planar structure of the three cell structures included therein; Figure 4 This is a partial planar structural schematic diagram of the silicon carbide diode chip structure provided in an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the structure after forming a first N-type silicon carbide epitaxial layer, provided in an embodiment of the present invention. Figure 6 This is a cross-sectional structural diagram of the second P+ type shielding structure provided in an embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of the structure after forming the second N-type silicon carbide epitaxial layer according to an embodiment of the present invention; Figure 8 This is a schematic cross-sectional view of the structure after the stepped grooves are formed, provided in an embodiment of the present invention. Figure 9 This is a schematic cross-sectional view of the structure after the formation of the first anode metal, provided in an embodiment of the present invention. Figure 10 This is a cross-sectional structural diagram of the second anode metal and cathode metal provided in an embodiment of the present invention. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0013] Figure 2 This is a planar schematic diagram (i.e., a top view) of a silicon carbide diode structure provided by the present invention, as well as cross-sectional views along the AA and AB directions. Figure 2 As shown, along the first direction A1, the silicon carbide diode structure includes: Cathode metal 08; N+ type substrate 01 is located on the upper surface of cathode metal 08; The first N-type silicon carbide epitaxial layer 02 is located on the upper surface of the N+ type substrate 01; A first P+ type shielding structure is formed on the upper surface and inside of a first N- type silicon carbide epitaxial layer 02, and includes a plurality of shielding regions spaced apart along a second direction A2. Each shielding region contains a plurality of first P+ type shielding regions 031 spaced apart along a third direction A3. The first P+ type shielding regions 031 in adjacent shielding regions are staggered along the second direction A2, such as... Figure 2 As shown, the third direction A3 and the second direction A2 are in the same horizontal plane and perpendicular to each other; The second N-type silicon carbide epitaxial layer 04 is located on the upper surface of the first N-type silicon carbide epitaxial layer 02; Multiple stepped trenches 05, each stepped trench 05 includes a first trench and a second trench that are interconnected, each stepped trench is located in a shielded area and extends along a third direction A3; The first anode metal 06 includes a Schottky metal layer located on the upper surface of the second N-type silicon carbide epitaxial layer 04 and on the sidewalls of each stepped trench; The second anode metal 07 is located on the upper surface of the first anode metal 06.

[0014] In this invention, the N+ type substrate 01 has a concentration range of 2e19~4e19 cm⁻¹ -3 The high-concentration N-type drain electrode, and the N+ type substrate 01 is a silicon carbide substrate, which can be a material such as 4H-SiC, 6H-SiC or 3C-SiC; for example, it is a 4H-SiC material.

[0015] In this invention, such as Figure 2 As shown, along the second direction A2, the width of the second groove is greater than the width of the first groove. The angle between the sidewall and the bottom surface of the first groove is in the range of 89.5~90°, that is, the angle between the sidewall and the bottom surface of the first groove is approximately a right angle, and the sidewall of the second groove is curved.

[0016] In this invention, such as Figure 2 As shown, the bottom of the first trench extends into the first P+ type shielding area 031, and along the second direction A2, the width of each first P+ type shielding area 031 is less than or equal to the width of the second trench, but greater than or equal to the width of the first trench.

[0017] In some embodiments, the width of the first P+ type shielding region 031 along the second direction A2 ranges from 1.5 to 2.5 μm.

[0018] In some embodiments, the depth range of the first P+ type shielding region 031 along the first direction A1 is 0.5~1.5μm.

[0019] In some embodiments, along the third direction A3, the spacing between two adjacent first P+ type shielding regions 031 ranges from 1.5 to 2 μm.

[0020] In some embodiments, along the second direction A2, the spacing between two adjacent first P+ type shielding regions 031 ranges from 3.5 to 5.5 μm.

[0021] In some embodiments, the depth of the stepped groove 05 along the first direction A1 ranges from 0.8 to 1.5 μm.

[0022] In some embodiments, along the first direction A1, the depth of the second groove in the stepped groove 05 accounts for 35% to 45% of the total depth of the stepped groove 05. For example, the depth of the second groove accounts for 40% of the total depth of the stepped groove 05.

[0023] In this invention, the first P+ type shielding region 031 is the region obtained by selectively implanting aluminum ions into the upper surface of the first N- type silicon carbide epitaxial layer 02 via ion implantation. For example, the energy range during ion implantation is 200~300keV, and the implantation dose range is 2e15~5e15 cm⁻¹. -3 .

[0024] In this invention, the Schottky metal can be titanium, titanium nitride, nickel, or a combination of these metals, and this invention does not limit the specific metal used.

[0025] In this invention, the second anode metal 07 is aluminum or a copper-aluminum alloy, wherein the copper content in the copper-aluminum alloy is 0.8% and the aluminum content is 99.2%.

[0026] In this invention, the cathode metal 08 is a combination of titanium / nickel / silver, that is, the cathode metal is a multilayer metal, and starting from the lower surface of the N+ type substrate 01, the first layer is a titanium metal layer, the second layer is a nickel metal layer, and the third layer is a silver metal layer.

[0027] This invention forms a stepped trench structure, and a Schottky structure is formed on the lower surface and sidewalls of the entire stepped trench, as well as on the surface of the second N-type epitaxial layer without the stepped trench. Introducing the stepped trench significantly increases the Schottky area of ​​the device, reducing the on-state voltage drop while maintaining the same chip area, thereby improving the switching efficiency of the silicon carbide diode. Furthermore, the structure of this invention also introduces a P+ type shielding region to increase the reverse breakdown voltage and reduce the leakage current of the device. However, because the P+ type shielding structure in the silicon carbide diode structure of this invention includes multiple shielding regions spaced apart along a second direction, and each shielding region contains multiple first P+ type shielding regions spaced apart along a third direction, with the first P+ type shielding regions in adjacent shielding regions staggered along the second direction, the P+ type shielding region in the silicon carbide diode structure of this invention is a discontinuous periodic structure. This invention, by introducing a discontinuous periodic P+ type shielding region structure, can reduce the loss of Schottky area while meeting the device breakdown voltage requirements.

[0028] This invention also provides a method for fabricating a silicon carbide diode structure, comprising: S10. Select silicon carbide substrate as N+ type substrate 01.

[0029] S11. A first N-type silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of the N+ type substrate 01.

[0030] Specifically, a first N-type silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of an N+ type substrate 01 by chemical vapor deposition.

[0031] S12. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer 02. An ion implantation window is etched using a mask template with a first design pattern through photolithography and etching processes. A first P+ type shielding structure is formed by ion implantation, which is located on the upper surface and inside the first N-type silicon carbide epitaxial layer 02. After that, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along the second direction A2. Each shielding region includes a plurality of first P+ type shielding regions 031 spaced apart along the third direction. The first P+ type shielding regions 031 in two adjacent shielding regions are staggered along the second direction A2. The third direction A3 is in the same horizontal plane as the second direction A2 and is perpendicular to each other.

[0032] Specifically, a mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer 02. An ion implantation window is etched using a mask template with a first design pattern through photolithography and etching processes. A first P+ type shielding structure is formed simultaneously on the surface and inside the first N-type silicon carbide epitaxial layer 02 by selectively implanting aluminum ions. The ion implantation energy range is 200~300 keV, and the implantation dose range is 2e15~5e15 cm⁻¹. -3 .

[0033] S13. A second N-type silicon carbide epitaxial layer 04 is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer 02.

[0034] Specifically, a second N-type silicon carbide epitaxial layer 04 is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer 02 by chemical vapor deposition.

[0035] S14. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer 04. A first trench extending in the third direction is etched in each shielded area by photolithography and etching processes. Then the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending in the third direction on the first trench. The first trench and the second trench that are interconnected form a stepped trench 05.

[0036] S15. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer 04 and on the sidewalls of each stepped trench 05 to form the first anode metal 06.

[0037] S16. Deposit a second anode metal 07 on the upper surface of the Schottky metal layer.

[0038] S17. Thin the lower surface of the N+ type substrate and fabricate cathode metal 08 on the lower surface of the N+ type substrate.

[0039] The present invention also provides a silicon carbide diode chip structure, comprising: a plurality of spaced-apart first cell structures A, each first cell structure being the aforementioned silicon carbide diode structure, and these plurality of spaced-apart first cell structures forming multiple rows of first cell structures arranged along a third direction A3, each row of first cell structures containing at least two first cell structures A spaced apart along a second direction A2. For example, Figure 3 This is a planar structural diagram of a silicon carbide diode chip, and planar structural diagrams (i.e., top views) of the three different cell structures contained in this silicon carbide diode chip structure, as shown. Figure 3 As shown, each white area represents a first-cell structure A.

[0040] In some embodiments, such as Figure 3 As shown, the silicon carbide diode chip structure provided by this invention further includes multiple second cell structures C; each second cell structure C is located between two adjacent first cell structures A in each row of first cell structures. (Continue to refer to...) Figure 3 Each second cell structure C includes a second P+ type shielding structure and a plurality of stepped trenches 05. The second P+ type shielding structure is formed on the upper surface and inside of the first N-type silicon carbide epitaxial layer 02, and includes a plurality of second P+ type shielding regions 032 arranged along the second direction A2 and extending along the third direction A3. Each stepped trench 05 is located in a second P+ type shielding region 032 and extends along the third direction A3.

[0041] In this invention, each layer in the first cell structure A and the second cell structure C is prepared in a single step using the same preparation method, and the materials of each layer in the first cell structure A and the second cell structure C are the same. The only difference between the first cell structure A and the second cell structure C is the arrangement of the P+ type shielding region on the second N- type silicon carbide epitaxial layer.

[0042] In some embodiments, continue to refer to Figure 3The silicon carbide diode chip structure further includes: a plurality of third cell structures B, each third cell structure B being located between two adjacent rows of first cell structures, and each third cell structure B including a third P+ type shielding region 033. The third P+ type shielding region 033 is formed on the upper surface and inside of the first N-type silicon carbide epitaxial layer, and each third P+ type shielding region 033 extends along the second direction A2 and connects to every two adjacent second P+ type shielding regions 032 on the third direction A3. Furthermore, a stepped trench 05 in any one of the two second P+ type shielding regions 032 extends along the third direction A3 to the third P+ type shielding region 033 and then connects to a stepped trench 05 in the other second P+ type shielding region 032. For example, Figure 4 This is a partial planar structural diagram of a silicon carbide diode chip, as well as cross-sectional views in the AC and AD directions. Specifically, Figure 4 It includes a partial planar structural diagram of two third-cell structures B and three second-cell structures C separated by the two third-cell structures B, as well as a cross-sectional diagram of one third-cell structure B and one second-cell structure C. Figure 4 As shown, the third P+ type shielding area 033 extends along the second direction A2 and connects with every two adjacent second P+ type shielding areas 032 on the third direction A3. Furthermore, after the stepped groove 05 in any one of the two second P+ type shielding areas 032 extends along the third direction A3 to the third P+ type shielding area 033, it connects with the stepped groove 05 in the other second P+ type shielding area 032. It can be understood that, as... Figure 4 As shown, the stepped groove 05 in every two adjacent second P+ type shielding areas 032 on the third direction A3 and the stepped groove 05 in the third P+ type shielding area 033 belong to the same stepped groove 05.

[0043] In some embodiments, the stepped trench 05 located in each shielding area is also connected along the third direction A3 to the stepped trench 05 located in the third P+ type shielding area 033.

[0044] In some embodiments, the area ratio of the first cell structure A in the active region of the silicon carbide diode chip structure ranges from 70% to 75%, and the area ratio of the sum of the areas of the second cell structure C and the third cell structure B in the active region of the silicon carbide diode chip structure ranges from 25% to 30%.

[0045] In this invention, each layer in the first cell structure A, the second cell structure C, and the third cell structure B is prepared in a single step using the same method, and the materials of each layer in the first cell structure A, the second cell structure C, and the third cell structure B are the same. The only difference between the first cell structure A, the second cell structure C, and the third cell structure B is the arrangement of the P+ type shielding region on the second N- type silicon carbide epitaxial layer.

[0046] The silicon carbide diode chip structure proposed in this invention incorporates different cell structures arranged in a specific manner, further improving the chip's surge current carrying capacity and enabling it to better absorb large surge current impacts. Specifically, under normal operating conditions, current flows through the Schottky region (the contact area between the Schottky metal and the second N-type silicon carbide epitaxial layer). The Schottky region is electronically conductive; when a sudden surge current occurs in the system, the Schottky region generates a larger voltage drop, leading to severe heat generation and potentially burning out the device. This invention addresses this by introducing... Figure 4 The device structure on the upper left side means that when the device is in normal operation, current flows in the Schottky region, and the current does not pass through the P+ type shielding region. When the device encounters a surge current, because the P+ type shielding region and the second N-type silicon carbide epitaxial layer are PN diodes, a conductivity modulation effect occurs under high current, thus this region has a stronger current carrying capacity, and the current flows through the P+ type shielding region. Furthermore... Figure 4 The device structures shown in the lower left corner are all PN diodes. This invention introduces PN diodes into the chip structure. Figure 4 The device structure shown on the lower left can be used to further improve the surge current carrying capacity.

[0047] This invention also provides a method for fabricating a silicon carbide diode chip structure, comprising: S20, Select silicon carbide substrate as N+ type substrate 01.

[0048] N+ type substrate 01 has a concentration range of 2e19~4e19cm⁻¹ -3 The high-concentration N-type drain electrode, and the N+ type substrate 01 is made of silicon carbide substrate, and the silicon carbide substrate can be a material such as 4H-SiC, 6H-SiC or 3C-SiC, for example, 4H-SiC material.

[0049] S21. A first N-type silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of the N+ type substrate 01.

[0050] Specifically, a first N-type silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of an N+ type substrate 01 by chemical vapor deposition, for example, Figure 5This is a schematic diagram of the cross-sectional structure after the formation of the first N-type silicon carbide epitaxial O2.

[0051] S22. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer 02. An ion implantation window is etched using a mask template with a first design pattern, a second design pattern, and a third design pattern through photolithography and etching processes. A first P+ type shielding structure, a second P+ type shielding structure, and a plurality of third P+ type shielding regions are formed simultaneously on the upper surface and inside the first N-type silicon carbide epitaxial layer 02 through ion implantation. Afterward, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along a second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along a third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction and the second direction are in the same horizontal plane and perpendicular to each other. The second P+ type shielding structure includes a plurality of second P+ type shielding regions arranged along the second direction and extending along the third direction. Each third P+ type shielding region extends along the second direction and connects to every two adjacent second P+ type shielding regions in the third direction.

[0052] Specifically, a mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer 02. An ion implantation window is etched using a mask template with a first design pattern through photolithography and etching processes. Then, aluminum ions are selectively implanted to form a first P+ type shielding structure, a second P+ type shielding structure, and multiple third P+ type shielding regions simultaneously located on the upper surface and inside the first N-type silicon carbide epitaxial layer 02. The ion implantation energy range is 200–300 keV, and the implantation dose ranges from 2e¹⁵ to 5e¹⁵ cm⁻¹. -3 For example, Figure 6 This is a cross-sectional structural diagram after the formation of the second P+ type shielding structure, which includes multiple second P+ type shielding areas 032.

[0053] S23. A second N-type silicon carbide epitaxial layer 04 is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer 02.

[0054] Specifically, a second N-type silicon carbide epitaxial layer 04 is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer 02 by chemical vapor deposition. For example, Figure 7 This is a schematic cross-sectional view of the structure after the formation of the second N-type silicon carbide epitaxial layer 04.

[0055] S24. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer. A first trench extending in the third direction is etched by photolithography and etching processes. Then, the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending in the third direction on the first trench. The interconnected first and second trenches constitute a stepped trench 05. Each shielding region has a stepped trench 05 extending in the third direction, and each second P+ type shielding region 032 has a stepped trench 05 extending in the third direction. Furthermore, after the stepped trench 05 in any one of two adjacent second P+ type shielding regions 032 extends in the third direction to the third P+ type shielding region, it communicates with the stepped trench 05 in the other second P+ type shielding region 032. For example, Figure 8 This is a cross-sectional structural diagram after the formation of the stepped trench 05.

[0056] S25. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer 04 and on the sidewalls of each stepped trench 05 to form the first anode metal 06. For example, Figure 9 This is a schematic diagram of a cross-sectional structure after the formation of the first anode metal 06.

[0057] S26. Deposit a second anode metal 07 on the upper surface of the Schottky metal layer.

[0058] S27. Thin the lower surface of the N+ type substrate 01, and fabricate cathode metal 08 on the lower surface of the N+ type substrate 01 to obtain a silicon carbide diode chip structure containing three different cell structures. For example, Figure 10 This is a schematic cross-sectional view of the structure after the formation of the second anode metal 07 and cathode metal 08. It should be noted that... Figures 5-10 This merely illustrates the formation process of the second cell structure during the fabrication of a silicon carbide diode chip structure.

[0059] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0061] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0062] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A silicon carbide diode structure, characterized in that, Along the first direction, the silicon carbide diode structure includes: Cathode metal; An N+ type substrate is located on the upper surface of the cathode metal; The first N-type silicon carbide epitaxial layer is located on the upper surface of the N+ type substrate; The first P+ type shielding structure is formed on the upper surface and inside of the first N-type silicon carbide epitaxial layer, and includes a plurality of shielding regions spaced apart along the second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along the third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction and the second direction are in the same horizontal plane and perpendicular to each other. The second N-type silicon carbide epitaxial layer is located on the upper surface of the first N-type silicon carbide epitaxial layer; Multiple stepped trenches, each stepped trench comprising a first trench and a second trench that are interconnected, each stepped trench being located in a shielded area and extending along the third direction; The first anode metal includes a Schottky metal layer located on the upper surface of the second N-type silicon carbide epitaxial layer and on the sidewalls of each stepped trench; The second anode metal is located on the upper surface of the first anode metal.

2. The silicon carbide diode structure according to claim 1, characterized in that, Along the second direction, the width of the second groove is greater than the width of the first groove; the angle between the sidewall of the first groove and the bottom surface is in the range of 89.5~90°, and the sidewall of the second groove is curved.

3. The silicon carbide diode structure according to claim 1, characterized in that, The bottom of the first trench extends into the first P+ type shielding area, and along the second direction, the width of each first P+ type shielding area is less than or equal to the width of the second trench, but greater than or equal to the width of the first trench.

4. A method for fabricating a silicon carbide diode structure, characterized in that, include: S10. Select silicon carbide substrate as N+ type substrate; S11. A first N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the N+ type substrate; S12. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer. An ion implantation window is etched by photolithography and etching using a mask template with a first design pattern. A first P+ type shielding structure is formed by ion implantation, which is located on the upper surface and inside the first N-type silicon carbide epitaxial layer. Then, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along a second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along a third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction is in the same horizontal plane as the second direction and is perpendicular to each other. S13. A second N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer; S14. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer. A first trench extending along the third direction is etched in each shielded area by photolithography and etching processes. Then the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending along the third direction on the first trench. The interconnected first trench and second trench constitute a stepped trench. S15. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer and the sidewalls of each stepped trench to form a first anode metal; S16. Deposit a second anode metal on the upper surface of the Schottky metal layer; S17. Thin the lower surface of the N+ type substrate and fabricate cathode metal on the lower surface of the N+ type substrate.

5. A silicon carbide diode chip structure, characterized in that, include: Multiple spaced-apart first cell structures, each first cell structure being a silicon carbide diode structure as described in any one of claims 1 to 3, and the multiple spaced-apart first cell structures forming multiple rows of first cell structures arranged along the third direction, each row of first cell structures containing at least two first cell structures spaced apart along the second direction.

6. The silicon carbide diode chip structure according to claim 5, characterized in that, The silicon carbide diode chip structure further includes: multiple second cell structures; each second cell structure is located between two adjacent first cell structures in each row of first cell structures; Each second-cell structure includes: The second P+ type shielding structure is formed on the upper surface and inside of the first N-type silicon carbide epitaxial layer, and includes a plurality of second P+ type shielding regions arranged along the second direction and extending along the third direction. The plurality of stepped trenches, each stepped trench being located in a second P+ type shielding area and extending along the third direction.

7. The silicon carbide diode chip structure according to claim 6, characterized in that, The silicon carbide diode chip structure further includes: multiple third cell structures, each third cell structure being located between two adjacent rows of first cell structures; Each third cell structure includes: A third P+ type shielding region is formed on the upper surface and inside the first N-type silicon carbide epitaxial layer, and each third P+ type shielding region extends along the second direction and connects with every two adjacent second P+ type shielding regions in the third direction. Furthermore, the stepped trench in any one of the two second P+ type shielding regions extends along the third direction to the third P+ type shielding region and then connects with the stepped trench in the other second P+ type shielding region.

8. The silicon carbide diode chip structure according to claim 7, characterized in that, The stepped trench located within each shielding area is connected along the third direction to the stepped trench located within the third P+ type shielding area.

9. The silicon carbide diode chip structure according to claim 7, characterized in that, The area of ​​the first cell structure in the active region of the chip structure is 70% to 75%, and the area of ​​the second cell structure and the third cell structure in the active region of the chip structure is 25% to 30%.

10. A method for fabricating a silicon carbide diode chip structure, characterized in that, include: S20. Silicon carbide substrate is selected as N+ type substrate; S21. A first N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the N+ type substrate; S22. A mask layer is deposited on the upper surface of the first N-type silicon carbide epitaxial layer. An ion implantation window is etched using a mask template with a first design pattern, a second design pattern, and a third design pattern through photolithography and etching processes. A first P+ type shielding structure, a second P+ type shielding structure, and a plurality of third P+ type shielding regions are formed simultaneously on the upper surface and inside the first N-type silicon carbide epitaxial layer through ion implantation. Then, the mask layer is removed. The first P+ type shielding structure includes a plurality of shielding regions spaced apart along a second direction. Each shielding region includes a plurality of first P+ type shielding regions spaced apart along a third direction. The first P+ type shielding regions in two adjacent shielding regions are staggered along the second direction. The third direction is in the same horizontal plane as the second direction and is perpendicular to each other. The second P+ type shielding structure includes a plurality of second P+ type shielding regions arranged along the second direction and extending along the third direction. Each third P+ type shielding region extends along the second direction and connects to every two adjacent second P+ type shielding regions in the third direction. S23. A second N-type silicon carbide epitaxial layer is epitaxially grown on the upper surface of the first N-type silicon carbide epitaxial layer; S24. A mask layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer. A first trench extending along the third direction is etched by photolithography and etching processes. Then, the mask layer is removed. Then, the photolithography and etching processes are repeated to form a second trench extending along the third direction on the first trench. The interconnected first trench and second trench constitute a stepped trench. Each shielding region has a stepped trench extending along the third direction, and each second P+ type shielding region has a stepped trench extending along the third direction. Furthermore, after the stepped trench in any one of the two adjacent second P+ type shielding regions in the third direction extends along the third direction to the third P+ type shielding region, it communicates with the stepped trench in the other second P+ type shielding region. S25. A Schottky metal layer is deposited on the upper surface of the second N-type silicon carbide epitaxial layer and the sidewalls of each stepped trench to form a first anode metal; S26. Deposit a second anode metal on the upper surface of the Schottky metal layer; S27. Thin the lower surface of the N+ type substrate and fabricate cathode metal on the lower surface of the N+ type substrate to obtain a silicon carbide diode chip structure containing three different cell structures.

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