Forming method of PMOS (P-channel Metal Oxide Semiconductor) transistor
By introducing a uniformly thick first silicon-germanium epitaxial layer transition layer into the PMOS transistor, the leakage current problem at the interface between the seed layer and the semiconductor substrate is solved, thereby improving the electrical performance of the PMOS transistor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-07
AI Technical Summary
In the prior art, the high germanium content and doping ion concentration gradient at the interface between the seed layer and the semiconductor substrate lead to significant leakage current problems, affecting the electrical performance of PMOS transistors.
A uniformly thick transition layer is introduced between the semiconductor substrate and the seed crystal layer. The transition layer is a first silicon-germanium epitaxial layer with a germanium atom percentage content of 10%~20%. The carrier concentration gradient is reduced by controlling the crystal orientation growth rate ratio to 1.0~1.3.
This effectively reduces the carrier concentration gradient between the semiconductor substrate and the seed layer, decreases the risk of leakage current, and improves the electrical stability and performance of the PMOS transistor.
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Figure CN121815696A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a PMOS transistor. Background Technology
[0002] In current semiconductor device fabrication processes, stress can alter the bandgap and carrier mobility of silicon materials, making stress-based enhancement of MOS transistor performance an increasingly common method. Typically, embedded germanium-silicon (EGS) technology is employed, which involves forming Sigma-shaped grooves in the source / drain regions of the transistor, filling these grooves with silicon-germanium material, and applying compressive or tensile stress to the channel through the tips of the Sigma-shaped grooves.
[0003] Currently, the silicon-germanium material used to fill the grooves mainly consists of a three-layer structure: a seed layer, a host layer, and a cap layer. Because the seed layer, which is in direct contact with the semiconductor substrate, has a high germanium and boron content, a large carrier concentration gradient exists at the interface between the semiconductor substrate and the seed layer. This carrier concentration gradient generates significant leakage current at the interface. Summary of the Invention
[0004] The purpose of this invention is to provide a method for forming a PMOS transistor by forming a transition layer with uniform thickness and low doping level between a semiconductor substrate and a seed layer. The transition layer reduces the carrier concentration gradient between the semiconductor substrate and the seed layer, thereby effectively reducing the risk of leakage current.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for forming a PMOS transistor, comprising: A semiconductor substrate is provided, wherein a gate structure is formed on the surface of the semiconductor substrate, and grooves for depositing source / drain regions are formed on both sides of the gate structure in the semiconductor substrate. Silicon and germanium are deposited in the groove, and a transition layer, a seed layer, a main layer, and a cap layer are deposited sequentially from the surface of the groove to the direction away from the surface of the groove. The transition layer is a first silicon-germanium epitaxial layer with a thickness of 50-300 Å and a crystal orientation. <100> Deposited on the bottom wall of the groove, with crystal orientation <110> The gas flow ratio of germanium source gas to silicon source gas deposited on the sidewall of the groove to form the first silicon-germanium epitaxial layer is 3:2 to 2:1, with crystal orientation. <100> and crystal orientation <110> The growth rate ratio is 1.0~1.3.
[0006] Optionally, the process for forming the transition layer is as follows: process temperature 500℃~800℃, process pressure 10 torr~30 torr, silicon source gas flow rate range of 50~300 sccm, germanium source gas flow rate range of 50~600 sccm, and germanium atomic percentage content in the first silicon-germanium epitaxial layer is 10%~20%.
[0007] Optionally, the process gas in the transition layer may further include a selective gas, the flow rate of which is in the range of 50~100 sccm.
[0008] Optionally, the seed layer is a second silicon-germanium epitaxial layer, and the formation process of the seed layer is as follows: process temperature 500℃~800℃, process pressure 10 torr~30 torr, the gas flow rate of silicon source gas and germanium source gas in the process gas of the seed layer is 1~1000 sccm, and the atomic percentage content of germanium in the second silicon-germanium epitaxial layer is 25%~35%.
[0009] Optionally, the process gas of the seed crystal layer further includes a selective gas and a doping gas, wherein the flow rate of the selective gas is in the range of 50~200 sccm, the flow rate of the doping gas is in the range of 10~100 sccm, and the doping amount of the doping gas is greater than 1E+19 per cubic centimeter.
[0010] Optionally, the main layer is a third silicon-germanium epitaxial layer, and the formation process of the main layer is as follows: process temperature 600℃~700℃, process pressure 10 torr~30 torr, the gas flow rate of silicon source gas and germanium source gas in the process gas of the main layer is 1~1000 sccm, and the atomic percentage content of germanium in the third silicon-germanium epitaxial layer is greater than or equal to 40%.
[0011] Optionally, the process gas of the main layer further includes a selective gas and a doping gas, wherein the flow rate of the selective gas is in the range of 50~200 sccm, the flow rate of the doping gas is in the range of 10~1000 sccm, and the doping amount of the doping gas is greater than 1E+20 per cubic centimeter.
[0012] Optionally, the germanium content in the third silicon-germanium epitaxial layer gradually increases along the direction from the seed layer to the cap layer.
[0013] Optionally, the cap layer is a fourth silicon-germanium epitaxial layer, and the formation process of the cap layer is as follows: process temperature 700℃~750℃, process pressure 10 torr~30 torr, and the gas flow rates of silicon source gas and germanium source gas in the process gas of the cap layer are both 1~1000 sccm.
[0014] Optionally, the silicon source gas is at least one of silane, trichlorosilane, dichlorosilane, and silicon tetrachloride; the germanium source gas is at least one of germanane and digermanane.
[0015] Optionally, the selective gas is at least one of chlorine and hydrogen chloride.
[0016] Optionally, the doping gas is a boron source gas, which is at least one of diborane, butorane, and boron trichloride.
[0017] Optionally, the process gas used to form the transition layer, seed layer, host layer, and cap layer may also include a carrier gas, wherein the carrier gas is at least one of hydrogen and helium, and the flow rate of the carrier gas is 25,000 to 35,000 sccm.
[0018] Compared with the prior art, the present invention has the following advantages: The technical solution of the present invention forms a transition layer with a thickness of 50~300 Å between the semiconductor substrate and the seed crystal layer. The transition layer contains 10%~20% germanium atomic percentage and has no other doped ions. The presence of the transition layer reduces the carrier concentration gradient between the semiconductor substrate and the seed crystal layer, thereby effectively reducing the risk of leakage current.
[0019] Furthermore, this invention achieves crystal plane orientation by controlling the ratio of silicon source gas and germanium source gas in the process gas. <100> / Crystal orientation <110> The crystal growth rate decreased from 2.0 to about 1.2, achieving uniform growth of the transition layer and thus effectively improving the uniform coverage of the transition layer. Attached Figure Description
[0020] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings described below are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figures 1 to 5 A flowchart of the PMOS manufacturing method provided by the present invention; Figure 6 This is a schematic diagram showing the relationship between the growth thickness of silicon-germanium materials with different crystal orientations and gas flow rate. Detailed Implementation
[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the solution proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.
[0022] like Figures 1 to 5 The diagram shown is a flowchart of the PMOS transistor manufacturing method provided by the present invention.
[0023] like Figure 1 As shown, the process includes: Step 1: Providing a semiconductor substrate 100, on which a gate structure 101 is formed, and on both sides of the gate structure, grooves 102 for depositing source / drain regions are formed in the semiconductor substrate.
[0024] The substrate semiconductor 100 may be silicon, silicon germanium, silicon-on-insulator, etc., and is not limited thereto. The substrate 100 includes an isolation structure (not shown), which may be a silicon oxide shallow trench isolation structure, and the isolation structure is used to isolate devices formed on the surface of the semiconductor substrate 100. The gate structure also includes a sidewall structure.
[0025] The groove can be formed by forming a hard mask layer on the surface of the semiconductor substrate, the hard mask layer having an opening corresponding to the position and width of the groove to be formed subsequently, etching the semiconductor substrate along the opening to form a groove 102, the shape of the formed groove can be U-shaped, square, or Sigma-shaped, the shape of the groove is not limited thereto, and the method of forming the groove is not limited thereto either.
[0026] Continue to refer to Figure 1 Step 2: Transfer the semiconductor substrate to the graphite base in the epitaxial device, and then pass hydrogen gas through it for high-temperature baking to remove moisture and residual carbon oxides from the wafer surface. The baking temperature can be 800℃~1200℃, preferably 850℃~1050℃.
[0027] like Figure 2 As shown, step 3 is performed: a transition layer 103 is formed on the bottom wall and side wall of the groove 102.
[0028] The process conditions for the transition layer are as follows: process temperature 500℃~800℃, more preferably 600℃~700℃; process pressure 10 torr~30 torr; process gas includes silicon source gas, germanium source gas and carrier gas, more preferably, the silicon source gas is at least one of silane (SiH4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2, also known as DCS) and silicon tetrachloride (SiCl4), preferably silane and / or dichlorosilane; the germanium source gas is at least one of germanane (GeH4) and digermanane (Ge2H6), preferably germanane; the carrier gas is at least one of hydrogen (H2) and helium (He), preferably hydrogen. The flow rate of the silicon source gas is 50-300 sccm, preferably 50-150 sccm; the flow rate of the germanium source gas is 50-600 sccm, preferably 100-200 sccm; the ratio of the flow rates of the germanium source and the silicon source is 3:2 to 2:1. The flow rate of the carrier gas is 25000-35000 sccm.
[0029] The transition layer formed in step 3 is the first silicon-germanium epitaxial layer, with a thickness of 50-300 Å, preferably 100-200 Å. The crystal planes of the first silicon-germanium epitaxial layer are then oriented. <100> Deposited on the bottom wall of the groove, with crystal orientation <110> Deposited on the sidewalls of the groove, controlling the crystal orientation. <100> and crystal orientation <110> The growth rate ratio is 1.0 to 1.3. Furthermore, the atomic percentage content of germanium in the first silicon-germanium epitaxial layer is 10% to 20%.
[0030] Furthermore, the process gas in step 3 also includes a selective gas, which is at least one of chlorine (Cl2) and hydrogen chloride (HCl), and the flow rate of the selective gas is in the range of 50~100 sccm. When dichlorosilane is used as the silicon source gas, the flow rate of the selective gas can be appropriately reduced; when silane is used as the selective gas, the flow rate can be appropriately increased. Introducing a selective gas into the process gas can increase selectivity.
[0031] With the miniaturization of semiconductor devices and the increasing demands on transistor performance, if the germanium content and dopant ion content in the seed layer are relatively high, a large carrier concentration gradient will be created at the interface between the semiconductor substrate and the seed layer. This carrier concentration gradient will generate significant leakage current at the interface, which is one of the important factors affecting electrical properties in MOSFET technology.
[0032] By introducing a transition layer, which is a first silicon-germanium epitaxial layer, the atomic percentage content of germanium in the first silicon-germanium epitaxial layer is 10%~20%. Furthermore, the transition layer is not doped to avoid severe lattice mismatch between the semiconductor substrate and the silicon-germanium material, taking the silicon substrate as an example. The presence of the transition layer allows the lattice constant to gradually transition, thereby reducing the concentration gradient of charge carriers and reducing the risk of leakage current.
[0033] Furthermore, the thickness of the transition layer is 50~300 Å, referring to the thickness of the first silicon-germanium epitaxial layer deposited on the bottom wall of the trench. The crystal orientation of the first silicon-germanium epitaxial layer is also specified. <100> Deposited on the bottom wall of the groove, with crystal orientation <110> Deposited on the sidewalls of the groove. In existing processes, the transition layer tends to grow thicker on the bottom wall of the groove, i.e., crystal orientation. <100> The growth rate is fast, but the sidewalls of the grooves grow very thin, meaning they are oriented at the crystal plane. <110> The growth rate is relatively slow, and the crystal orientation is... <111> Almost no growth occurs. Such a transition layer causes uneven deposition of the first silicon-germanium epitaxial layer within the trench, thus negating the transition layer's function of reducing leakage current.
[0034] Reference Figure 6 The crystal orientation can be adjusted by changing the gas flow ratio of germanium source gas to silicon source gas to form the first silicon-germanium epitaxial layer to 3:2 to 2:1. <100> and crystal orientation <110> The growth rate ratio is 1.0~1.3, which effectively improves the uniform coverage of the transition layer.
[0035] like Figure 3 As shown, step 4 is performed: a seed layer 104 is formed on the surface of the transition layer (i.e., the bottom and sidewalls of the transition layer). The process conditions for the seed layer are: a process temperature of 500℃~800℃, preferably 600℃~700℃; a process pressure of 10 torr~30 torr; and process gases including silicon source gas, germanium source gas, selective gas, doping gas, and carrier gas. Further, the silicon source gas is at least one of silane, trichlorosilane, dichlorosilane, and silicon tetrachloride, preferably silane and / or dichlorosilane, and the gas flow rate of the silicon source gas is 1~1000 sccm. The germanium source gas is germanane, digerane, or ethylgermanane. The following gas is preferred: germane; the flow rate of the germanium source gas is 1-1000 sccm; the selective gas is at least one of chlorine and hydrogen chloride; the flow rate of the selective gas is 50-100 sccm; the doping gas is a boron source gas, specifically at least one of diborane, butorane, and boron trichloride; the flow rate of the doping gas is 10-100 sccm; and the carrier gas is at least one of hydrogen and helium, preferably hydrogen, with a flow rate of 25000-35000 sccm.
[0036] The seed layer formed in step 4 is the second silicon-germanium epitaxial layer. The atomic percentage content of germanium in the second silicon-germanium epitaxial layer is 25%~35%, the boron doping amount in the second silicon-germanium epitaxial layer is greater than 1E+19 per cubic centimeter, and the thickness of the seed layer is 10-200 Å.
[0037] Since high-temperature processing is performed after the source and drain regions are formed to activate the dopant ions, seed layers are typically formed on the bottom and sidewalls of the trench to prevent the dopant ions from diffusing into the semiconductor substrate and causing a shift in the resistivity of the source and drain regions. This invention, in addition to the seed layer, also includes a transition layer between the seed layer and the semiconductor substrate, which can more effectively prevent the diffusion of dopant ions into the semiconductor substrate.
[0038] Furthermore, the presence of the seed layer can play a role in the gradual transition of the lattice constant. If a silicon-germanium host layer with a high germanium content (>40%) is directly deposited on the surface of the groove, lattice mismatch will occur because the lattice constant of germanium is greater than that of silicon. This will result in a large number of line defects (dislocations) and surface defects near the interface, which will seriously affect the threshold voltage stability and increase leakage current.
[0039] like Figure 4 As shown, step 5 is performed to form a main layer on the surface of the seed crystal layer.
[0040] The process conditions for the main body layer are: process temperature 600℃~700℃, process pressure 10 torr~30 torr, and process gases including silicon source gas, germanium source gas, selective gas, doping gas, and carrier gas. Further, the silicon source gas is at least one of silane, trichlorosilane, dichlorosilane, and silicon tetrachloride, preferably silane and / or dichlorosilane, and the gas flow rate of the silicon source gas is 1~1000 sccm; the germanium source gas is at least one of germanane and digerane, preferably germanane, and the germanium... The source gas has a flow rate of 1-1000 sccm; the selective gas is at least one of chlorine and hydrogen chloride, and the flow rate of the selective gas is 50-200 sccm; the doping gas is a boron source gas, and the boron source gas is at least one of diborane, butorane, and boron trichloride, and the flow rate of the doping gas is 10-1000 sccm; the carrier gas is at least one of hydrogen and helium, preferably hydrogen, and the flow rate of the carrier gas is 25000-35000 sccm.
[0041] The main layer formed in step 5 is the third silicon-germanium epitaxial layer, which serves as the main contributing layer to the compressive stress of the MOSFET. The atomic percentage content of germanium in the third silicon-germanium epitaxial layer is greater than or equal to 40%, and the boron doping amount in the second silicon-germanium epitaxial layer is greater than 1E+20 per cubic centimeter.
[0042] Furthermore, the germanium content in the third silicon-germanium epitaxial layer gradually increases along the direction from the seed layer to the cap layer.
[0043] like Figure 5 As shown, step 6 is performed to form a cap layer on the surface of the main body layer.
[0044] The process conditions for the cap layer are as follows: process temperature 700℃~750℃, process pressure 10 torr~30 torr, and process gases including silicon source gas, selective gas, and carrier gas. Further, the silicon source gas is at least one of silane, trichlorosilane, dichlorosilane, and silicon tetrachloride, preferably silane and / or dichlorosilane, with a flow rate of 1~1000 sccm; the selective gas is at least one of chlorine and hydrogen chloride, with a flow rate of 1~100 sccm; and the carrier gas is at least one of hydrogen and helium, preferably hydrogen, with a flow rate of 25000~35000 sccm.
[0045] The cap layer is heated at a higher temperature to improve the growth rate.
[0046] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, the term "connection" in this document indicates a direct connection between A and B, or an indirect connection between A and B, such as an indirect connection between A and B via C, or even via C and D, or more components. The connection between A and B can be integral or separate, detachable or fixed. The term "optional" in this document indicates that the technical feature can be combined with or not combined with any feature in the document.
[0047] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for forming a PMOS transistor, characterized in that, include: A semiconductor substrate is provided, wherein a gate structure is formed on the surface of the semiconductor substrate, and grooves for depositing source / drain regions are formed on both sides of the gate structure in the semiconductor substrate. Silicon and germanium are deposited in the groove, and a transition layer, a seed layer, a main layer, and a cap layer are deposited sequentially from the surface of the groove to the direction away from the surface of the groove. The transition layer is a first silicon-germanium epitaxial layer with a thickness of 50-300 Å and a crystal orientation. <100> Deposited on the bottom wall of the groove, with crystal orientation <110> The gas flow ratio of germanium source gas to silicon source gas deposited on the sidewall of the groove to form the first silicon-germanium epitaxial layer is 3:2 to 2:1, with crystal orientation. <100> and crystal orientation <110> The growth rate ratio is 1.0~1.
3.
2. The method for forming a PMOS transistor according to claim 1, characterized in that, The process for forming the transition layer is as follows: process temperature 500℃~800℃, process pressure 10 torr~30 torr, the flow rate of silicon source gas in the process gas of the transition layer is 50~300 sccm, the flow rate of germanium source gas is 50~600 sccm, and the atomic percentage content of germanium in the first silicon-germanium epitaxial layer is 10%~20%.
3. The method for forming a PMOS transistor according to claim 2, characterized in that, The process gas in the transition layer also includes a selective gas, the flow rate of which is 50~100 sccm.
4. The method for forming a PMOS transistor according to claim 1, characterized in that, The seed crystal layer is a second silicon-germanium epitaxial layer. The formation process of the seed crystal layer is as follows: process temperature 500℃~800℃, process pressure 10 torr~30 torr, the gas flow rate of silicon source gas and germanium source gas in the process gas of the seed crystal layer is 1~1000 sccm, and the atomic percentage content of germanium in the second silicon-germanium epitaxial layer is 25%~35%.
5. The method for forming a PMOS transistor according to claim 4, characterized in that, The process gas of the seed crystal layer also includes a selective gas and a doping gas. The flow rate of the selective gas is in the range of 50~200 sccm, the flow rate of the doping gas is in the range of 10~100 sccm, and the doping amount of the doping gas is greater than 1E+19 per cubic centimeter.
6. The method for forming a PMOS transistor according to claim 1, characterized in that, The main layer is a third silicon-germanium epitaxial layer. The formation process of the main layer is as follows: process temperature 600℃~700℃, process pressure 10 torr~30 torr, the gas flow rate of silicon source gas and germanium source gas in the process gas of the main layer is 1~1000 sccm, and the atomic percentage content of germanium in the third silicon-germanium epitaxial layer is greater than or equal to 40%.
7. The method for forming a PMOS transistor according to claim 6, characterized in that, The process gas of the main layer also includes a selective gas and a doping gas. The flow rate of the selective gas is in the range of 50~200 sccm, the flow rate of the doping gas is in the range of 10~1000 sccm, and the doping amount of the doping gas is greater than 1E+20 per cubic centimeter.
8. A method for forming a PMOS transistor according to claim 6, characterized in that, The germanium content in the third silicon-germanium epitaxial layer gradually increases from the seed layer to the cap layer.
9. A method for forming a PMOS transistor according to claim 1, characterized in that, The cap layer is a fourth silicon-germanium epitaxial layer. The formation process of the cap layer is as follows: process temperature 700℃~750℃, process pressure 10 torr~30 torr, and the gas flow rate of silicon source gas in the process gas of the cap layer is 1~1000 sccm.
10. A method for forming a PMOS transistor according to claim 1, characterized in that, The silicon source gas is at least one of silane, trichlorosilane, dichlorosilane, and silicon tetrachloride; the germanium source gas is at least one of germanane and digerane.
11. A method for forming a PMOS transistor according to claim 5 or 7, characterized in that, The selective gas is at least one of chlorine and hydrogen chloride.
12. A method for forming a PMOS transistor according to claim 5 or 7, characterized in that, The doping gas is a boron source gas, and the boron source gas is at least one of diborane, butorane, and boron trichloride.
13. The method for forming a PMOS transistor according to claim 1, characterized in that, The process gas used to form the transition layer, seed layer, host layer, and cap layer also includes a carrier gas, which is at least one of hydrogen and helium, and the flow rate of the carrier gas is 25,000 to 35,000 sccm.