Integrated circuit and method of manufacturing the same

Abstract

The invention provides an integrated circuit and a method of manufacturing the same. A fin region including one or more fin field effect transistors (finFETs) is formed in device regions of a semiconductor substrate and a high voltage (HV) planar region is formed adjacent to the fin region, the finFETs of each device region including one or more fins formed to have a fin top at a first height from a fin substrate region. The HV planar region comprises a first HV planar region and a second HV planar region, the first HV planar region is at a second height greater than the first height from the fin-shaped substrate region, and the second HV planar region is provided with an HV isolation structure for isolating the first HV planar region from the fin region; the HV isolation structure includes a boundary buffer having an intermediate step at a third height from the fin-shaped substrate region, the third height being equal to or greater than the first height and less than the second height. According to the invention, the device yield can be improved.

Description

Technical Field

[0001] This invention relates to an integrated circuit and a method for manufacturing the same. Background Technology

[0002] The following content pertains to semiconductor integrated circuits (ICs) using fin field-effect transistors (finFETs) or other three-dimensional (3D) semiconductor structures that include fins and planar boundaries, as well as their fabrication methods. Summary of the Invention

[0003] Embodiments of the present invention relate to a method of manufacturing an integrated circuit, comprising: forming a fin region comprising one or more fin field-effect transistors (finFETs) in a device region of a semiconductor substrate, each fin FET in the device region comprising one or more fins and a gate, the fins being formed having fin-shaped tops at a first height from a fin FET substrate region, the fin FET substrate region being adjacent to the fin-shaped tops, and the gates being formed to cover one or more fin-shaped tops; and forming a high-voltage (HV) plane region adjacent to the fin region in the device region of the semiconductor substrate, the HV plane region... The device includes a first HV plane region and a second HV plane region. The first HV plane region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region. The second height is greater than the first height. The second HV plane region has an HV isolation structure that isolates the first HV plane region from the fin region. The HV isolation structure includes a boundary buffer. The boundary buffer has an intermediate step at a third height from the fin field-effect transistor substrate region. The third height is equal to or greater than the first height and less than the second height.

[0004] Embodiments of the present invention relate to an integrated circuit, comprising: a semiconductor substrate; and a device region including one or more fin field-effect transistors (finFETs). Each finFET in the device region includes one or more fins and a gate. The fins are formed having fin-shaped tops at a first height relative to the fin FET substrate region, the fin FET substrate region being adjacent to the fin-shaped tops. The gate is formed to cover one or more of the one or more fin-shaped tops. The device region includes a high-voltage (HV) plane region adjacent to the fin region. The HV plane region includes a first HV plane region and a second HV plane region. The first HV plane region has one or more planar transistor device structures formed at a second height relative to the fin FET substrate region, the second height being greater than the first height. The second HV plane region has an isolation structure that isolates the first HV plane region from the fin region. The isolation structure includes a boundary buffer having an intermediate step at a third height relative to the fin FET substrate region, the third height being equal to or greater than the first height and less than the second height.

[0005] An embodiment of the present invention relates to a method of manufacturing an integrated circuit, comprising: forming a fin region including one or more fin field-effect transistors (finFETs) and a planar region adjacent to the fin region in a device region of a semiconductor substrate, each fin field-effect transistor in the device region including one or more fins and a gate formed to cover one or more tops of the one or more fins, the planar region including one or more planar semiconductor device structures; and forming a sealing ring region surrounding the device region, the sealing ring region including an inner sealing ring surrounding the device region and an outer sealing ring surrounding the inner sealing ring and the device region, the outer sealing ring including a plurality of fins, each fin having a fin top at a first height from a fin substrate region adjacent to the fin, and the inner sealing ring including a planar boundary buffer adjacent to the planar region of the device region, the planar boundary buffer being formed at a second height from the fin substrate region, the second height being less than the first height. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1AThis is a cross-sectional view of an integrated circuit (IC) structure (Example 1) according to an exemplary embodiment of the present disclosure, which includes a fin field-effect transistor (finFET) region, a high voltage (HV) left plane region and a low / medium voltage (M / LV) right plane region, wherein the left plane region includes a boundary buffer of the left plane region and the right plane region includes a boundary buffer of the right plane region.

[0008] Figure 1B According to the exemplary embodiments disclosed herein Figure 1A A detailed cross-sectional view of the boundary buffer zone of the left planar region in the IC structure shown (Example 1).

[0009] Figure 1C According to the exemplary embodiments disclosed herein Figure 1A A detailed cross-sectional view of the boundary buffer of the right-side planar region in the integrated circuit IC structure shown (Example 1) includes a depiction of the slope of the boundary buffer relative to the height of the HV planar region and the LV fin field-effect transistor (finFET) region (Example 1).

[0010] Figure 2A This is a top view of a wafer including an IC structure, the IC structure including a planar region of a chip / IC / device area adjacent to a sealing ring surrounding the chip, the sealing ring including an outer dummy sealing ring, a finned intermediate sealing ring wall and an inner sealing ring (i.e., a seal ring enhanced zone (SREN)). According to an exemplary embodiment of this disclosure (Embodiment 2), the inner sealing ring includes a planar boundary buffer that reduces the step height from the fins of the sealing ring wall to the planar region of the chip, the planar boundary buffer being adjacent to the planar region of the chip.

[0011] Figure 2B Is it like this? Figure 2A The diagram shows a detailed top view of a wafer including an integrated circuit (IC) structure, and details of the external dummy sealing ring structure, the intermediate sealing ring wall (fin structure), and the internal sealing ring (planar boundary buffer) structure are shown according to an exemplary embodiment of this disclosure (Example 2).

[0012] Figure 2C According to the exemplary embodiments disclosed herein Figure 2A and 2B The cross-sectional view shown shows the planar boundary buffer zone of the sealing ring adjacent to the fin-like structure of the sealing ring wall and the planar region of the chip.

[0013] Figure 3This is a cross-sectional view of an IC structure (Example 3) according to an exemplary embodiment of the present disclosure, which includes a fin field-effect transistor (finFET) region and an interconnected HV left-side plane region, the left-side plane region including a buffer boundary buffer of the left-side plane region.

[0014] Figure 4 This is a semiconductor chip layout diagram based on an exemplary embodiment of the present disclosure, illustrating an IC layout arrangement, the IC layout including one or more boundary buffers.

[0015] Figure 5 A method for forming an IC according to an exemplary embodiment of the present disclosure is described, the IC including a fin field-effect transistor (finFET) region, an interconnected HV left-side plane region, and an interconnected M / LV right-side plane region, the left-side plane region including a boundary buffer of the left-side plane region, and the right-side plane region including a boundary buffer of the right-side plane region.

[0016] Figures 6A-6E The various stages of forming an IC (Example 5) according to an exemplary embodiment of the present disclosure are described. The IC includes a fin field-effect transistor (finFET) region, an interconnected HV left-side plane region, and an interconnected M / LV right-side plane region. The left-side plane region includes a boundary buffer of the left-side plane region, and the right-side plane region includes a boundary buffer of the right-side plane region. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Numerical values ​​in this disclosure and the claims should be understood to include values ​​that remain the same when reduced to the same number of significant figures, as well as values ​​that differ from those determined by experimental errors less than those determined by conventional measurement techniques of the type described in this disclosure. All scopes of this disclosure include the stated endpoints.

[0019] The term "approximately" can be used to include any different numerical value without altering its fundamental function. When used with a range, "approximately" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also indicates a range "from 2 to 4". The term "approximately" can be plus or minus 10% of the indicated numerical value.

[0020] This disclosure relates to structures composed of different layers. When the terms "on" or "on" are used to refer to two different layers (including a substrate), they simply mean that one layer is on or on another layer. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between them. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other, with no layers between them. Furthermore, when referring to performing process steps on a substrate, this should be interpreted as performing such steps on any layers that may be present on the substrate, depending on the context.

[0021] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0022] As used herein, the term "intermediate" or "intermediate step" refers to a step, platform, structure, or surface whose height is higher than the first end of the intermediate step and whose height is lower than or equal to the second end of the intermediate step.

[0023] As used in this article, the term "recess" in relation to boundary buffers refers to a surface or structure having a height or elevation that is lower than that of one or more adjacent boundary buffers.

[0024] As used herein, the terms “finFET base region” or “fin substrate region” or “fin top substrate region” refer to the first end or portion of a fin, wherein the fin extends from an adjacent shallow trench isolation (STI) material or other material to a second end, or from the finFET base region to the fin top.

[0025] The term "layer" as used in this document may include a single layer or multiple layers.

[0026] The term “conductive feature” as used in this article may refer to metallized layer contacts, patterned metallized layer contacts, or other electrically conductive metal contacts.

[0027] The term “intermetallic dielectric” (IMD) film or layer, as may be used in this article, refers to a dielectric / insulating material layer between two metal layers.

[0028] The term “interlayer dielectric” (ILD) may be used in this article to refer to an insulating material structure placed between two conductive layers.

[0029] Generally, some embodiments disclosed herein relate to semiconductor devices that use and / or form one or more fin field-effect transistors (FinFETs). FinFETs are named as such because the channel between the source and drain regions of a field-effect transistor (FET) typically takes the form of a three-dimensional (3D) straight wall or "fin," which is built on and / or rises from the semiconductor wafer. Therefore, a FinFET is a 3D transistor. The fins serve as the transistor channel, and the gate typically contacts the top and sides of the fins. Typically, FinFET devices have significantly faster switching times and higher current densities compared to planar transistor devices.

[0030] This disclosure and the exemplary embodiments described herein relate to the optimization of IC structure topology to employ various manufacturing processes used to manufacture ICs, thereby expanding the process window associated with these semiconductor manufacturing processes and reducing device defects in the manufacturing process. Generally, according to the exemplary embodiments, the applicable fields include, but are not limited to, high-voltage / medium-voltage / low-voltage integration processes, such as integration processes and manufacturing processes for interconnecting low-voltage (LV) (<3.3V), medium-voltage (MV) (3.3V–12V), and high-voltage (HV) (>12V) IC regions, integration processes and manufacturing processes for interconnecting LV (<3.3V) and HV (>20V) IC regions, and integration processes and manufacturing processes for interconnecting LV (<3.3V) and HV (>20V) IC regions, as well as integration processes typically used for planar regions of ICs for interconnection with adjacent fin regions manufactured using FinFET processes.

[0031] According to an exemplary manufacturing process, some conventional static random access memory (SRAM) ICs suffer manufacturing yield losses due to defects in the IC manufacturing process, particularly dummy polysilicon (“dummy polysilicon”) gates, especially 16HV isolation rings / structures. Transmission electron microscopy (TEM) analysis has revealed that the step height between the HV plane region and the FinFET LV region in these SRAM devices results in a relatively narrow process window because the FinFET fins are recessed below the HV plane region, and the height of the LV FinFET substrate region (i.e., the shallow trench isolation (STI) region adjacent to the FinFET fins) is significantly lower than the height of the HV plane region.

[0032] This disclosure and the exemplary embodiments provided herein offer solutions to improve IC manufacturing-related yields, as previously described, for adjacent HV and LV regions. These solutions are also applicable to other interconnected semiconductor structures, including planar regions interconnected with adjacent fin regions, such as LV regions, or any fin-containing regions, whether active or not (e.g., not limited to sealing rings containing fin structures adjacent to IC planar regions, HV, MV, LV regions, or other semiconductor structures where the height of the fin substrate region is lower than the height of adjacent or adjacent planar regions). The exemplary embodiments described herein add planar regions or boundary buffers, including recesses or buffers, between the fins and the planar boundary regions to minimize the step height slope from the fin substrate region to the upper or top surface of the relatively higher H / MV or other planar regions interconnected. This disclosure can expand the manufacturing process window compared to IC manufacturing-related process windows without the disclosed boundary buffers. In other words, based on the intermediate step of the boundary buffer located between the HV or higher HV plane region and the LVFinFET region in this example, this disclosure provides a reduced gradient of the step from the FinFET substrate region to the boundary buffer compared to the transition gradient from the FinFET substrate region to the higher interconnect plane region without using the boundary buffer disclosed herein. Therefore, the boundary buffer disclosed herein results in a reduction of device defects related to or caused by subsequent IC manufacturing processes such as forming and planarizing dielectric layers, e.g., interlayer dielectric (ILD) layers. In other words, the reduced slope between adjacent and adjacent planes and the fin material-filled region makes the surface relatively smoother to accommodate material-filling or forming processes.

[0033] Furthermore, according to some embodiments, the disclosed structure and its formation method utilize existing planar regions and existing processes in current manufacturing devices to manufacture currently manufactured devices. Therefore, according to some embodiments, the disclosed boundary buffer structure and method reduce the slope of the terrain from the plane to the fin boundary region by using existing IC regions and manufacturing processes, without increasing additional manufacturing costs compared to the manufacturing costs associated with similar devices that do not have the disclosed boundary buffer.

[0034] Another example of current semiconductor structures and related narrow process windows includes finned LV device regions and planar MV device regions covered by planar isolation rings to form isolation wells for each device. Here, the step height from the isolation ring to the fin region is relatively large because the fin region needs to be recessed to form the fin structure.

[0035] Another further example of existing semiconductor structures and associated narrow process windows includes a 16HV sealing ring having a fin region that includes a fin-like boundary region with a blank planar region or planar isolation ring with adjacent chips. Without using the boundary buffer disclosed herein, the sealing ring / chip topology can result in a narrower process window for subsequent device processing and negatively impact device yield due to the relatively large fin (sealing ring) to plane (chip) step height.

[0036] According to the exemplary embodiments described below, a wafer, IC, semiconductor device, or structure, and a method of manufacturing thereof, includes one or more boundary buffers having intermediate steps and / or recessed planar regions to minimize the step height slope of the transition from fin to planar region and the transition from planar region to fin. According to the following exemplary embodiments, Embodiment 1 1001 includes the use of a boundary buffer formed within an isolation ring structure that isolates (a) a boundary buffer of the HV plane region interconnected to a logic or LV FinFET region, and (b) a boundary buffer of the M / LV plane region interconnected to a logic or LV FinFET region; Embodiment 2 2001 includes the use of a boundary buffer formed within a Sealed Ring Reinforcement Region (SREZ) adjacent to or connected to the HV or M / LV plane region of the chip; Embodiment 3 3001 includes the use of a boundary buffer formed within an isolation ring structure that includes an STI trench deeper than the LV FinFET STI trench to reduce the step height from the FinFET substrate region to the adjacent HV plane region; and Embodiment 4 4001 includes a chip layout that includes Embodiment 1 1001 (see Figure 1A-1C Example 2 2001 (see Example 2 2001) Figure 2A-2C ) and Example 3 3001 (see Figure 3 One or more boundary buffers in ). Example 4 4001 (see Figure 4 The IC chip layout may include one or more of Embodiment 1 1001, Embodiment 2 2001 and Embodiment 3 3001.

[0037] According to some exemplary embodiments, the boundary buffer is formed with intermediate steps or grooves such that the step height from the higher metal-oxide-semiconductor (MOS) silicon HV / MV / LV planar region to the lower MOS LV logic fin region is less than 60 nanometers.

[0038] According to some exemplary embodiments, the boundary buffer is formed with an intermediate step or groove. In some exemplary embodiments, the boundary buffer with an intermediate step or groove is formed such that the step height from the planar region of the sealing ring (i.e., the boundary buffer) to the higher planar region of the chip is less than 60 nanometers, and the planar region of the chip is higher than the planar region of the sealing ring (i.e., the boundary buffer). According to this embodiment, the sealing ring fin region fabrication process is a fin region formation process related to the chip fin field-effect transistor (FinFET) fabrication process, wherein the sealing ring covers the boundary buffer. Since the original sealing ring is a fin region, and the chip region contacting the sealing ring is a planar region, the SREZ region of the sealing ring is modified from a fin type to a planar topology, thereby reducing the step height from the sealing ring to the chip boundary using existing integrated circuit manufacturing methods. Because there is no isolation ring between the chip and the boundary buffer of the sealing ring, no electrical operation is required.

[0039] According to some exemplary embodiments, the boundary buffer is formed with an intermediate step or groove such that the step height does not use an isolation ring or sealing ring, wherein the integrated circuit adds an additional area or region to accommodate the boundary buffer as disclosed.

[0040] According to some exemplary embodiments, the LV fin region serves as logic circuitry, providing LV voltage operation for high-speed, low-power, or SRAM functions, while the planar region interconnected with the LV logic circuitry includes MV and HV devices. According to some exemplary embodiments, the HV devices are used to drive and control the fin field-effect transistors (finFETs) of the LV logic circuitry, thereby controlling the transistors' on / off function. The MV devices are used to drive and control the transistor sources to control color and / or brightness via voltage bias, or to drive and control the digital-to-analog converter (DAC) function for signal transmission.

[0041] According to another exemplary embodiment, the existing integrated circuit layout includes a 40-nanometer step height or height offset from the top of the fin to the fin substrate region (i.e., STI), and a step height of approximately 30 nanometers from adjacent and interconnected planar H / MV regions to the fin substrate region STI. According to this exemplary embodiment, due to some limitations of the planar process used to manufacture this integrated circuit, a total step height of 70 nanometers from the H / MV planar region to the LV fin-type substrate region is desired. To accommodate the planar process, a boundary buffer is formed using the existing structure and available area of ​​this integrated circuit to achieve a plane-to-fin substrate region transition height (i.e., step) of less than 70 nanometers, or less than 60 nanometers, or less than 50 nanometers, etc.

[0042] According to some exemplary embodiments, a boundary buffer is used to create a planar boundary region height that is close to or equal to the height of the top of the LV fin region. In this case, the 40 nm step height between the planar boundary buffer and the fin STI, and the approximately 30 nm step height between the planar boundary buffer and the adjacent and interconnected HV planar regions, result in a total of approximately 70 nm from the HV planar regions to the STI fin substrate region of the LV logic circuit, which is consistent with the structural design constraints of the original integrated circuit before the addition of the boundary buffer. It should be understood that this is only an exemplary embodiment and scenario, and the boundary buffer disclosed herein can be adapted to other structural design constraints or requirements related to the integrated circuit structure. Specifically, the boundary buffer provides an intermediate step between the planar region and the fin region to adapt to the original integrated circuit structure that requires the total step height from the planar region to the LV fin substrate region to be greater than or less than 70 nm.

[0043] Reference Figure 1A The diagram shows a cross-sectional view (a cross-sectional view of the plane formed by the x and z directions perpendicular to the y direction) of an integrated circuit (IC) structure (Example 1) 1001 according to an exemplary embodiment of the present disclosure, which includes a fin field-effect transistor (finFET) region 100, an interconnect high voltage (HV) left plane region 200 (including a boundary buffer 230 from the left plane region to the fin region) and an interconnect low / medium voltage (M / LV) right plane region 300 (including a boundary buffer 330 from the right plane region).

[0044] As shown in the figure, this exemplary embodiment is an integrated circuit that includes the following: Semiconductor substrate 2, on which deep N-wells (DNW) 112, 212A, 212B and 312A, and core well 113 are formed; A fin region 100 is formed on the core well 113, the fin region having a first finFET transistor structure 111A, a second finFET transistor structure 111B, a third finFET transistor structure 111C, and a fourth finFET transistor structure 111D, and a shallow trench isolation (STI) region 115 formed next to each finFET transistor fin (see, for example, [link to relevant documentation]). Figure 1B (Fins 116A1, 116A2, 116B1, and 116B2). Each fin has polysilicon gates 117A, 117B, 117C, and 117D formed on it. The first planar region 200 has an H / MV region 210, on which deep N-wells 212A and 212B are formed, and on which a first (MOS) HV transistor device 211A and an HV MOS gate 216A, a second (MOS) HV transistor device 211B and an HV MOS gate 216B are formed. Planar HV P-wells 213A, 213B and 213C, and planar HV N-wells 214A, 214B and 214C are also formed in the HV planar region 200. STIs 215A, 215B, 215C, 215D, 215E, 215F, 215G, 215H, 215I, 215J and 215K are formed to provide isolation for the various depicted semiconductor regions for HV planar region operation, and a dummy polysilicon gate 217; and The second planar region 300 has an M / LV region 310, which is formed on a deep N-well 312A, and on which a first M / LV transistor device 311A ​​and an M / LV metal gate 316A, a second M / LV transistor device 311B and an M / LV metal gate 316B, and a third M / LV transistor device 311C and an M / LV metal gate 316C are formed. Planar M / LV P-well 313B, planar M / LV N-wells 314A and 314B, and M / LV region planar well 313A are also formed in the M / LV planar region 300. STI 315A, 315B, 315C, 315D, 315E, 315F, 315G, 315H, 315I, 315J, 315K, 315L, 315L, 315M, and 315N are formed to provide isolation for various depicted semiconductor regions for M / LV planar region operation.

[0045] The first planar region 200 also includes an isolation (ring) 220 structure having a boundary buffer 230 from the left planar region to the fin region and a top surface 231 of the boundary buffer from the left planar region to the fin region.

[0046] The second plane region 300 also includes an isolation (ring) structure 320 having a boundary buffer 330 from the right plane region to the fin region, and a top surface 331 of the boundary buffer from the right plane region to the fin region, wherein the isolation (ring) structure extends from STI 315N to plane M / LV P well 313B. The complete isolation (ring) structures 220 and 320 surround the LV logic region 100 structure.

[0047] According to an exemplary embodiment, an IC structure 1001 is formed on a wafer made of semiconductor material, wherein the integrated interconnect structure or integrated circuit (IC) structure 1001 is built or formed thereon using conventional semiconductor manufacturing techniques, including but not limited to photolithography, such as applying a photoresist layer, patterning a photoresist layer, developing the photoresist layer, then etching, followed by planarization and cleaning, to apply a pattern / structure in a given layer. While the specific semiconductor manufacturing process required to form the illustrated IC structure 1001 is not the focus of this disclosure, for completeness, a general description of the semiconductor manufacturing process is provided below.

[0048] The semiconductor substrate 2 material may include silicon, for example, in the form of crystalline silicon or polycrystalline silicon. In alternative embodiments, the substrate may be made of other elemental semiconductors, such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In a particular embodiment, the wafer substrate is silicon.

[0049] Typically, photoresist layers can be applied using methods such as spin coating, spray coating, roller coating, dip coating, or extrusion coating. In spin coating, the substrate is typically placed on a rotating platform, which may include a vacuum fixture to hold the substrate in place. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to allow the photoresist to spread uniformly from the center of the substrate to its periphery. The rotational speed of the platform is then fixed, which controls the final thickness of the photoresist layer.

[0050] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate or oven, or similar equipment. Thus, a photoresist layer is formed on the substrate.

[0051] The photoresist layer is then patterned by radiation exposure. The radiation can be any wavelength of light carrying the desired mask pattern. In a particular embodiment, extreme ultraviolet light with a wavelength of about 13.5 nanometers is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation, while other portions are not. This exposure makes some portions of the photoresist soluble in the developer, while other portions remain insoluble.

[0052] An additional photoresist baking step (post-exposure baking, or PEB) may be performed after radiation exposure. For example, this may help release acid leaving groups (ALGs) or other molecules that are important in chemically amplified photoresists.

[0053] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. The soluble portions of the photoresist layer are dissolved and rinsed away during the development step, leaving the photoresist pattern. A common example of a developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers may include 2-heptanone, butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate or propylene glycol monomethyl ether acetate, amyl acetate, butyl propionate, hexyl acetate, butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, a post-development bake or "hard bake" may be performed after development to stabilize the developed photoresist pattern for optimal performance in subsequent steps.

[0054] Next, portions of the layer beneath the patterned photoresist layer are now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. The patterned photoresist layer can be removed after use, for example, by using various solvents such as N-methylpyrrolidone (NMP) or alkaline media or other stripping agents at elevated temperatures, or by dry etching using oxygen plasma.

[0055] Generally, any etching step used in this article may employ wet etching, dry etching, or plasma etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or combinations thereof, as appropriate. Etching may be anisotropic. Depending on the material, the etching agent may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), fluorides, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), or similar substances, or combinations thereof, in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4 and / or H2.

[0056] Planarization can be performed to obtain a flat surface. Planarization can be performed, for example, using a chemical mechanical polishing (CMP) process. Typically, CMP is performed using a rotating platform with a polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier rotate, which creates mechanical and chemical effects on the surface of the wafer substrate and / or its top layers, removing unwanted material and creating a highly flat surface. A post-CMP cleaning step is then performed using a rotating brush and cleaning solution to clean one or both sides of the wafer substrate.

[0057] Finally, cleaning steps such as wet cleaning can be performed between various process steps. The cleaning solution will depend on the etching formulation and the exposed layers. Examples of cleaning solutions may include deionized water, diluted HF, and other conventional solutions.

[0058] The dielectric structure can be made from any suitable combination of dielectric materials. Examples of dielectric materials include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon oxynitride (SiO2). x N y Hafnium oxide (HfO) x N y ) or zirconium oxynitride (ZrO) x N y ), or hafnium silicate (ZrSi)x O y ) or zirconium silicate (ZrSi) x O y ) or silicon dioxide (SiC) x O y N z Alternatively, it can be hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0059] Any conductive material discussed herein, such as the metal vias 240A and 240B, can generally be any conductive metal or conductive oxide. Examples of suitable metals include copper, aluminum, nickel, chromium, gold, germanium, silver, titanium, tungsten, platinum, tantalum, ruthenium, cobalt, rhenium, palladium, or zirconium; composite materials such as TiN, WN, or TaN; or alloys thereof such as AlCu. Examples of suitable conductive oxides include indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), zinc aluminum oxide (AlZnO), indium oxide (InO), or cadmium oxide (CdO). Metallic or oxide materials can be deposited, for example, by vapor deposition or sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods.

[0060] like Figure 1A as well as Figure 1B As shown, the HV plane region 210 is the highest point in the IC chip / semiconductor structure 1001, while the highest point of the M / LV plane region 310 is at the same vertical height as the fin region 100. Therefore, the boundary buffer 230 implemented in the first or left plane region 200 may have a different intermediate or recessed step height than the boundary buffer 330 implemented in the second or right plane region 300. For example, according to some embodiments, the step height from the HV plane region 210 to the fin substrate region 118 is less than 70 nanometers, while the step height from the M / LV plane region 310 to the fin substrate region 118 is less than 60 nanometers. Although Figure 1A As shown in other figures, the M / LV plane region 310 has the same height as the fin region 100, but the M / LV plane region 310 may extend further vertically (in the z-direction), depending on the voltage plateau it accommodates. However, unless the right-hand plane region 300 is an HV plane region, the vertical height of the M / LV plane region 310 will be less than that of the HV plane region 210 and greater than or equal to the vertical height of the fin region 100.

[0061] also, Figure 1AThe HV plane region 200 shown includes an isolation ring 220 (near the fin region) which is manufactured or modified to include a boundary buffer 230, while the M / LV plane region 300 includes an isolation ring 320 which is manufactured or modified to include a boundary buffer 330. Figure 1A The example structure shown is a general structure for a display driver IC used for mixed LV, MV, and HV devices. The SRAM of the display driver IC (DDIC) is part of the FinFET region 100 with isolation rings 220 and 320, while the LV, MV, and HV devices are adjacent to the isolation rings 220 and 320 of the SRAM. Other LV functions associated with the M / LV region 300 may include, but are not limited to, a timing controller (TCON). The SRAM or FinFET region 100 consists of FinFET bit cells and needs to be surrounded by isolation rings (planar regions) 220 and 330 to block MV or HV voltages near the FinFET region 100 or the SRAM region.

[0062] Reference Figure 1B as well as Figure 1A According to one embodiment of the present disclosure, it is shown as follows: Figure 1A A detailed cross-sectional view of the boundary buffer zone of the left planar region of the IC structure shown (Example 1).

[0063] According to one embodiment, Table 1 below provides various size labels and example size ranges for reference in the figures.

[0064] [Table 1]

[0065] According to an illustrative example, if the height H5 from the HV plane region to the fin top is X nanometers, by implementing the disclosed boundary buffer 230, the height H6 from the HV plane region to the LV fin substrate is less than or equal to X+10 nanometers. If the boundary buffer length L1 is Y nanometers, X+10 / Y (e.g., the slope S1) is less than or equal to 1 / 80.

[0066] Reference Figure 1C As shown Figure 1A The detailed cross-sectional view of the boundary buffer 330 of the right-side planar region of the integrated circuit IC structure shown in the present disclosure (Embodiment 1) includes a depiction of the slope of the boundary buffer relative to the height of the M / LV planar region 310 and the LV fin field-effect transistor region 100 (Embodiment 1) according to an embodiment of the present disclosure.

[0067] As previously mentioned, the function of the HV boundary buffer 230 and the M / LV boundary buffer 330 is to reduce or lower the slope from the planar region to the fin region boundary. The required length of the boundary buffer depends on the height H2 and the height H8. If the length of the boundary buffer is too short, the transition height or slope from the fin substrate 118 to the top surface of the boundary buffer plane may be too steep to accommodate certain subsequent processes, such as planarization, within the required process window. The slope is defined as the height H6 from the LV fin substrate 118 (STI) to the top surface of the HV planar region 210, and the height H11 from the LV fin substrate (STI) to the top surface of the M / LV planar region 310, as follows: Figure 1B and 1C As shown, divide by the lengths L1 and L2 of the boundary buffer, respectively. According to an example IC embodiment, it is expected that the boundary buffer lengths (L1, L2) will produce a boundary buffer slope (S1, S2) < 1:80.

[0068] Reference Figure 2A The diagram shows a top view of a portion of a die, including an IC structure 3. This includes a planar region of the chip / IC / device area adjacent to a sealing ring 400 surrounding the chip 3. The sealing ring 400 includes external dummy sealing ring structures 430A and 430B, a finned intermediate sealing ring wall 420, and an in-plane sealing ring buffer 410, i.e., a sealing ring reinforcement region (SREN). The in-plane sealing ring buffer 410 includes a boundary buffer according to an embodiment (Embodiment 2) of this disclosure, which reduces the distance from the sealing ring wall fin 423 (see...). Figure 2B and 2C The step height of the chip's planar region adjacent to the boundary buffer zone of the internal sealing ring. Figure 2B Display as shown Figure 2A The figure shows a detailed top view of the wafer die portion including the integrated circuit (IC) structure, showing details of the outer dummy sealing ring structures 430A and 430B, the fin structure of the intermediate sealing ring wall 420, and the structure of the inner sealing ring buffer 410. Figure 2C show Figure 2A and 2B The cross-sectional view shown is of the sealing ring buffer zone 410 adjacent to the fin structure of the sealing ring wall 420 and the planar region of the chip 3.

[0069] Example 2 IC structure includes a sealing ring 400 surrounding an IC chip 3, such as one or both of the previously described Examples 11001 and 22001, but not limited to these examples. The sealing ring 400 has an inner sealing ring boundary buffer zone 410, including a planar layer 411 and a dummy polysilicon gate 414; an intermediate sealing ring wall (fin structure) 420; and outer dummy sealing rings 430A and 430B. The intermediate sealing ring wall 420 has a plurality of fins 423 formed using a sacrificial element 422 and a dummy polysilicon gate 424, and the outer dummy rings have a plurality of fins 433 formed using a sacrificial element 432 and a dummy polysilicon gate 434. The outer dummy sealing rings 430A and 430B include a metal layer (active layer) 435 formed therein, and the intermediate sealing ring wall 420 includes a metal layer (active layer) 435 formed therein.

[0070] and Figure 1A-1C Unlike the boundary buffer integration shown, the integration of the sealing ring boundary buffer aims to form an intermediate step or transition from the sealing ring fin substrate region 426 to the planar region or surface on the chip 3 surrounded by the sealing ring 400. The sealing ring intermediate step provides a reduction in the gradient (i.e., slope) from the sealing ring fin substrate region 426 to the adjacent chip planar surface 3, which can be a high-voltage (HV) planar region, a medium-voltage (MV) planar region, a low-voltage (LV) planar region, and / or a planar region as part of a high-voltage / medium-voltage / low-voltage isolation structure.

[0071] According to exemplary embodiment 2001, embodiment 2001 includes a boundary buffer implemented by modifying an existing sealing ring to have a planar groove, thereby reducing the step height from the sealing ring to the surface of the planar region of the adjacent chip. The sealing ring structure 400 is modified from being entirely finned to include an internal sealing ring buffer 410 comprising a fin + plane (SREZ), which reduces or shortens the boundary step height from the sealing ring to the adjacent chip. The SREZ is a reserved space between the chip 3 and the sealing ring wall 420 to prevent dicing stress from damaging the chip.

[0072] According to an exemplary embodiment, the lengths of the dummy sealing ring structures 430A and 430B are approximately 3.6 to 7.2 micrometers, also referred to as "cut-line dummy strips". More specifically, according to an exemplary embodiment, the lengths of the dummy sealing ring structures 430A and 430B are approximately 7.2 micrometers. In practice, the lengths of the dummy sealing ring structures 430A and 430B depend on the cutting capability. In chip region 2, according to an exemplary embodiment, the sacrificial width / pitch is approximately 48 nanometers / 48 nanometers, however, the sealing ring width / pitch is designed to be approximately 140 nanometers / 140 nanometers. The sacrificial used to form the sealing ring fin pattern can also be used during the formation of other fins of the IC, such as fin region transistor fins.

[0073] According to exemplary embodiments, the length of the sealing ring wall is approximately 2.7 micrometers to 5.4 micrometers, depending on the resistance of the sealing ring wall and its resistance to stress and moisture. More specifically, according to some embodiments, the length of the sealing ring wall 420 is approximately 5.4 micrometers.

[0074] The boundary buffer or internal sealing ring buffer 410 (internal sealing ring) has a planar area width of approximately 2.7 micrometers to 6 micrometers. More specifically, according to some embodiments, the boundary buffer width is approximately 2.46 micrometers. According to exemplary embodiments, the sealing ring 400 and the adjacent planar chip area use the same manufacturing process as chip 3, which is manufactured / processed concurrently with the manufacturing / processing of the sealing ring. Examples of sealing ring materials include, but are not limited to, silicon, oxides, metals, passivation materials, etc.

[0075] Based on exemplary embodiments, Table 2 below provides various size labels and exemplary size ranges.

[0076] [Table 2]

[0077] Reference Figure 3 The diagram shows a cross-sectional view of an IC structure (Example 3) 3001, including a finFET region 3100 and an interconnect high voltage left-side planar region 3200, including a planar region-fin region boundary buffer (isolation (ring)) 3220 according to an exemplary embodiment of the present disclosure.

[0078] As shown in the figure, an exemplary embodiment is an IC that includes the following: Semiconductor substrate 3002 has an HV planar region 3211, a low-voltage fin region 3100, and an isolation (ring) structure 3220 (i.e., an isolation ring is formed therein). STI regions 3215A, 3215B, 3215C, and 3215D are further formed in semiconductor substrate 3002. Fin region 3100 has a first FinFET transistor structure 3111A, a second FinFET transistor structure 3111B, and a third FinFET transistor structure 3111C. STI regions 3115A, 3115B, and 3115C are formed adjacent to each FinFET transistor fin 3112A, 3112B, and 3112C. A polysilicon gate (not shown) is formed on each fin; and The HV plane region 3200 has an HV region 3210, on which high-voltage STIs 3215A, 3215B, 3215C, and 3215D are formed, and on which high-voltage (MOS) transistor devices 3211 and high-voltage MOS gates / GOX (gate oxide) 3218 are formed. High-temperature dielectric (HTO) regions 3501A, 3501B, 3501C, and 3501D are also formed in the HV plane region to provide isolation for the various semiconductor regions depicted for operation of the HV plane region.

[0079] ILD0 layers / regions 3502A, 3502B, 3502C, 3502D and 3502F are formed on the high-pressure and low-pressure devices shown for the planarization process.

[0080] Similar to previous references Figure 1A -C describes the boundary buffer, IC includes a boundary buffer 3230 having a height H2 of about 35 nanometers to about 45 nanometers and a slope S1 of less than 1:80.

[0081] and Figure 1A-1C Unlike the boundary buffer integration shown, the boundary buffer 3230 integration in Embodiment 3 is designed to form an intermediate step or transition from the HV plane region 3210 to the LV fin substrate region 3118, wherein the IC structure includes an isolation ring 3220 or a structure formed by the mesa of STI 3215B, 3215C and 3215D, and has mesa tops 3216A, 3216B and 3216C respectively, the height of which is lower than the LV fin top.

[0082] Reference Figure 4 The diagram illustrates a semiconductor chip layout 4002, illustrating an IC layout arrangement according to an exemplary embodiment (Embodiment 4) 4002 disclosed herein. The IC layout includes the previously described HV plane region 200 and M / LV plane region 300. As shown, Embodiment 4 4001 further includes high-density devices 4003A, 4003B, 4003C, 4003D, 4003E, 4003F, and 4003G; medium-voltage devices 4004A, 4004B, and 4004C; and low-voltage devices 4005A, 4005B, and 4005C. A dummy high-voltage isolation ring 4006 surrounds each low-voltage and medium-voltage device to isolate the operation of the low-density and medium-density devices from the high-density devices, and a high-voltage isolation ring 4007 is formed to cover areas in chip 4002 not used by the low-voltage, medium-voltage, and high-voltage devices. A sealing ring 4008 prevents dicing stress from damaging chip 4002.

[0083] According to an exemplary embodiment, and to further aid in understanding the boundary buffer structure disclosed herein, a boundary buffer 230 (not shown) is integrated into the HV plane region 200 of the high-voltage device 4003A. The boundary buffer 230 (not shown) reduces and / or provides an intermediate step from the plane region of the high-voltage device 4003A to the finned substrate region of the low-voltage device 4005A, as previously referenced. Figure 1A-1C and / or Figure 3 As described above. Furthermore, a boundary buffer 330 (not shown) is integrated into the M / LV plane region 300 of the intermediate voltage device 4004A, the boundary buffer 330 (not shown) reducing and / or providing an intermediate step from the plane region of the intermediate voltage device 4004A to the finned substrate region of the low voltage device 4005A, as previously referenced. Figure 1A-1C and / or Figure 3 As described above. Furthermore, the sealing ring 4008 may include a sealing ring structure comprising an inner sealing ring having a boundary buffer zone 410 (not shown), as previously referenced. Figure 2A-2C As described, the sealing ring boundary buffer provides an intermediate step from the sealing ring 4008 to the planar surface of the chip 4002 / isolation ring 4007 and / or dummy isolation ring 4006, as previously described.

[0084] Reference Figure 5 This describes the various stages of forming an IC, including a finFET region, an interconnect high voltage left plane region (including a boundary buffer from the left plane region to the fin region), and an interconnect M / LV right plane region (including a boundary buffer from the right plane region), according to an exemplary embodiment disclosed herein.

[0085] In step 501, the method forms a fin region in a device region of a semiconductor substrate, comprising one or more fin field-effect transistors (finFETs), each device region finFET comprising one or more fins, forming a finFET substrate region with its fin tops adjacent to the fins having a first height, and forming a gate to cover one or more fin tops.

[0086] In step 502, the method is formed in the device region of the semiconductor substrate. (1) A high-voltage (HV) planar region adjacent to the fin region, the HV planar region comprising a first HV planar region having one or more planar transistor device structures forming a second height at a distance from the finFET substrate region, the second height being greater than the first height, and a second HV planar region having a high-voltage isolation structure isolating the first HV planar region from the fin region, the high-voltage isolation structure including a boundary buffer having an intermediate step at a third height at a distance from the finFET substrate region, the third height being equal to or greater than the first height and less than the second height; and (2) (Selective) medium / low voltage (M / LV) planar regions adjacent to and separated from the HV plane, the M / LV planar regions including a first M / LV planar region having one or more planar transistor device structures forming a second height at a distance from the finFET substrate region, the second height being greater than the first height, and a second M / LV planar region having an M / LV isolation structure that isolates the first M / LV planar region from the fin region, the M / LV isolation structure including a boundary buffer with an intermediate step at a third height at a distance from the finFET substrate region, the third height being equal to or greater than the first height and less than the second height.

[0087] Some processes that can be used to form the IC disclosed herein include chemical mechanical polishing (CMP), wet etching, and photolithography to confine the CMP / chemical etching areas. According to some exemplary embodiments, the boundary buffer intermediate step is formed by removing material from the existing isolation ring region surrounding the IC logic low-voltage fin region, or in the case of Embodiment 3, the boundary buffer is integrated with a sealing ring by removing material from the sealing ring inside the sealing ring release zone (SREZ) to form a planar intermediate step between the sealing ring and the adjacent IC chip planar region.

[0088] In Example 1, where the IC includes an HV planar region and an M / LV planar region, a medium-pressure process mask is used to define the intermediate step / groove region of the boundary buffer in the isolation ring, and the medium-pressure process mask is also used to define the seal ring release zone (SREZ) of the seal ring using a photolithography process. Then, a groove / step formation process is performed using a dry chemical etching process. (Fin groove formation is performed after the planarization process.) The result is a step height to the fin substrate region similar to the boundary buffer of the medium-pressure planar region, but with high-pressure wells in these regions for isolation purposes.

[0089] Reference Figures 6A-6E This describes the various stages of forming an IC (Example 5) 5001, comprising a FinFET region, an interconnected HV left-side plane region (including a boundary buffer of the left-side plane region), and an interconnected M / LV right-side plane region (including a boundary buffer of the right-side plane region), according to an exemplary embodiment of this disclosure.

[0090] Figure 6A As previously explained Figure 1A-1C The initial stage 601 for forming the boundary buffer is described, wherein the IC structure state initially formed is previously formed using the previously described semiconductor manufacturing photolithography process. The fin region 100, HV plane region 210, and selective M / LV plane region 310, as well as isolation rings 220 and 320, and boundary buffers 230 and 330 are substantially previously referenced. Figure 1A-1CThe functional equivalents of the same reference characters described will not be repeated here.

[0091] As shown in the figure, in the initial stage 601 of the process, the semiconductor IC structure is previously formed to include a recess height R1, which is the initial recess height of the high voltage gate oxide (HVGOX) gate 216B to the high voltage STI 215E of the HV plane region 210 before the formation of the boundary buffer 230, for example, about 100 nanometers. Furthermore, the semiconductor IC structure is previously formed to include a recess height R2, which is the initial recess height of the isolation ring plane region 220 relative to the high voltage STI 215I before the formation of the boundary buffer 230, for example, 100 nanometers.

[0092] The process or manufacturing steps described below focus on forming the planar HV boundary buffer 230 (see [link]). Figure 6E However, it should be understood that a similar process is performed concurrently with the fabrication of the HV boundary buffer to form the M / LV boundary buffer 330 (see [link to relevant documentation]). Figure 6E ).

[0093] Figure 6B This describes stage 602 of the boundary buffer manufacturing process, including... Figure 6A An MVGOX (medium-voltage gate oxide) layer 716 is formed on the structure, thereby covering the entire surface of the HV plane region 210, the isolation ring structure 220, the fin region 100, the isolation ring structure 320, and the M / LV plane region 310. Further etching is performed to etch the MVGOX layer 716, forming a trench height R3, which is the trench height from the high-voltage gate oxide (HVGOX) gate 216B to the high-voltage STI 215E in the HV plane region 210 after etching, for example, approximately 300 nanometers.

[0094] Figure 6C The next stage 603 describes applying a hard mask 717 to the MVGOX layer 716 and performing an etching process to remove a portion of the STI material 115 and form a groove for the fin 116, which also provides a groove height R4, for example, 400 nanometers, from the top surface 231 of the high-voltage isolation ring planar region 210 / boundary buffer.

[0095] Figure 6D Explain the next stage of 604, including... Figure 6C A polysilicon layer 718 is applied to the entire surface of the structure shown, and a CMP process is performed to planarize the surface. For reference, regions 718A, 718B, and 718C are outlined. Figure 6E The polysilicon gates 718A, 718B, and 718C subsequently formed in the next stage are shown.

[0096] Figure 6EThe next stage 605 describes performing a photolithography process to etch the CMP planarization surface of the polysilicon layer 718 and form polysilicon gates 718A, 718B, and 718C. The resulting semiconductor IC structure 5001 includes completed boundary buffers 230 and 330, which are formed and integrated into isolation rings 220 and 320, respectively.

[0097] Based on the foregoing discussion, it is clear that this disclosure offers advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor are specific advantages required for all embodiments. One advantage is that the disclosed integrated circuit boundary buffer provides a reduced step height from the fin region to the adjacent planar region, which in turn may improve the process window associated with one or more subsequent semiconductor manufacturing processes.

[0098] Some further embodiments are described below.

[0099] In a non-limiting illustrative embodiment, a method of manufacturing an integrated circuit includes: forming a fin region comprising one or more fin field-effect transistors (finFETs) in a device region of a semiconductor substrate, each of the device regions having one or more fins and a gate, the fins being formed having fin-shaped tops at a first height relative to a fin field-effect transistor substrate region, the fin field-effect transistor substrate region being adjacent to the fin-shaped tops, and the gates being formed to cover the one or more fin-shaped tops; and forming a high-voltage (HV) plane region adjacent to the fin region in the device region of the semiconductor substrate, the HV plane region... The surface region includes a first HV plane region and a second HV plane region. The first HV plane region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region. The second height is greater than the first height. The second HV plane region has an HV isolation structure that isolates the first HV plane region from the fin region. The HV isolation structure includes a boundary buffer. The boundary buffer has an intermediate step at a third height from the fin field-effect transistor substrate region. The third height is equal to or greater than the first height and less than the second height.

[0100] In one embodiment, the boundary buffer has a slope defined as the second height divided by the length of the boundary buffer, and the slope is less than or equal to 1:80. In one embodiment, the method further includes: forming a high-voltage (HV) circuit in the HV plane region; and forming a low-voltage (LV) circuit on the fin region, controlled by the HV circuit, the HV circuit operating at a voltage range greater than about 12 volts, and the LV circuit operating at a voltage range greater than about 3 volts and less than about 12 volts. In one embodiment, the first height is about 35 nanometers to about 45 nanometers, and the third height is about 35 nanometers to about 45 nanometers. In one embodiment, the first height is substantially equal to the third height. In one embodiment, the boundary buffer is formed by a method including the step of performing a photolithography process to etch at least a portion of the isolation structure to form a groove at the third height, the groove defining the intermediate step of the boundary buffer. In one embodiment, the HV isolation structure is an isolation ring. In one embodiment, the method further includes: forming a medium / low voltage (M / LV) planar region adjacent to the fin region and separated from the HV plane in the device region of the semiconductor substrate; the M / LV planar region includes a first M / LV planar region and a second M / LV planar region; the first M / LV planar region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region, the second height being greater than the first height; and the second M / LV planar region has an M / LV isolation structure that isolates the first M / LV planar region from the fin region; the M / LV isolation structure includes a boundary buffer having an intermediate step at a third height from the fin field-effect transistor substrate region, the third height being equal to or greater than the first height and less than the second height. In one embodiment, the second height of the HV planar region is greater than the second height of the M / LV planar region. In one embodiment, the third height of the boundary buffer of the HV planar region is substantially equal to the third height of the boundary buffer of the M / LV planar region.

[0101] In another non-limiting illustrative embodiment, an integrated circuit includes: a semiconductor substrate; and a device region including one or more fin field-effect transistors (finFETs). Each finFET in the device region includes one or more fins and a gate. The fins are formed with fin-shaped tops at a first height relative to the fin FET substrate region, the fin FET substrate region being adjacent to the fin-shaped tops. The gate is formed to cover one or more of the one or more fin-shaped tops. The device region includes a high-voltage (HV) plane region adjacent to the fin region. The HV plane region includes a first HV plane region and a second HV plane region. The first HV plane region has one or more planar transistor device structures formed at a second height relative to the fin FET substrate region, the second height being greater than the first height. The second HV plane region has an isolation structure that isolates the first HV plane region from the fin region. The isolation structure includes a boundary buffer having an intermediate step at a third height relative to the fin FET substrate region, the third height being equal to or greater than the first height and less than the second height.

[0102] In one embodiment, the boundary buffer has a slope defined as the second height divided by the length of the boundary buffer, and the slope is less than or equal to 1:80. In one embodiment, the first height is about 35 nanometers to about 45 nanometers, the third height is about 35 nanometers to about 45 nanometers, and the first height is substantially equal to the third height. In one embodiment, the HV isolation structure is an isolation ring. In one embodiment, the device region further includes: a medium / low voltage (M / LV) planar region adjacent to the fin region and separated from the HV plane; the M / LV planar region includes a first M / LV planar region and a second M / LV planar region; the first M / LV planar region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region, the second height being greater than the first height; the second M / LV planar region has an M / LV isolation structure that isolates the first M / LV planar region from the fin region; the M / LV isolation structure includes a boundary buffer having an intermediate step at a third height from the fin field-effect transistor substrate region, the third height being equal to or greater than the first height and less than the second height. In one embodiment, the second height of the HV planar region is greater than the second height of the M / LV planar region. In one embodiment, the third height of the boundary buffer of the HV planar region is substantially equal to the third height of the boundary buffer of the M / LV planar region.

[0103] In another non-limiting illustrative embodiment, a method of manufacturing an integrated circuit includes: forming a fin region comprising one or more fin field-effect transistors (finFETs) and a planar region adjacent to the fin region in a device region of a semiconductor substrate, each fin field-effect transistor in the device region comprising one or more fins and a gate formed to cover one or more tops of the one or more fins, the planar region comprising one or more planar semiconductor device structures; and forming a sealing ring region surrounding the device region, the sealing ring region comprising an inner sealing ring surrounding the device region and an outer sealing ring surrounding the inner sealing ring and the device region, the outer sealing ring comprising a plurality of fins, each fin having a fin top at a first height from a fin substrate region adjacent to the fin, and the inner sealing ring comprising a planar boundary buffer adjacent to the planar region of the device region, the planar boundary buffer being formed at a second height from the fin substrate region, the second height being less than the first height.

[0104] In one embodiment, the planar region of the device area is adjacent to the inner sealing ring, and the planar region of the device area is at a third height from the finned substrate region of the outer sealing ring, and the third height is greater than the second height, thereby providing an intermediate step from the inner sealing ring to the planar region of the device area. In one embodiment, the first height is about 35 nanometers to about 45 nanometers, and the second height is about 35 nanometers to about 45 nanometers.

[0105] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit, comprising: In a device region of a semiconductor substrate, a fin region comprising one or more fin field-effect transistors is formed. Each fin field-effect transistor in the device region includes one or more fins and a gate. The fins are formed to have fin-shaped tops at a first height from the fin field-effect transistor substrate region. The fin field-effect transistor substrate region is adjacent to the fin-shaped tops. The gate is formed to cover one or more of the fin-shaped tops. as well as In the device region of the semiconductor substrate, a high-voltage plane region adjacent to the fin region is formed. The high-voltage plane region includes a first high-voltage plane region and a second high-voltage plane region. The first high-voltage plane region has one or more planar transistor device structures. The planar transistor device structures are formed at a second height from the fin field-effect transistor substrate region. The second height is greater than the first height. The second high-voltage plane region has a high-voltage isolation structure that isolates the first high-voltage plane region from the fin region. The high-voltage isolation structure includes a boundary buffer. The boundary buffer has an intermediate step at a third height from the fin field-effect transistor substrate region. The third height is equal to or greater than the first height and less than the second height.

2. The method of claim 1, wherein the boundary buffer has a slope defined as the second height divided by the length of the boundary buffer, and the slope is less than or equal to 1:

80.

3. The method of claim 1, wherein the first height is substantially equal to the third height.

4. The method of claim 1, wherein the boundary buffer is formed by a method comprising the following steps: A photolithography process is performed to etch at least a portion of the isolation structure to form a groove at the third height, the groove defining the intermediate step of the boundary buffer.

5. The method according to claim 1, further comprising: In the device region of the semiconductor substrate, a medium / low voltage plane region is formed adjacent to the fin region and separated from the high voltage plane. The medium / low voltage plane region includes a first medium / low voltage plane region and a second medium / low voltage plane region. The first medium / low voltage plane region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region, the second height being greater than the first height. The second medium / low voltage plane region has a medium / low voltage isolation structure that isolates the first medium / low voltage plane region from the fin region. The medium / low voltage isolation structure includes a boundary buffer, the boundary buffer having an intermediate step at a third height from the fin field-effect transistor substrate region, the third height being equal to or greater than the first height and less than the second height.

6. An integrated circuit, comprising: Semiconductor substrate; as well as A device region includes one or more fin field-effect transistors (FETs). Each FET in the device region includes one or more fins and a gate. The fins are formed with fin-shaped tops at a first height relative to the FET substrate region. The FET substrate region is adjacent to the fin-shaped tops. The gate is formed to cover one or more of the one or more fin-shaped tops. The device region includes a high-voltage plane region adjacent to the fin region. The high-voltage plane region includes a first high-voltage plane region and a second high-voltage plane region. The first high-voltage plane region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region. The second height is greater than the first height. The second high-voltage plane region has an isolation structure that isolates the first high-voltage plane region from the fin region. The isolation structure includes a boundary buffer. The boundary buffer has an intermediate step at a third height from the fin field-effect transistor substrate region. The third height is equal to or greater than the first height and less than the second height.

7. The integrated circuit of claim 6, wherein the boundary buffer has a slope defined as the second height divided by the length of the boundary buffer, and the slope is less than or equal to 1:

80.

8. The integrated circuit according to claim 6, further comprising: The device region includes a medium / low voltage plane region adjacent to the fin region and separated from the high voltage plane. The medium / low voltage plane region includes a first medium / low voltage plane region and a second medium / low voltage plane region. The first medium / low voltage plane region has one or more planar transistor device structures formed at a second height from the fin field-effect transistor substrate region. The second height is greater than the first height. The second medium / low voltage plane region has a medium / low voltage isolation structure that isolates the first medium / low voltage plane region from the fin region. The medium / low voltage isolation structure includes a boundary buffer. The boundary buffer has an intermediate step at a third height from the fin field-effect transistor substrate region. The third height is equal to or greater than the first height and less than the second height.

9. A method for manufacturing an integrated circuit, comprising: A fin region comprising one or more fin field-effect transistors and a planar region adjacent to the fin region are formed in a device region of a semiconductor substrate. Each fin field-effect transistor in the device region includes one or more fins and a gate formed to cover one or more tops of the one or more fins. The planar region includes one or more planar semiconductor device structures. A sealing ring region is formed around the device area, the sealing ring region including an inner sealing ring surrounding the device area and an outer sealing ring surrounding the inner sealing ring and the device area, the outer sealing ring including a plurality of fins, each fin having a fin-shaped top at a first height from a fin-shaped substrate area adjacent to the fin, and the inner sealing ring including a planar boundary buffer adjacent to the planar area of ​​the device area, the planar boundary buffer being formed at a second height from the fin-shaped substrate area, the second height being less than the first height.

10. The method of claim 9, wherein the planar region of the device area is adjacent to the inner sealing ring, and the planar region of the device area is at a third height from the finned substrate region of the outer sealing ring, and the third height is greater than the second height, thereby providing an intermediate step from the inner sealing ring to the planar region of the device area.

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