Display device, optical device, and electronic device

Abstract

A display device, an optical device, and an electronic device are provided. The display device includes: a substrate; a first electrode on the substrate; a pixel defining film on the first electrode; a light emitting stack on the first electrode and the pixel defining film; a second electrode on the light emitting stack; and an encapsulation layer on the second electrode, in which the encapsulation layer includes a plurality of sub-encapsulation layers, and at least two ends of the plurality of sub-encapsulation layers are aligned in one direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0135381, filed on October 7, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and for example, to display devices that can reduce manufacturing costs and improve reliability, optical devices including display devices, electronic devices including display devices, and methods for manufacturing display devices. Background Technology

[0004] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to create a focused image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0005] Head-mounted displays magnify images displayed on small display devices using multiple lenses, and display the magnified image. Therefore, it is desirable for display devices used in head-mounted displays to provide high-resolution images (e.g., images with a resolution of 3000 PPI (pixels per inch) or higher). For this purpose, organic light-emitting diodes on silicon (OLEDoS), which are high-resolution, small organic light-emitting display devices, can be used as display devices for head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed.

[0006] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure and may contain information that does not constitute prior art. Summary of the Invention

[0007] Embodiments of this disclosure relate to display devices that can reduce manufacturing costs and improve reliability, optical devices including display devices, electronic devices including display devices, and methods for manufacturing display devices.

[0008] An aspect of the embodiments of this disclosure relates to a display device in which the encapsulation layer is patterned together with the pad area in a process that exposes the pad area, thereby reducing the number of masks and thus reducing manufacturing costs.

[0009] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the embodiments of this disclosure presented.

[0010] According to one or more embodiments of the disclosure, a display device includes a substrate, a first electrode on the substrate, a pixel definition film on the first electrode, an emission stack on the first electrode and the pixel definition film, a second electrode on the emission stack, and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a plurality of sub-encapsulation layers, and at least two ends of the plurality of sub-encapsulation layers are arranged (e.g., aligned) along one direction.

[0011] According to one or more embodiments of the disclosure, an optical device includes a display device, and a light path changing member on the display device, wherein the display device includes a substrate, a first electrode on the substrate, a pixel definition film on the first electrode, an emission stack on the first electrode and the pixel definition film, a second electrode on the emission stack, and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a plurality of sub-encapsulation layers, and at least two ends of the plurality of sub-encapsulation layers are arranged (e.g., aligned) along one direction.

[0012] According to one or more embodiments of the disclosure, an electronic device includes a display device, wherein the display device includes a substrate, a first electrode on the substrate, a pixel definition film on the first electrode, an emission stack on the first electrode and the pixel definition film, a second electrode on the emission stack, and an encapsulation layer on the second electrode, wherein the encapsulation layer includes a plurality of sub-encapsulation layers, and at least two ends of the plurality of sub-encapsulation layers are arranged (e.g., aligned) along one direction.

[0013] Further, according to one or more embodiments of the disclosure, a method for manufacturing a display device includes forming a first electrode on a substrate, forming a pixel definition film on the first electrode, forming an emission stack on the first electrode and the pixel definition film, forming a second electrode on the emission stack, forming a first sub-encapsulation layer across an entire surface of the second electrode, forming a second sub-encapsulation layer on the first sub-encapsulation layer using a first mask, forming a third sub-encapsulation layer on the first sub-encapsulation layer and the second sub-encapsulation layer, forming a fourth sub-encapsulation layer across an entire surface of the third sub-encapsulation layer, and patterning the first sub-encapsulation layer, the third sub-encapsulation layer, and the fourth sub-encapsulation layer while exposing a metal layer of a pad of the substrate using a second mask.

[0014] The display device, optical device, electronic device, and method for manufacturing a display device according to one or more embodiments of the disclosure can reduce manufacturing costs of the display device and can improve reliability of the display device. The reduction in manufacturing costs can be achieved by innovative design and manufacturing processes that minimize or reduce the number of masks required during encapsulation layer patterning. By integrating encapsulation layer patterning with pad region exposure processes, the number of photolithography steps (e.g., actions or tasks) is reduced, resulting in lower material and labor costs. Furthermore, the use of fewer masks reduces alignment errors and defects, thereby improving overall yield and quality of the display device. By using advanced materials and precise manufacturing techniques, the reliability of the display device is further improved, thereby providing reliable protection against environmental factors.

[0015] Effects / advantages of the present disclosure are not limited to the above-mentioned effects / advantages, and other effects / advantages not described herein will become apparent to those skilled in the art from the following descriptions. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure. In the drawings:

[0017] Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure;

[0018] Figure 2 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure;

[0019] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure;

[0020] Figure 4 is a layout diagram illustrating a display panel according to one or more embodiments of the present disclosure;

[0021] Figure 5 and Figure 6 each is a layout diagram illustrating a portion of a display area of Figure 4 according to one or more embodiments of the present disclosure;

[0022] Figure 7 is a cross-sectional view of a display panel taken along line I1-I1’ of Figure 5 according to one or more embodiments of the present disclosure;

[0023] Figure 8 is a layout diagram illustrating a portion of a display area of Figure 7is a magnified cross-sectional view of region Al of

[0024] Figure 9 is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure; Figure 4 is a layout view of a first pad of a first pad portion of

[0025] Figure 10 is a cross-sectional view taken along line B-B’ of Figure 9

[0026] Figure 11 is a cross-sectional view of a portion of a display panel taken along line E-E’ of Figure 4

[0027] Figure 12 is a cross-sectional view of a portion of a display panel taken along line F-F’ of Figure 4

[0028] Figure 13 is a magnified cross-sectional view of region A2 of Figure 11

[0029] Figures 14 to 28 is a perspective view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure; Figure 14 , Figure 16 , Figure 18 , Figure 19 , Figure 21 , Figure 22 , Figure 23 , Figure 25 and Figure 27 are cross-sectional views taken along line II-II’ of Figure 5 during a manufacturing process according to one or more embodiments of the present disclosure, and Figure 15 , Figure 17 , Figure 20 , Figure 24 , Figure 26 and Figure 28 are cross-sectional views taken along line B-B’ of Figure 9 during a manufacturing process according to one or more embodiments of the present disclosure;

[0030] Figure 29 is a cross-sectional view of a display panel taken along line E-E’ of Figure 4

[0031] Figure 30 is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure;​​​​​

[0032] Figure 31 is an exploded perspective view of a head-mounted display according to one or more embodiments of the present disclosure; Figure 30

[0033] Figure 32 is a perspective view of a head-mounted display according to one or more embodiments of the present disclosure;

[0034] Figure 33 is a block diagram of an electronic device according to one or more embodiments of the present disclosure; and

[0035] Figure 34 , Figure 35 and Figure 36 are schematic perspective views of an electronic device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The present disclosure can be modified in various alternative forms, and as such, specific embodiments will be shown in the drawings and will be described in greater detail in the written description. It is to be understood, however, that there is no intent to limit the disclosure to the particular form disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

[0037] Hereinafter, example embodiments will be described in greater detail with reference to the accompanying drawings. However, the present disclosure can be embodied in various different forms, and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements and techniques that are completely understood by those of ordinary skill in the art can not be described.

[0038] It will be understood that when an element such as a region, layer, film, area or part is referred to as being "on", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element, or one or more intervening elements can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, or "adjacent" to another element or layer, there are no intervening elements or layers present. It will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements can also be present.

[0039] ​Unless otherwise indicated, like reference numerals indicate like elements throughout the drawings and written description, and thus a description of what one part means can be relevant to another part. In the drawings, the relative sizes of elements, layers, and regions, including thicknesses, can be exaggerated for clarity.

[0040] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0041] For ease of explanation, spatial relative terms such as“on,”“under,”“lower,”“below,”“above,” and“upper” can be used herein to describe the relationship of one element or feature to another element or feature depicted in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if a device in the drawings is turned over, elements described as“below” or“beneath” other elements or features would then be oriented“above” the other elements or features. Thus, the example terms“below” and“beneath” can encompass both orientations in use or operation. The device can be otherwise oriented (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and“including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, the terms“comprises,”“comprising,”“includes,”“including” and the like can include a series of one or more steps, operations, elements, and / or components, and are not limited to consisting or consisting essentially of the features, integers, steps, operations, elements, and / or components that are listed.

[0043] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. Unless otherwise apparent from this disclosure, expressions such as “at least one of,” “multiple,” “one of,” and other prepositional phrases, when preceding or following a list of elements, should be understood to include separate lists when written as a combined list, and vice versa. For example, expressions “at least one of a, b, and c,” “choose one of the group consisting of a, b, and c,” “selected from at least one of a, b, and c,” “at least one of a, b, and c,” “one of a, b, and c,” “at least one of a to c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] As used herein, the terms “use” and “being used” may be considered synonymous with the terms “exploitation” and “being exploited”, respectively.

[0045] Features of the various embodiments of this disclosure can be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Various embodiments can be implemented individually or in combination.

[0046] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0047] Figure 1 This is an exploded perspective view showing a display device 10 according to one or more embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device 10 according to one or more embodiments of the present disclosure.

[0048] refer to Figure 1 and Figure 2 The display device 10 according to one or more embodiments is an apparatus for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. In one or more embodiments, the display device 10 according to one or more embodiments can be applied to smartwatches, watch phones, and / or head-mounted displays (HMDs) for implementing virtual reality and / or augmented reality.

[0049] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (or a timing controller) 400, and a power supply circuit (or a power supply unit) 500.

[0050] The display panel 100 can have a planar shape similar to a quadrilateral shape. For example, the display panel 100 can have a planar shape similar to a quadrilateral shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1 (e.g., having two short sides in the first direction DR1 and two long sides in the second direction DR2 to provide four sides of a quadrilateral). In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be a right angle, or can be rounded with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to the quadrilateral shape, and can be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 10 can coincide with the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0051] The display panel 100 can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. As shown in FIG. 1A, the display panel 100 can be divided into a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed. Figure 2 The display panel 100 can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. As shown in FIG. 1A, the display panel 100 can be divided into a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed.

[0052] The plurality of pixels PX can be arranged in the display area DAA. The plurality of pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can be arranged while extending in the first direction DR1 and the second direction DR2. The plurality of data lines DL can be arranged while extending in the second direction DR2 and the first direction DR1.

[0053] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0054] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in FIG. 2A, and the plurality of pixel transistors can be formed by a semiconductor process and can be arranged in a semiconductor substrate SSUB (e.g., see FIG. 2B). Figure 3 The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in FIG. 2A, and the plurality of pixel transistors can be formed by a semiconductor process and can be arranged in a semiconductor substrate SSUB (e.g., see FIG. 2B). Figure 7The plurality of data transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS), for example, but the present disclosure is not limited thereto.

[0055] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. For example, each of the plurality of sub-pixels SP1, SP2, and SP3 in the display area DAA can be connected to a corresponding write scan line GWL, control scan line GCL, bias scan line GBL, first emission control line EL1, second emission control line EL2, and data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and can emit light from the light emitting element according to the data voltage.

[0056] The scan driver 610, the emission driver 620, and the data driver 700 can be arranged in the non-display area NDA.

[0057] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed on a semiconductor substrate SSUB (see FIG. 1, for example) by a semiconductor process. Figure 7 The plurality of scan transistors and the plurality of light emitting transistors can be formed of CMOS, for example, but the present disclosure is not limited thereto.

[0058] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS of the timing control circuit 400, and can sequentially output them to the write scan lines GWL. The control scan signal output unit 612 can generate control scan signals according to the scan timing control signal SCS, and can sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 can generate bias scan signals according to the scan timing control signal SCS, and can sequentially output them to the bias scan lines GBL.

[0059] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate first emission control signals according to the emission timing control signal ECS, and can sequentially output them to the first emission control lines EL1. The second emission control driver 622 can generate second emission control signals according to the emission timing control signal ECS, and can sequentially output them to the second emission control lines EL2.

[0060] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed on a semiconductor substrate SSUB (see, for example, FIG. 1) by a semiconductor process. Figure 7 For example, the plurality of data transistors can be formed of CMOS, but the present disclosure is not limited thereto.

[0061] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data lines DL. In such an embodiment, the sub-pixels SP1, SP2, and SP3 can be selected by the write scan signals of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0062] The heat dissipation layer 200 may overlap the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100 (e.g., on the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer of graphite or a metal with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al).

[0063] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 using conductive adhesive members such as anisotropic conductive film (see, for example, see...). Figure 4 Multiple first pads PD1 (e.g., see...) Figure 4 Circuit board 300 can be a flexible film or a flexible printed circuit board with flexible materials. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In such an embodiment, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 may be connected to the first pad portion of the display panel 100, PDA1, using conductive adhesive members (see, for example, [link to relevant documentation]). Figure 4 Multiple first pads PD1 (e.g., see...) Figure 4 One end of the circuit board 300 can be the opposite end to the other end of the circuit board 300.

[0064] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source (e.g., outside the display panel 100 and / or display device 10). In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0065] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and can supply them to the display panel 100. This will be discussed later. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0066] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC), and can be attached to one surface of the circuit board 300. In such an embodiment, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Further, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0067] In one or more embodiments, each of the timing control circuit 400 and the power supply circuit 500 can be arranged in the non-display area NDA of the display panel 100, similar to the scan driver 610, the emission driver 620, and the data driver 700. In such an embodiment, the timing control circuit 400 can include a plurality of timing transistors, and the power supply circuit 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed on a semiconductor substrate SSUB (see, for example, Figure 7 ) by a semiconductor process. For example, the plurality of timing transistors and the plurality of power transistors can be formed by CMOS, but the present disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be arranged between the data driver 700 and the first pad portion PDA1 (see, for example, Figure 4 ).

[0068] Figure 3 is an equivalent circuit diagram of a first sub-pixel SP1 according to one or more embodiments of the present disclosure. Although one first sub-pixel SP1 is discussed with respect to Figure 3 , the configuration of the circuit of the remaining first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 in the entire display area DAA can be similar or identical to the configuration of the circuit of the first sub-pixel SP1 discussed with respect to Figure 3 .

[0069] Referring to Figure 3The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Further, the first sub-pixel SP1 can be connected to the first drive voltage line VSL to which the first drive voltage VSS corresponding to a low potential voltage is applied, the second drive voltage line VDL to which the second drive voltage VDD corresponding to a high potential voltage is applied, and the third drive voltage line VIL to which the third drive voltage VINT corresponding to an initialization voltage is applied. For example, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In such an embodiment, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0070] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0071] The light emitting element LE emits light in response to a drive current flowing through a channel of the first transistor T1. An emission amount of the light emitting element LE can be proportional to the drive current. The light emitting element LE can be arranged between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0072] The first transistor T1 can be a drive transistor that controls a source-drain current (hereinafter, referred to as “drive current”) flowing between a source electrode and a drain electrode thereof according to a voltage applied to a gate electrode thereof. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0073] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the above-described one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to the above-described one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the above-described one electrode of the first capacitor CP1.

[0074] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, if the gate electrode and the drain electrode of the first transistor T1 are connected (for example, when the gate electrode and the drain electrode of the first transistor T1 are connected), the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0075] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, a driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0076] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, a third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0077] The sixth transistor T6 can be arranged between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0078] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0079] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0080] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the above-mentioned other electrode of the first capacitor CP1, and the above-mentioned one electrode of the second capacitor CP2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0081] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type (class) MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type (class) MOSFET. In one or more embodiments, some of the first transistor T1 to the sixth transistor T6 can be a P-type (class) MOSFET, and each of the remaining transistors can be an N-type (class) MOSFET.

[0082] Although the first sub-pixel SP1 is shown in Figure 3 to include six transistors T1 to T6 and two capacitors C1 and C2, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3the number shown in FIG. 1.

[0083] Further, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with Figure 3 Further, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with

[0084] Figure 4 is a layout diagram showing the display panel 100 according to one or more embodiments of the present disclosure.

[0085] Referring to Figure 4 , the display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0086] The scan driver 610 can be arranged at a first side of the display area DAA, and the emission driver 620 can be arranged at a second side of the display area DAA. For example, the scan driver 610 can be arranged at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be arranged at the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 can be arranged at a left side of the display area DAA, and the emission driver 620 can be arranged at a right side of the display area DAA. However, the present disclosure is not limited thereto, and each of the scan driver 610 and the emission driver 620 can be arranged at either one of the first side and the second side of the display area DAA.

[0087] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be arranged at a third side of the display area DAA. For example, the first pad portion PDA1 can be arranged at one side of the display area DAA in the second direction DR2. The first pad portion PDA1 can be arranged outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 can be arranged closer to an edge of the display panel 100 than the data driver 700.

[0088] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to check pads for checking whether the test display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe during a checking process, or can be connected to a circuit board for checking. The circuit board for checking can be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0089] The second pad portion PDA2 can be disposed at a fourth side of the display area DAA. For example, the second pad portion PDA2 can be disposed at another side of the display area DAA in the second direction DR2 with respect to the first pad portion PDA1. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2. For example, the second pad portion PDA2 can be disposed closer to an edge of the display panel 100 than the second distribution circuit 720.

[0090] The first distribution circuit 710 distributes data voltages applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of first pads PD1 can be reduced. Since each first pad PD1 can distribute two or more data voltages to two or more corresponding data lines DL, the number of first pads PD1 is reduced with respect to the number of data lines DL. The first distribution circuit 710 can be disposed at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed at a lower side of the display area DAA.

[0091] The second distribution circuit 720 distributes signals applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at another side of the display area DAA in the second direction DR2 with respect to the first distribution circuit 710. For example, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0092] Figure 5 and Figure 6 FIGS. 1 to 8 illustrate a display panel according to one or more embodiments of the present disclosure. Figure 4 FIG. 8 illustrates a layout diagram of a portion of a display area DAA of the display panel of FIG. 1.

[0093] refer to Figure 5 and Figure 6 Each of the pixels PX may include a first emission region EA1, which is the emission region of the first sub-pixel SP1; a second emission region EA2, which is the emission region of the second sub-pixel SP2; and a third emission region EA3, which is the emission region of the third sub-pixel SP3.

[0094] In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical (e.g., non-geometric) shape.

[0095] For example, such as Figure 5 As shown, the maximum length of the third transmission region EA3 in the first direction DR1 can be less than each of the maximum lengths of the second transmission region EA2 and the first transmission region EA1 in the first direction DR1. The maximum lengths of the second transmission region EA2 and the first transmission region EA1 in the first direction DR1 can be substantially the same.

[0096] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than each of the maximum lengths of the second transmission region EA2 and the first transmission region EA1 in the second direction DR2. The maximum length of the second transmission region EA2 in the second direction DR2 can be less than the maximum length of the first transmission region EA1 in the second direction DR2. In other words, the maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0097] For example, such as Figure 6 As shown in the diagram, in the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape formed by six straight lines, but this disclosure is not limited thereto. In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape other than a hexagonal shape.

[0098] like Figure 5As shown in FIG. 1, in each of the plurality of pixels PX, the third emission region EA3 and the second emission region EA2 can be adjacent to each other in the first direction DR1. Further, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. In one or more embodiments, the second emission region EA2 and the first emission region EA1 can be adjacent to each other in the second direction DR2. The area of the first emission region EA1, the area of the second emission region EA2, and the area of the third emission region EA3 can be different.

[0099] In one or more embodiments, as Figure 6 shown in FIG. 1, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 can be adjacent to each other in a first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 can be adjacent to each other in a second diagonal direction DD2. The first diagonal direction DD1 can be a direction between the first direction DR1 and the second direction DR2 and can refer to a direction inclined by 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal (e.g., perpendicular) to the first diagonal direction DD1.

[0100] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light of a red color band, the second color light can be light of a green color band, and the third color light can be light of a blue color band. For example, the blue color band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green color band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red color band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0101] As Figure 5 and Figure 6 shown in FIG. 1, each of the plurality of pixels PX can include three emission regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, each of the plurality of pixels PX can include four emission regions.

[0102] In one or more embodiments, the layout of the emission regions of the plurality of pixels PX is not limited to the layout shown in Figure 5 and Figure 6 FIG. 1. For example, the emission regions of the plurality of pixels PX can be in a stripe structure in which the emission regions are alternately arranged in the first direction DR1, structure (e.g., an RGBG matrix, an RGBG structure, or an RGBG matrix structure) or a diamond shape (DIAMOND (e.g., a display (e.g., an OLED display) including red, green, and blue (RGB) emission regions arranged in a diamond shape) to arrange. and DIAMOND is a registered trademark of Samsung Display Co., Ltd.

[0103] Figure 7 is a cross-sectional view of a display panel 100 taken along a line I1-I1’ of Figure 5 according to one or more embodiments of the present disclosure. Figure 8 is an enlarged cross-sectional view of a region A1 of Figure 7 according to one or more embodiments of the present disclosure.

[0104] Referring to Figure 7 and Figure 8 , the display panel 100 can include a semiconductor backplane SBP, an emission element backplane EBP, an emission element layer EML, a thin film encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0105] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first to sixth transistors T1 to T6 described with reference to Figure 3

[0106] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type (kind) of impurity. A plurality of well regions WA can be arranged at a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type (kind) of impurity. The second type (kind) of impurity can be different from the aforementioned first type (kind) of impurity. For example, if the first type (kind) of impurity is a P-type (kind) of impurity (e.g., when the first type (kind) of impurity is a P-type (kind) of impurity), the second type (kind) of impurity can be an N-type (kind) of impurity. Alternatively, in one or more embodiments, if the first type (kind) of impurity is an N-type (kind) of impurity (e.g., when the first type (kind) of impurity is an N-type (kind) of impurity), the second type (kind) of impurity can be a P-type (kind) of impurity.

[0107] ​Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH arranged between the source region SA and the drain region DA.

[0108] A lower insulating layer BINS can be arranged between the gate electrode GE and the well region WA. A side insulating layer SINS can be arranged on a side surface of the gate electrode GE (e.g., the side insulating layer SINS can be arranged on a side surface of the gate electrode GE arranged along the first direction DR1 and / or the second direction DR2 when viewed in a cross-sectional view). The side insulating layer SINS can be arranged on the lower insulating layer BINS.

[0109] Each of the source region SA and the drain region DA can be a region doped with a first type (kind) of impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be arranged on one side of the gate electrode GE, and the drain region DA can be arranged on the other side of the gate electrode GE.

[0110] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 arranged between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 arranged between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than an impurity concentration of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than an impurity concentration of the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, a distance between the source region SA and the drain region DA can increase. Thus, a length of the channel region CH of each of the pixel transistors PTR can increase, such that punch-through and hot carrier phenomena that can be caused by a short channel can be reduced or prevented.

[0111] A first semiconductor insulating layer SINS1 can be arranged on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x , for example, 0 < x ≤ 2), but the present disclosure is not limited thereto.

[0112] A second semiconductor insulating layer SINS2 can be arranged on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be formed of silicon oxide (SiO x , for example, 0 < x ≤ 2), but the present disclosure is not limited thereto.

[0113] The plurality of contact terminals CTE can be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole passing through the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer INS2. The plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof.

[0114] The third semiconductor insulating layer SINS3 can be disposed on the side surface of each of the plurality of contact terminals CTE and the second semiconductor insulating layer SINS2. The top surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 can be formed of a silicon oxide (SiO x ) type inorganic film, but the present disclosure is not limited thereto.

[0115] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate. In such an embodiment, the pixel transistors PTR can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that is not bent, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0116] The light emitting element backplane EBP includes a plurality of conductive layers ML1 to ML8 and a plurality of vias VA1 to VA9. In addition, the light emitting element backplane EBP can include a plurality of insulating layers INS1 to INS9 disposed on, under, and between the first conductive layer ML1 to the eighth conductive layer ML8.

[0117] The first conductive layer ML1 to the eighth conductive layer ML8 serve to connect the plurality of contact terminals CTE exposed from the semiconductor backplane SBP to thereby implement, for example, the circuit of the first sub-pixel SP1 shown in FIG. Figure 3 For example, the first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 with the first capacitor CP1 and the second capacitor CP2 is implemented through the first conductive layer ML1 to the eighth conductive layer ML8. In one or more embodiments, the connection between the drain region DA corresponding to the drain electrode of the fourth transistor T4, the source region SA corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light emitting element LE is also implemented through the first conductive layer ML1 to the eighth conductive layer ML8.

[0118] The first insulating layer INS1 can be disposed on the semiconductor base plate SBP. Each of the first vias VA1 can pass through the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor base plate SBP. The first conductive layer ML1 can be disposed on the first insulating layer INS1 and can be connected to the first vias VA1.

[0119] The second insulating layer INS2 can be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second vias VA2 can pass through the second insulating layer INS2 and can be connected to the exposed first conductive layer ML1. The second conductive layer ML2 can be disposed on the second insulating layer INS2 and can be connected to the second vias VA2.

[0120] The third insulating layer INS3 can be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third vias VA3 can pass through the third insulating layer INS3 and can be connected to the exposed second conductive layer ML2. The third conductive layer ML3 can be disposed on the third insulating layer INS3 and can be connected to the third vias VA3.

[0121] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can pass through the fourth insulating layer INS4 and can be connected to the exposed third conductive layer ML3. The fourth conductive layer ML4 can be disposed on the fourth insulating layer INS4 and can be connected to the fourth vias VA4.

[0122] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can pass through the fifth insulating layer INS5 and can be connected to the exposed fourth conductive layer ML4. The fifth conductive layer ML5 can be disposed on the fifth insulating layer INS5 and can be connected to the fifth vias VA5.

[0123] The sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can pass through the sixth insulating layer INS6 and can be connected to the exposed fifth conductive layer ML5. The sixth conductive layer ML6 can be disposed on the sixth insulating layer INS6 and can be connected to the sixth vias VA6.

[0124] The seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can pass through the seventh insulating layer INS7 and can be connected to the exposed sixth conductive layer ML6. The seventh conductive layer ML7 can be disposed on the seventh insulating layer INS7 and can be connected to the seventh vias VA7.

[0125] The eighth insulating layer INS8 can be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can pass through the eighth insulating layer INS8 and can be connected to the exposed seventh conductive layer ML7. The eighth conductive layer ML8 can be disposed on the eighth insulating layer INS8 and can be connected to the eighth vias VA8.

[0126] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more of them. The first insulating layer INS1 to the eighth insulating layer INS8 can be made of substantially the same material. The first insulating layer INS1 to the eighth insulating layer INS8 can be formed of a silicon oxide (SiO x ) class inorganic film, but the present disclosure is not limited thereto.

[0127] The thickness (in the third direction DR3) of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can each be greater than the thickness (in the third direction DR3) of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. For example, the thickness (in the third direction DR3) of the first conductive layer ML1 can be greater than the thickness (in the third direction DR3) of each of the first vias VA1. The thickness (in the third direction DR3) of the second conductive layer ML2 can be greater than the thickness (in the third direction DR3) of each of the second vias VA2. The thickness (in the third direction DR3) of the third conductive layer ML3 can be greater than the thickness (in the third direction DR3) of each of the third vias VA3. The thickness (in the third direction DR3) of the fourth conductive layer ML4 can be greater than the thickness (in the third direction DR3) of each of the fourth vias VA4. The thickness (in the third direction DR3) of the fifth conductive layer ML5 can be greater than the thickness (in the third direction DR3) of each of the fifth vias VA5. The thickness (in the third direction DR3) of the sixth conductive layer ML6 can be greater than the thickness (in the third direction DR3) of each of the sixth vias VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately (roughly) 0.5 to 2.0 times the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately (roughly) 0.5 to 2.0 times the thickness of the first conductive layer ML1. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately (roughly) 0.5 to 2.0 times the thickness of the first conductive layer ML1.

[0128] A thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than a thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. A thickness of the seventh conductive layer ML7 and a thickness of the eighth conductive layer ML8 can be greater than a thickness of each of the seventh via VA7 and the eighth via VA8, respectively. For example, the thickness of the seventh conductive layer ML7 can be greater than a thickness of each of the seventh vias VA7. The thickness of the eighth conductive layer ML8 can be greater than a thickness of each of the eighth vias VA8. A thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than a thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately (about) 100 nm to 300 nm, for example, approximately (about) 150 nm to 250 nm, for example, approximately (about) 200 nm. A thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately (about) 100 nm to 300 nm, for example, approximately (about) 150 nm to 250 nm, for example, approximately (about) 200 nm.

[0129] A ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be formed of a silicon oxide (SiO x ) inorganic film, but the present disclosure is not limited thereto.

[0130] Each of the ninth vias VA9 can pass through the ninth insulating layer INS9 and can be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. A thickness of the ninth via VA9 can be approximately (about) 100 nm to 300 nm, for example, approximately (about) 150 nm to 250 nm, for example, approximately (about) 200 nm.

[0131] A display element layer EML can be disposed on the light emitting element base plate EBP. The display element layer EML can include light emitting elements LE each including a reflective electrode layer RL, a tenth insulating layer INS10, a tenth via VA10, a first electrode AND, a light emitting stack IL, and a second electrode CAT, a pixel definition film PDL, and a plurality of trenches TRC.

[0132] The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL can include a step layer STPL and / or at least one reflective electrode. For example, Figure 7It is shown that the at least one reflective electrode includes first to fourth reflective electrodes RL1, RL2, RL3, and RL4, but the disclosure is not limited thereto.

[0133] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating layer INS9 and can be connected to the ninth via hole VA9. The first reflective electrode RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0134] Each of the second reflective electrodes RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the second reflective electrode RL2 can include aluminum (Al).

[0135] In the third sub-pixel SP3, the step layer STPL can be disposed on the second reflective electrode RL2. The step layer STPL can not be disposed on the second reflective electrode RL2 in the second sub-pixel SP2 and / or the first sub-pixel SP1.

[0136] A thickness of the step layer STPL can be set in consideration of a wavelength of light of the third color and a distance from the light emitting stack IL of the third sub-pixel SP3 to the fourth reflective electrode RL4 to increase reflection of light of the third color emitted from the light emitting stack IL.

[0137] The step layer STPL can be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) inorganic film, but the disclosure is not limited thereto.

[0138] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the second sub-pixel SP2, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the step layer STPL. The third reflective electrode RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the third reflective electrode RL3 can include titanium nitride (TiN).

[0139] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 can not be provided.

[0140] The fourth reflective electrode RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be a layer that reflects light from the light emitting stack IL. The fourth reflective electrode RL4 can include a metal having a high reflectance to improve light reflection. In one or more embodiments, because the fourth reflective electrode RL4 is an electrode that substantially reflects light from the light emitting stack IL, a thickness of the fourth reflective electrode RL4 can be greater than a thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3. The fourth reflective electrode RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the fourth reflective electrode RL4 can include aluminum (Al) or titanium (Ti).

[0141] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9 and the fourth reflective electrode RL4. The tenth insulating layer INS10 can be an optical auxiliary layer through which light among light emitted from the light emitting stack IL, which is reflected by the reflective electrode layer RL, passes. The tenth insulating layer INS10 can be formed of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0142] Each of the tenth vias VA10 can pass through the tenth insulating layer INS10 and can be connected to the exposed fourth reflective electrode RL4. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof.

[0143] A thickness of the tenth via VA10 can vary in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 in order to adjust a resonance distance of light emitted from the light emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the thickness of the tenth via VA10 in the third sub-pixel SP3 can be less than the thickness of the tenth via VA10 in each of the first sub-pixel SP1 and the second sub-pixel SP2. Also, the thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the first sub-pixel SP1. For example, a distance between the light emitting stack IL and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0144] Accordingly, in order to adjust the distance between the light emitting stack IL and the reflective electrode layer RL according to the main peak wavelength of light emitted from the first sub-pixel SP1, the presence or absence of the step layer STPL in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and the thickness of the step layer STPL can be set. For example, the step layer STPL can be provided in the first sub-pixel SP1 to reduce the distance between the fourth reflective electrode RL4 and the light emitting stack IL in the first sub-pixel SP1 with respect to the distance between the fourth reflective electrode RL4 and the light emitting stack IL in the second sub-pixel SP2 and the third sub-pixel SP3. The reduced distance can be related to the resonance distance of the first color light emitted by the light emitting stack IL in the first sub-pixel SP1, and thus can cause an increase in light reflection of the fourth reflective electrode RL4. Similarly, the distances between the fourth reflective electrodes RL4 and the light emitting stack IL of the second sub-pixel SP2 and the third sub-pixel SP3 can also be related to the resonance distances of the second color light and the third color light, respectively, and thus can also cause an increase in light reflection of those respective fourth reflective electrodes RL4.

[0145] The first electrode AND of each of the light emitting elements LE can be disposed on the tenth insulating layer INS10 and can be connected to the tenth via hole VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the first electrode AND of each of the light emitting elements LE can include titanium nitride (TiN).

[0146] The pixel definition film PDL can be disposed on a portion of the first electrode AND of each of the light emitting elements LE and the tenth insulating layer INS10. The pixel definition film PDL can cover the edge of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can be used to separate the first, second, and third emission areas EA1, EA2, and EA3.

[0147] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked to emit light in the first sub-pixel SP1. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked to emit light in the second sub-pixel SP2. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked to emit light in the third sub-pixel SP3.

[0148] The pixel definition film PDL can include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 can be disposed on an edge of the first electrode AND of each of the light emitting elements LE and the tenth insulating layer INS10, the second pixel definition film PDL2 can be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 can be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can each have a thickness of about .

[0149] When the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, the height of the one pixel definition film increases, so that the first sub-package layer TFE1 can be disconnected due to step coverage. The step coverage refers to a ratio of a degree of coating of a thin film on an inclined portion to a degree of coating of the thin film on a flat portion. The lower the step coverage, the more likely the thin film is to be disconnected at the inclined portion.

[0150] Accordingly, to reduce or prevent the possibility that the first sub-package layer TFE1 is disconnected due to step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure including a step portion. For example, the width of the first pixel definition film PDL1 can be greater than the width of the second pixel definition film PDL2 and the width of the third pixel definition film PDL3, and the width of the second pixel definition film PDL2 can be greater than the width of the third pixel definition film PDL3. The width of the first pixel definition film PDL1 refers to a horizontal length of the first pixel definition film PDL1 defined in the first direction DR1 and the second direction DR2.

[0151] Each of the plurality of trenches TRC can pass through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Further, the tenth insulating layer INS10 can be partially recessed at each of the plurality of trenches TRC.

[0152] The at least one trench TRC can be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two trenches TRC are shown as being disposed between adjacent sub-pixels SP1, SP2, and SP3 (e.g., between the adjacent first sub-pixel SP1 and the second sub-pixel SP2 and between the adjacent second sub-pixel SP2 and the third sub-pixel SP3), but the disclosure is not limited thereto.

[0153] The light emitting stack IL can include a plurality of intermediate layers. Figure 7 A three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 is shown as being included in the light emitting stack IL, but the disclosure is not limited thereto. For example, the light emitting stack IL can have a two-series structure including two stack layers.

[0154] In the three-series structure, the light emitting stack IL can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different colors of light. For example, the light emitting stack IL can include a first stack layer IL1 that emits a first color of light, a second stack layer IL2 that emits a third color of light, and a third stack layer IL3 that emits a second color of light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0155] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits a first color of light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits a third color of light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer that emits a second color of light, and a third electron transport layer are sequentially stacked.

[0156] A first charge generation layer for supplying holes to the second stack layer IL2 and supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type (class) charge generation layer that supplies electrons to the first stack layer IL1 and a P-type (class) charge generation layer that supplies holes to the second stack layer IL2. The N-type (class) charge generation layer can include a dopant of a metal material.

[0157] A second charge generation layer for supplying holes to the third stack layer IL3 and for supplying electrons to the second stack layer IL2 can be arranged between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type (class) charge generation layer for supplying electrons to the second stack layer IL2 and a P-type (class) charge generation layer for supplying holes to the third stack layer IL3.

[0158] The first stack layer IL1 can be arranged on the first electrode AND and the pixel definition film PDL. A remaining stack layer RIL made of the same material as that of the first stack layer IL1 can be arranged on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be broken between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The second stack layer IL2 can be arranged on the first stack layer IL1. The second stack layer IL2 can be broken between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. A void ESS or empty space can be arranged between the remaining stack layer RIL and the second stack layer IL2 in each of the trenches TRC. The third stack layer IL3 can be arranged on the second stack layer IL2. The third stack layer IL3 can not be broken by the trenches TRC and can be arranged to cover the second stack layer IL2 in each of the trenches TRC. For example, in a triple series structure, each of the plurality of trenches TRC can be a structure for breaking the first stack layer IL1 and the second stack layer IL2 of the display element layer EML, the first charge generation layer, and the second charge generation layer between the adjacent sub-pixels SP1, SP2, and SP3.

[0159] In one or more embodiments, in a double series structure, each of the plurality of trenches TRC can be a structure for breaking the lower stack layer and the charge generation layer arranged between the lower stack layer and the upper stack layer.

[0160] In order to stably break the first stack layer IL1 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, a height of each of the plurality of trenches TRC can be greater than a height of the pixel definition film PDL. The height of each of the plurality of trenches TRC refers to a length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel definition film PDL refers to a length of the pixel definition film PDL in the third direction DR3. In order to break the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3, another structure can exist instead of the trenches TRC. For example, instead of the trenches TRC, an inverted taper-shaped partition wall can be arranged on the pixel definition film PDL.

[0161] In addition, Figure 7 and Figure 8It is shown that the first to third stack layers IL1, IL2, and IL3 are all disposed in the first, second, and third emission areas EA1, EA2, and EA3, but the disclosure is not limited thereto. For example, the first stack layer IL1 can be disposed in the first emission area EA1, and can not be provided in the second and third emission areas EA2 and EA3. Also, the second stack layer IL2 can be disposed in the second emission area EA2, and can not be provided in the first and third emission areas EA1 and EA3. Also, the third stack layer IL3 can be disposed in the third emission area EA3, and can not be provided in the first and second emission areas EA1 and EA2. In such an embodiment, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can not be provided.

[0162] The second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be formed of a transparent conductive material (TCM) such as ITO or IZO, which can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, light emission efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to a microcavity effect.

[0163] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film (e.g., sub-encapsulation layers TFE1, TFE2, TFE3, and / or TFE4) for reducing or preventing penetration of oxygen or moisture into the display element layer EML. For example, the encapsulation layer TFE can include a first sub-encapsulation layer TFE1, a second sub-encapsulation layer TFE2, a third sub-encapsulation layer TFE3, and a fourth sub-encapsulation layer TFE4, which are sequentially stacked along a thickness direction (e.g., the third direction DR3) of the encapsulation layer TFE. Here, the first, third, and fourth sub-encapsulation layers TFE1, TFE3, and TFE4 can each include an inorganic material, and the second sub-encapsulation layer TFE2 can include an organic material.

[0164] The first sub-encapsulation layer TFE1 can be disposed on the second electrode CAT. The first sub-encapsulation layer TFE1 can be formed of an inorganic material selected from silicon nitride (Si x N y , for example, 0 < x ≤ 3 and 0 < y ≤ 4), silicon oxynitride (SiO x N y , for example, 0 < x ≤ 2 and 0 < y ≤ 2), and silicon oxide (SiO xa single layer of an inorganic film of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x ) and silicon oxide (SiO x ) and silicon oxide (SiO x ) alternately stacked. The first sub-encapsulation layer TFE1 can be formed by a chemical vapor deposition (CVD) process. The thickness of the first sub-encapsulation layer TFE1 can be less than or equal to 1 µm.

[0165] The second sub-encapsulation layer TFE2 can be disposed on the first sub-encapsulation layer TFE1. For example, the second sub-encapsulation layer TFE2 can be disposed between the first sub-encapsulation layer TFE1 and the third sub-encapsulation layer TFE3. The second sub-encapsulation layer TFE2 can be in contact (e.g., direct contact) with each of the first sub-encapsulation layer TFE1 and the third sub-encapsulation layer TFE3. The second sub-encapsulation layer TFE2 can be an organic film of one or more materials selected from the group consisting of acryl resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0166] The third sub-encapsulation layer TFE3 can be disposed on the second sub-encapsulation layer TFE2. For example, the third sub-encapsulation layer TFE3 can be disposed between the second sub-encapsulation layer TFE2 and the fourth sub-encapsulation layer TFE4. The third sub-encapsulation layer TFE3 can be in contact (e.g., direct contact) with each of the second sub-encapsulation layer TFE2 and the fourth sub-encapsulation layer TFE4. The third sub-encapsulation layer TFE3 can be formed as a single layer of an inorganic film of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x N y a plurality of layers of inorganic films of a material selected from the group consisting of silicon nitride (Si x ) and silicon oxide (SiO x ) and silicon oxide (SiO x ) alternately stacked. The third sub-encapsulation layer TFE3 can be formed by a chemical vapor deposition (CVD) process.

[0167] The fourth sub-packaging layer TFE4 can be disposed on the third sub-packaging layer TFE3. For example, the fourth sub-packaging layer TFE4 can be disposed between the third sub-packaging layer TFE3 and the organic layer APL. The fourth sub-packaging layer TFE4 can be in contact (e.g., direct contact) with each of the third sub-packaging layer TFE3 and the organic layer APL. Among the sub-packaging layers TFE1 to TFE4 of the packaging layer TFE, the fourth sub-packaging layer TFE4 can be disposed at the uppermost side. The fourth sub-packaging layer TFE4 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ; for example, Al2O3), but the present disclosure is not limited thereto. The fourth sub-packaging layer TFE4 can be formed by an atomic layer deposition (ALD) process.

[0168] The organic layer APL can be a layer for increasing interfacial adhesion between the packaging layer TFE and the optical layer OPL. The organic layer APL can be an organic film selected from one or more materials such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0169] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a fill layer FIL. The plurality of color filters CF1, CF2, and CF3 can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be disposed on the organic layer APL.

[0170] The first color filter CF1 can overlap the first emission area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color (i.e., light of a red wavelength band). Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1.

[0171] The second color filter CF2 can overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (i.e., light of a green wavelength band). Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2.

[0172] The third color filter CF3 can overlap the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color (i.e., light of a blue wavelength band). Accordingly, the third color filter CF3 can transmit light of the third color among light emitted from the third emission area EA3.

[0173] A plurality of lenses LNS can be respectively arranged on the first, second, and third color filters CF1, CF2, and CF3. Each of the plurality of lenses LNS can be a structure for increasing a proportion of light that is directed to the front face of the display device 10. Although each of the lenses LNS is illustrated as having a cross-sectional shape that is convex upward, the present disclosure is not limited thereto.

[0174] A filling layer FIL can be arranged on the plurality of lenses LNS. The filling layer FIL can have a set or predetermined refractive index such that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. Further, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic film selected from one or more materials such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0175] A cover layer CVL can be arranged on the filling layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filling layer FIL. In such an embodiment, the filling layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly coated onto the filling layer FIL.

[0176] A polarizing plate POL can be arranged on one surface of the cover layer CVL. The polarizing plate POL can be a structure for reducing or preventing visibility reduction caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (a quarter wave plate), but the present disclosure is not limited thereto. However, for example, if visibility reduction caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3 (e.g., when visibility reduction caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3), then the polarizing plate POL can not be provided.

[0177] Figure 9 is a layout view of a first pad PD1 of a first pad portion PDA1 of Figure 4 is a layout view of a first pad PD1 of a first pad portion PDA1 of Figure 10 is a cross-sectional view taken along a line B-B’ of Figure 9 is a cross-sectional view taken along a line B-B’ of

[0178] Referring to Figure 9 and Figure 10Each of the first pads PD1 includes a first sub-pad BPD and a second sub-pad IPD in which the pad metal layer PML is separated by the tenth insulating layer INS10. Both the first sub-pad BPD and the second sub-pad IPD can be electrically connected to a pad or a bump of the circuit board 300 through a conductive adhesive member. In one or more embodiments, the second sub-pad IPD can be a pad connected to a circuit board for inspection or connected to a clamp or a probe during an inspection process.

[0179] An area of the first sub-pad BPD can be greater than an area of the second sub-pad IPD. A length of the first sub-pad BPD in the first direction DR1 can be substantially the same as a length of the second sub-pad IPD in the first direction DR1. A length of the first sub-pad BPD in the second direction DR2 can be greater than a length of the second sub-pad IPD in the second direction DR2.

[0180] The pad metal layer PML can include a first sub-pad metal layer SPML1 and a second sub-pad metal layer SPML2. The first sub-pad metal layer SPML1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. The second sub-pad metal layer SPML2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and an alloy including any one or more thereof. For example, the first sub-pad metal layer SPML1 can be made of aluminum (Al) and can have a thickness of approximately 1 µm. In one or more embodiments, the second sub-pad metal layer SPML2 can be made of titanium nitride (TiN) and can have a thickness of approximately 1 µm. A thickness of the pad metal layer PML can be greater than a thickness of the reflective electrode layer RL.

[0181] A portion of a top surface of the second sub-pad metal layer SPML2 corresponding to the first sub-pad BPD can be exposed without being covered by the tenth insulating layer INS10. A portion of the top surface of the second sub-pad metal layer SPML2 corresponding to the second sub-pad IPD can be exposed without being covered by the tenth insulating layer INS10. The first sub-pad metal layer SPML1 can be connected to one or more pad vias PVA9 passing through the ninth insulating layer INS9 to be connected to the eighth conductive layer ML8.

[0182] As Figure 9 and Figure 10 ​As the pad metal layer PML of the first sub-pad BPD and the pad metal layer PML of the second sub-pad IPD are integrally formed, if the pad metal layer PML of the second sub-pad IPD is damaged or broken during the inspection process (for example, when the pad metal layer PML of the second sub-pad IPD is damaged or broken during the inspection process), the pad metal layer PML of the first sub-pad BPD can also be damaged or broken. Accordingly, it is desirable and / or necessary to separate or distinguish the pad metal layer PML of the second sub-pad IPD used in the inspection process and the pad metal layer PML of the first sub-pad BPD.

[0183] Figure 11 is a cross-sectional view of a portion of the display panel 100 taken along a line E-E’ of Figure 4 is a cross-sectional view of a portion of the display panel 100 taken along a line F-F’ of Figure 12 is a cross-sectional view of a portion of the display panel 100 taken along a line E-E’ of Figure 4 is a cross-sectional view of a portion of the display panel 100 taken along a line F-F’ of

[0184] Figure 11 and Figure 12 shows the first distribution circuit 710, the power connection part PCA, the dam part DMA, the data driver 700, the first pad part PDA1, the electrostatic protection part ESA, the anti-infiltration part MPA, and the anti-cracking part CPA arranged at one side of the display area DAA.

[0185] At one side of the display area DAA, the first distribution circuit 710, the power connection part PCA, the dam part DMA, the data driver 700, the first pad part PDA1, the electrostatic protection part ESA, the anti-infiltration part MPA, and the anti-cracking part CPA can be sequentially arranged in the second direction DR2. However, the present disclosure is not limited thereto, and the power connection part PCA can overlap the first distribution circuit 710 or the data driver 700 in the third direction DR3 and the dam part DMA can overlap the first distribution circuit 710 or the data driver 700 in the third direction DR3.

[0186] The first distribution circuit 710 can include a plurality of first distribution transistors DBTR1. As each of the plurality of first distribution transistors DBTR1 can be formed substantially the same as the pixel transistor PTR described in connection with Figure 7 a redundant description of the plurality of first distribution transistors DBTR1 can not be provided. In one or more embodiments, as the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the ninth via VA9 electrically connected to the plurality of first distribution transistors DBTR1 are also substantially the same as those described in connection with Figure 7 a redundant description of the plurality of first distribution transistors DBTR1 can not be provided. In one or more embodiments, as the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the ninth via VA9 electrically connected to the plurality of first distribution transistors DBTR1 are also substantially the same as those described in connection with

[0187] The power connection part PCA includes the first power connection area PCA A1 of the semiconductor substrate S SUB, the first power connection electrode PCE1, and the second power connection electrode PCE2.

[0188] The first driving voltage VSS can be applied to the first power connection area PCA A1 of the semiconductor substrate S SUB.

[0189] The first power connection electrode PCE1 can be disposed on the ninth insulating layer INS9. The first power connection electrode PCE1 can be connected to the first power connection area PCA A1 of the semiconductor substrate S SUB through the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via hole VA1 to the ninth via hole VA9.

[0190] The first power connection electrode PCE1 can include first to fourth sub power connection electrodes SPCE1 to SPCE4. The first to fourth sub power connection electrodes SPCE1 to SPCE4 of the first power connection electrode PCE1 can be substantially the same as the first to fourth reflective electrodes RL1 to RL4 of the reflective electrode layer RL. For example, the first sub power connection electrode SPCE1 can correspond to the first reflective electrode RL1, the second sub power connection electrode SPCE2 can correspond to the second reflective electrode RL2, the third sub power connection electrode SPCE3 can correspond to the third reflective electrode RL3, and the fourth sub power connection electrode SPCE4 can correspond to the fourth reflective electrode RL4.

[0191] The second power connection electrode PCE2 can be disposed on the tenth insulating layer INS10. The second power connection electrode PCE2 can be connected to the first power connection electrode PCE1 through the tenth via hole VA10. The second power connection electrode PCE2 can include a material substantially the same as a material of the first electrode AND of the light emitting element LE. The second power connection electrode PCE2 can be exposed through the pixel definition film PDL. The second electrode CAT of the light emitting element LE can be connected to the second power connection electrode PCE2 exposed and not covered by the pixel definition film PDL.

[0192] The dam part DMA includes a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 can be substantially the same as the trench TRC. Each of the first dam DM1 and the second dam DM2 can pass through the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. The tenth insulating layer INS10 can be partially recessed at each of the first dam DM1 and the second dam DM2.

[0193] In each of the first dam DM1 and the second dam DM2, a first sub-packaging layer TFE1 can be disposed on a bottom surface, a second sub-packaging layer TFE2 can be disposed on the first sub-packaging layer TFE1, and a third sub-packaging layer TFE3 can be disposed on the second sub-packaging layer TFE2. The second sub-packaging layer TFE2 can be disposed to fill a portion of each of the first dam DM1 and the second dam DM2. Alternatively, in one or more embodiments, the second sub-packaging layer TFE2 can not be disposed in each of the first dam DM1 and the second dam DM2. For example, the first sub-packaging layer TFE1 and the third sub-packaging layer TFE3 can be disposed in each of the first dam DM1 and the second dam DM2.

[0194] The first dam DM1 and the second dam DM2 can prevent or reduce a possibility of the second sub-packaging layer TFE2 flowing to the first pad portion PDA1 and covering the first pad PD1. When the second sub-packaging layer TFE2 covers the first pad PD1, the first pad PD1 can not be electrically connected to the circuit board 300.

[0195] The data driver 700 can include a plurality of data transistors DTR. Because each of the plurality of data transistors DTR can be formed substantially the same as the pixel transistor PTR described in connection with Figure 7 A redundant description of the plurality of data transistors DTR can not be provided because the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the eighth via VA8 electrically connected to the plurality of data transistors DTR are also substantially the same as those described in connection with Figure 7 A redundant description of them can not be provided because the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the eighth via VA8 electrically connected to the plurality of data transistors DTR are also substantially the same as those described in connection with

[0196] The electrostatic protection portion ESA includes a second power connection area PCAA2 of the semiconductor substrate SSUB.

[0197] The first driving voltage VSS can be applied to the second power connection area PCAA2 of the semiconductor substrate SSUB. The second power connection area PCAA2 can be connected to the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the eighth via VA8. Accordingly, the electrostatic protection portion ESA can discharge electrostatic applied from the outside to the first driving voltage VSS.

[0198] The impervious portion MPA includes an impervious electrode MPE and a third power connection area PCAA3 of the semiconductor substrate SSUB.

[0199] The first driving voltage VSS can be applied to the third power connection area PCAA3 of the semiconductor substrate SSUB. Alternatively, in one or more embodiments, the third power connection area PCAA3 of the semiconductor substrate SSUB can be electrically floating.

[0200] The permeation-preventing electrode MPE can be substantially identical to the pad metal layer PML shown in Figure 10

[0201] The permeation-preventing electrode MPE can include a first sub-permeation-preventing electrode SMPE1 and a second sub-permeation-preventing electrode SMPE2. The first sub-permeation-preventing electrode SMPE1 and the second sub-permeation-preventing electrode SMPE2 of the permeation-preventing electrode MPE can be substantially identical to the first sub-pad metal layer SPML1 and the second sub-pad metal layer SPML2, respectively, as shown in Figure 10

[0202] The crack-preventing portion CPA includes the fourth power connection area PCAA4 of the semiconductor substrate SSUB.

[0203] The first driving voltage VSS can be applied to the fourth power connection area PCAA4 of the semiconductor substrate SSUB. Alternatively, in one or more embodiments, the fourth power connection area PCAA4 of the semiconductor substrate SSUB can be electrically floating. The fourth power connection area PCAA4 can be connected to the contact terminal CTE, the first metal layer ML1 to the eighth metal layer ML8, and the first via VA1 to the eighth via VA8.

[0204] Figure 13 is a cross-sectional view of the region A2 of Figure 11

[0205] The display device 10 according to one or more embodiments, as shown in Figure 12 and Figure 13 The end of the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 can be arranged (aligned) in a row along a diagonal direction, as in the example shown in

[0206] ​​​An angle θ between the first end E1 of the first sub-encapsulation layer TFE1 and the bottom surface BS of the first sub-encapsulation layer TFE1 can be an acute angle. For example, the angle θ between the first end E1 and the bottom surface BS of the first sub-encapsulation layer TFE1 can be 30 to 60 degrees. Here, the bottom surface BS of the first sub-encapsulation layer TFE1 can be an interface between the third pixel definition film PDL3 and the first sub-encapsulation layer TFE1.

[0207] An angle between the third end E3 of the third sub-encapsulation layer TFE3 and the aforementioned bottom surface BS can be an acute angle. For example, the angle between the third end E3 of the third sub-encapsulation layer TFE3 and the bottom surface BS can be 30 to 60 degrees.

[0208] An angle between the fourth end E4 of the fourth sub-encapsulation layer TFE4 and the aforementioned bottom surface BS can be an acute angle. For example, the angle between the fourth end E4 of the fourth sub-encapsulation layer TFE4 and the bottom surface BS can be 30 to 60 degrees.

[0209] The angle θ between the first end E1 and the bottom surface BS, the angle between the third end E3 and the bottom surface BS, and the angle between the fourth end E4 and the bottom surface BS can be equal to each other.

[0210] According to one or more embodiments, the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 can be manufactured by a photolithography process using one mask (e.g., the same mask), so that the first end E1 of the first sub-encapsulation layer TFE1, the third end E3 of the third sub-encapsulation layer TFE3, and the fourth end E4 of the fourth sub-encapsulation layer TFE4 can be arranged along an imaginary diagonal line. Also, because the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 are manufactured by the photolithography process using one mask (e.g., the same mask), the angle θ between the first end E1 and the bottom surface BS, the angle between the third end E3 and the bottom surface BS, and the angle between the fourth end E4 and the bottom surface BS can be equal to each other.

[0211] Figures 14 to 28 is a cross-sectional view illustrating a method for manufacturing a display device 10 according to one or more embodiments of the present disclosure.

[0212] First, as shown in Figure 14 and Figure 15 The light emitting element base plate EBP can be formed on the semiconductor base plate SBP, and a display element layer EML including a light emitting element LE can be formed on the light emitting element base plate EBP.

[0213] Thereafter, as shown in Figure 16 and Figure 17As shown, the first sub-encapsulation layer TFE1 covering the light-emitting element LE can be formed on the display element layer EML. For example, the first sub-encapsulation layer TFE1 can be formed on the second electrode CAT, the pad metal layer PML of the first pad PD1, and the tenth insulating layer INS10. In such an embodiment, the first sub-encapsulation layer TFE1 can be formed over the entire surface of the semiconductor substrate SSUB (including the second electrode CAT, the pad metal layer PML of the first pad PD1, and the tenth insulating layer INS10). The first sub-encapsulation layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0214] Next, as Figure 18 As shown, the second sub-package layer TFE2 can be formed on the first sub-package layer TFE1. The second sub-package layer TFE2 can be selectively formed in the display area DAA and its peripheral edges using a deposition mask. The second sub-package layer TFE2 may not be disposed on the pad metal layer PML of the first pad PD1. For example, the second sub-package layer TFE2 may not be disposed on the first sub-package layer TFE1 on the pad metal layer PML of the first pad PD1.

[0215] Next, as Figure 19 and Figure 20 As shown, a third sub-package layer TFE3 can be formed on the first sub-package layer TFE1 and the second sub-package layer TFE2, and then a fourth sub-package layer TFE4 can be formed on the third sub-package layer TFE3. In such an embodiment, the third sub-package layer TFE3 can be formed covering the entire surface of the semiconductor substrate SSUB (including the first and second sub-package layers TFE1 and TFE2). The third sub-package layer TFE3 can be formed by a chemical vapor deposition (CVD) process. Furthermore, the fourth sub-package layer TFE4 can be formed covering the entire surface of the semiconductor substrate SSUB (including the third sub-package layer TFE3). The fourth sub-package layer TFE4 can be formed by an atomic layer deposition (ALD) process.

[0216] In one or more embodiments, such as Figure 20 As shown, the second sub-package layer TFE2 is not disposed on the pad metal layer PML of the first pad PD1, so that the first sub-package layer TFE1 and the third sub-package layer TFE3 can contact each other on the pad metal layer PML of the first pad PD1.

[0217] Next, as Figure 21 As shown, the organic layer APL can be formed on the package layer TFE (e.g., the fourth sub-package layer TFE4). In such an embodiment, the organic layer APL is not formed on the pad metal layer PML of the first pad PD1.

[0218] After that, asFigure 22 As shown in FIG. 1A, a first color filter CF1 overlapping the first emission area EA1 can be formed on the organic layer APL, a second color filter CF2 overlapping the second emission area EA2 can be formed, and a third color filter CF3 overlapping the third emission area EA3 can be formed. In one or more embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 are not formed on the pad metal layer PML of the first pad PD1.

[0219] Next, as shown in FIG. 1B, a first lens pattern layer LNL1 can be formed on the color filters CF1, CF2, and CF3, and a second lens pattern layer LNL2 can be formed on the first lens pattern layer LNL1. In such embodiments, the first lens pattern layer LNL1 can be formed not only on the color filters CF1, CF2, and CF3, but also on the fourth sub-package layer TFE4 in the first pad portion PDA1 and the second pad portion PDA2. For example, as shown in FIG. 1C, the first lens pattern layer LNL1 and the second lens pattern layer LNL2 can be formed on the pad metal layer PML of the first pad PD1. Figure 23 Figure 24 Next, as shown in FIG. 1B, a first lens pattern layer LNL1 can be formed on the color filters CF1, CF2, and CF3, and a second lens pattern layer LNL2 can be formed on the first lens pattern layer LNL1. In such embodiments, the first lens pattern layer LNL1 can be formed not only on the color filters CF1, CF2, and CF3, but also on the fourth sub-package layer TFE4 in the first pad portion PDA1 and the second pad portion PDA2. For example, as shown in FIG. 1C, the first lens pattern layer LNL1 and the second lens pattern layer LNL2 can be formed on the pad metal layer PML of the first pad PD1. Figure 24

[0220] The second lens pattern layer LNL2 can be formed by a photolithography process. The second lens pattern layer LNL2 can have an upwardly convex pattern shape on the first lens pattern layer LNL1 disposed on the color filters CF1, CF2, and CF3. The second lens pattern layer LNL2 can not be disposed at edges of the color filters CF1, CF2, and CF3. For example, the second lens pattern layer LNL2 can be disposed apart from and / or separated from each other (e.g., spaced apart or separated from each other).

[0221] Further, the second lens pattern layer LNL2 can be formed on the first lens pattern layer LNL1 disposed on the second sub-pad metal layer SPML2 and the tenth insulating layer INS10 in the first pad portion PDA1 and the second pad portion PDA2. The second lens pattern layer LNL2 can not have a convex pattern shape in the first pad portion PDA1 and the second pad portion PDA2, and for example, as shown in FIG. 1C, the second lens pattern layer LNL2 can be formed flat (e.g., can have a flat upper surface). Figure 24

[0222] Thereafter, as shown in FIG. 1D, a third lens pattern layer LNL3 can be formed on the second lens pattern layer LNL2. In such embodiments, the third lens pattern layer LNL3 can be formed not only on the second lens pattern layer LNL2, but also on the eleventh insulating layer INS11 in the first pad portion PDA1 and the second pad portion PDA2. For example, as shown in FIG. 1E, the third lens pattern layer LNL3 and the second lens pattern layer LNL2 can be formed on the pad metal layer PML of the first pad PD1. Figure 25 Figure 26 ​​​​As shown in FIG. 1A, the plurality of lenses LNS can be formed by selectively removing the first lens pattern layer LNL1 and the second lens pattern layer LNL2 by means of a dry etching process. Because the second lens pattern layer LNL2 disposed on the plurality of color filters CF1, CF2, and CF3 has an upwardly convex shape, the plurality of lenses LNS can be patterned to have an upwardly convex shape similar to that of the second lens pattern layer LNL2.

[0223] The thickness of the first lens pattern layer LNL1 can be greater than the thickness of the second lens pattern layer LNL2. For example, the first lens pattern layer LNL1 can have a thickness of approximately 2.5 µm, and the second lens pattern layer LNL2 can have a thickness of approximately 1.5 µm. In such an embodiment, if the thickness of the first lens pattern layer LNL1 etched away by the dry etching process is greater than the thickness of the second lens pattern layer LNL2 and less than the total thickness of the first lens pattern layer LNL1 (e.g., when the thickness of the first lens pattern layer LNL1 etched away by the dry etching process is greater than the thickness of the second lens pattern layer LNL2 and less than the total thickness of the first lens pattern layer LNL1), then the first lens pattern layer LNL1 can remain in regions where the second lens pattern layer LNL2 is not formed even if the first lens pattern layer LNL1 and the second lens pattern layer LNL2 are etched together. Accordingly, the plurality of color filters CF1, CF2, and CF3 can be protected. However, the present disclosure is not limited thereto, and the entire first lens pattern layer LNL1 disposed in regions where the second lens pattern layer LNL2 is not formed can be etched. In such an embodiment, as shown in FIG. 1A, the plurality of lenses LNS can be formed by selectively removing the first lens pattern layer LNL1 and the second lens pattern layer LNL2 by means of a dry etching process. Figure 25 As shown in FIG. 1A, the plurality of lenses LNS can be arranged to be spaced apart and / or separated from each other (e.g., spaced apart or separated from each other).

[0224] For example, as shown in FIG. 1A, in the first pad portion PDA1 and the second pad portion PDA2, the second lens pattern layer LNL2 can be removed by a dry etching process. Figure 26

[0225] The first lens pattern layer LNL1 and the second lens pattern layer LNL2 can be made of the same material. Alternatively, in one or more embodiments, if the first lens pattern layer LNL1 and the second lens pattern layer LNL2 are made of different materials (e.g., when the first lens pattern layer LNL1 and the second lens pattern layer LNL2 are made of different materials), the etching rate of the first lens pattern layer LNL1 and the etching rate of the second lens pattern layer LNL2 using an etching gas in the dry etching process can be substantially the same.

[0226] Thereafter, as shown in FIG. 1A, the plurality of lenses LNS can be formed by selectively removing the first lens pattern layer LNL1 and the second lens pattern layer LNL2 by means of a dry etching process. Figure 27 and Figure 28 ​As shown, the encapsulation layer TFE and the first lens pattern layer LNL1 arranged on the second sub-pad metal layer SPML2 in the first pad portion PDA1 and the second pad portion PDA2 can be removed.

[0227] Because the second lens pattern layer LNL2 is arranged across the entire area of ​​the first sub-pad BPD and the second sub-pad IPD, therefore... Figure 26 During the etching step (e.g., action or task), the first lens pattern layer LNL1 can remain in the first pad portion PDA1 and the second pad portion PDA2 without being removed. Therefore, in Figure 26 During the etching step (e.g., action or task), only the second lens pattern layer LNL2 can be removed.

[0228] Next, as Figure 27 and Figure 28 As shown, the first lens pattern layer LNL1, the fourth sub-package layer TFE4, the third sub-package layer TFE3, and the first sub-package layer TFE1 can be removed based on the mask pattern MP. In such an embodiment, the mask pattern MP can be formed in areas other than the first pad portion PDA1 and the second pad portion PDA2. A dry etching process is performed using the mask pattern MP, such as... Figure 28 As shown, the first lens pattern layer LNL1, the fourth sub-package layer TFE4, the third sub-package layer TFE3, and the first sub-package layer TFE1 of the first pad portion PDA1 can be removed, allowing the fourth sub-package layer TFE4, the third sub-package layer TFE3, and the first sub-package layer TFE1 to be patterned. Furthermore, the second sub-pad metal layer SPML2 of the pad metal layer PML can be exposed. Correspondingly, the fourth sub-package layer TFE4, the third sub-package layer TFE3, and the first sub-package layer TFE1 can be patterned to avoid forming in the invalid space region of the semiconductor substrate SSUB, and the first pad PD1 of the first pad portion PDA1 and the second pad PD2 of the second pad portion PDA2 can be exposed respectively. In such an embodiment, when the dry etching process using the aforementioned mask pattern MP is performed, as... Figure 13 As shown, the ends E1, E3, and E4 of the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 can be arranged in a row along a diagonal direction. Furthermore, the angle θ between the first end E1 of the first sub-encapsulation layer TFE1 and the bottom surface BS, the angle between the third end E3 of the third sub-encapsulation layer TFE3 and the bottom surface BS, and the angle between the fourth end E4 of the fourth sub-encapsulation layer TFE4 and the bottom surface BS can be equal to each other. In such an embodiment, the aforementioned angles can be acute angles.

[0229] Thereafter, after the dry etching process, the mask pattern MP can be removed by a lift-off process.

[0230] Next, as shown in Figure 7 FIL can be formed on the plurality of lenses LNS, and a cover layer CVL can be disposed on the fill layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate, and the fill layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a polymer resin, it can be directly coated onto the fill layer FIL.

[0231] Next, as shown in Figure 7 POL can be attached to the cover layer CVL.

[0232] According to the method for manufacturing the display device 10 according to one or more embodiments, the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 can be patterned together in a process of exposing the first pad PD1 and the second pad PD2, so that the number of masks can be reduced. For example, the process of patterning the first sub-encapsulation layer TFE1, the third sub-encapsulation layer TFE3, and the fourth sub-encapsulation layer TFE4 and the process of exposing the second sub-pad metal layer SPML2 of each of the first pad PD1 and the second pad PD2 can be performed by one mask (e.g., the same mask (e.g., the mask pattern MP)). Accordingly, the manufacturing cost of the display device 10 can be reduced.

[0233] Figure 29 is a cross-sectional view of a display device according to one or more embodiments. For example, Figure 29 is a cross-sectional view showing another example of the display panel 100 taken along the line E-E’ of Figure 4

[0234] Figure 29 The display device of Figure 11 The display device of differs from the display device of in that it further includes a spacer SPC. The following description will mainly focus on this difference.

[0235] As shown in Figure 29 ​As illustrated in FIG. 1, the spacer SPC can be disposed on the third pixel defining film PDL3. The spacer SPC can include an organic material. The spacer SPC can support a deposition mask used, for example, in a process of forming the second sub-encapsulation layer TFE2 described above. Accordingly, during the process of forming the second sub-encapsulation layer TFE2, contact between the deposition mask and the substrate structure (e.g., the third pixel defining film PDL3) can be minimized or reduced. Thus, particles generated due to contact between the deposition mask and the substrate structure, and contamination of the particles during the process can be prevented or reduced, thereby improving the reliability of the display device 10.

[0236] Figure 30 is a perspective view illustrating a head-mounted display 1000 according to one or more embodiments of the disclosure. Figure 31 is an exploded perspective view illustrating the head-mounted display 1000 according to one or more embodiments of the disclosure. Figure 30

[0237] Referring to Figure 30 and Figure 31 , the head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0238] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Since each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figures 1 to 29 a redundant description of the first display device 10_1 and the second display device 10_2 can not be provided.

[0239] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0240] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and can be disposed between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 functions to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0241] ​The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through the middle frame 1400. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the middle frame 1400.

[0242] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image that can be improved or optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image that can be improved or optimized for the user's right eye to the second display device 10_2. Alternatively, in one or more embodiments, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0243] The display device housing 1100 serves to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed to cover one open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 at which the user's left eye is located, and a second eyepiece 1220 at which the user's right eye is located. Figure 30 and Figure 31 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are disposed separately, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be merged into one eyepiece.

[0244] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0245] The head-mounted band 1300 serves to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained at (on) the user's left eye and right eye. When the display device housing 1200 is implemented to be light in weight and compact, the head-mounted display 1000 can be provided with a head-mounted band 1300 as Figure 32The eyeglass temples 1040 and 1050 shown in FIG. 1 can be replaced with the head-mounted band 1300.

[0246] In one or more embodiments, the head-mounted display 1000 can further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0247] Figure 32 is a perspective view showing a head-mounted display 1000_1 according to one or more embodiments of the disclosure.

[0248] Referring to Figure 32 The head-mounted display 1000_1 according to one or more embodiments can be a glasses-type (glasses-like) display device in which the display device housing 1200_1 is implemented in a light-weight and compact manner. The head-mounted display 1000_1 according to one or more embodiments can include a display device 10_4, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, eyeglass temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0249] The display device housing 1200_1 can accommodate the display device 10_4, the optical member 1060, and the optical path changing member 1070. An image displayed on the display device 10_4 can be magnified by the optical member 1060 and can be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_4 and a real image seen through the right-eye lens 1020 are combined.

[0250] Figure 32 It is shown that the display device housing 1200_1 is arranged at the right end of the support frame 1030, but the disclosure is not limited thereto. For example, the display device housing 1200_1 can be arranged at the left end of the support frame 1030, and in such an embodiment, an image of the display device 10_4 can be provided to the left eye of the user. Alternatively, in one or more embodiments, the display device housing 1200_1 can be arranged at both the left end and the right end of the support frame 1030, and in such an embodiment, the user can view, through both the left eye and the right eye (e.g., simultaneously), an image displayed on the display device 10_4.

[0251] The display device 10 according to one or more embodiments can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments includes the display device 10 described above, and the electronic device can further include a module or a device having an additional function, in addition to the display device 10.

[0252] Figure 33 is a block diagram of an electronic device 50 according to one or more embodiments of the disclosure. Referring to Figure 33 , the electronic device 50 according to one or more embodiments can include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 can further include an input module 15, an output module 16, and / or a communication module 17.

[0253] The electronic device 50 can output various information in the form of an image through the display module 11. When the processor 12 executes an application stored in the memory 13, image information provided by the application can be provided to a user through the display module 11. The power module 14 can include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power for the operation of the electronic device 50. The input module 15 can provide input information to the processor 12 and / or the display module 11. The output module 16 can receive information (e.g., sound, haptics, and light) other than an image transmitted from the processor 12, and can provide the information to the user. The communication module 17 is a module responsible for transmitting and receiving information between the electronic device 50 and an external device, and can include a receiving unit and a transmitting unit.

[0254] At least one of the components of the electronic device 50 described above can be included in the display device 10 according to one or more embodiments described above. In addition, some of the functionally independent modules included in one module can be included in the display device 10, and the other modules can be provided separately from the display device 10. For example, the display module 11 can be included in the display device 10, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 50 other than the display device 10.

[0255] Figure 34 、 Figure 35 and Figure 36 is a schematic perspective view of an electronic device according to one or more embodiments of the disclosure. Figures 34 to 36 Examples of one or more suitable electronic devices to which the display device 10 according to one or more embodiments can be applied are illustrated.

[0256] Figure 34Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0257] In addition to the display module, the smartphone 10_1a may include an input module such as a touch sensor, and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules, and can display the processed information through the display module of the display device.

[0258] In the cases of tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e, similar to smartphone 10_1a, they also include a display module and an input module, and in some embodiments, they may additionally include a communication module.

[0259] Figure 35 An example is shown where an electronic device, including a display module, is applied to a wearable electronic device. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, and / or a smartwatch 10_2c, etc.

[0260] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with virtual reality and / or augmented reality images.

[0261] The smartwatch 10_2c may include a biosensor as an input device and can provide the user with biological information identified by the biosensor through a display module. Figure 36 The illustration shows an application of an electronic device, including a display module, to a vehicle. For example, the electronic device 10_3 can be applied to the vehicle's dashboard and / or central instrument panel, or it can be applied to a central information display (CID) placed on the vehicle's dashboard or an interior rearview mirror display that replaces the side mirrors.

[0262] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0263] Furthermore, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure".

[0264] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximations and not as terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein, “substantially” encompasses the value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art. For example, “substantially” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5% of the value.

[0265] Furthermore, any numerical range disclosed and / or recorded herein is intended to include all subranges with the same numerical precision contained within the recorded range. For example, the range “1.0 to 10.0” is intended to include all subranges between the recorded minimum value of 1.0 and the recorded maximum value of 10.0 (and including both the recorded minimum value of 1.0 and the recorded maximum value of 10.0), i.e., all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit recorded herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to amend the application document including the claims to explicitly record any subranges contained within the range explicitly recorded herein.

[0266] Display devices, electronic devices, means for manufacturing display devices, and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or a discrete IC chip. Furthermore, various components of the device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), or a printed circuit board (PCB), or can be formed on a substrate. Additionally, various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented using standard memory devices (such as, for example, random access memory (RAM)) in the computing device. The computer program instructions can also be stored in other non-transitory computer-readable media (such as, for example, CD-ROMs or flash drives). Furthermore, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of embodiments of the present disclosure.

[0267] Those skilled in the art will understand that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole and may be technically linked and operated in various suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable way, unless otherwise stated or implied.

[0268] It will be understood that the description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments, unless otherwise described. Therefore, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. It should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the claims and their equivalents.

Claims

1. A display device, comprising: substrate; The first electrode is on the substrate; A pixel-defining film is disposed on the first electrode; A light-emitting stack on the first electrode and the pixel defining film; The second electrode is on the light-emitting stack; as well as Encapsulation layer, on the second electrode, The encapsulation layer includes multiple sub-encapsulation layers, and At least two ends of the plurality of sub-encapsulation layers are aligned in one direction.

2. The display device according to claim 1, wherein, The direction mentioned is a diagonal direction.

3. The display device according to claim 1, wherein, The angle between each of the at least two ends of the plurality of sub-encapsulation layers and the bottom surface of one of the plurality of sub-encapsulation layers is an acute angle.

4. The display device according to claim 3, wherein, The angle between one of the at least two ends and the bottom surface is equal to the angle between the other of the at least two ends and the bottom surface.

5. The display device according to claim 1, wherein, The encapsulation layer includes: The first sub-encapsulation layer is on the second electrode; The second sub-encapsulation layer is on top of the first sub-encapsulation layer; A third sub-encapsulation layer, on top of the second sub-encapsulation layer; and The fourth sub-encapsulation layer, on top of the third sub-encapsulation layer, The first sub-encapsulation layer, the third sub-encapsulation layer, and the fourth sub-encapsulation layer comprise inorganic materials, and The second sub-encapsulation layer comprises organic materials.

6. The display device according to claim 5, wherein, The corresponding ends of the first sub-encapsulation layer, the third sub-encapsulation layer, and the fourth sub-encapsulation layer are aligned along the one direction.

7. The display device according to claim 5, wherein, The corresponding ends of the first sub-encapsulation layer, the third sub-encapsulation layer, and the fourth sub-encapsulation layer are aligned along a diagonal line.

8. The display device according to claim 5, wherein, The angle between the end of each of the first sub-encapsulation layer, the third sub-encapsulation layer, and the fourth sub-encapsulation layer and the bottom surface of the first sub-encapsulation layer is an acute angle.

9. The display device according to claim 8, wherein, The angle between the end of the first sub-encapsulation layer and the bottom surface, the angle between the end of the third sub-encapsulation layer and the bottom surface, and the angle between the end of the fourth sub-encapsulation layer and the bottom surface are equal to each other.

10. The display device according to claim 1, further comprising: An organic layer is present on the encapsulation layer.

11. An optical device, comprising: The display device according to any one of claims 1 to 10; as well as The optical path changing component is located on the display device.

12. An electronic device comprising: The display device according to any one of claims 1 to 10.

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