Battery management system and battery management method

Abstract

The invention discloses a battery management system and a battery management method. The battery management system includes: a battery monitoring IC (BMIC) for measuring a state of a battery; a processor for controlling all operations of the battery management system; a transceiver for identifying the measured state of the battery and transmitting the state of the battery to a processor; and a power management circuit for supplying power to the processor, in which the processor includes a first terminal (VDDSPowerControl) that outputs a first signal for controlling the first transistor, and controls the first transistor using the first signal, and thus may provide a VDDS signal for determining low power mode operation.

Description

Technical Field

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0002631, filed with the Korean Intellectual Property Office on January 8, 2024, the entire contents of which are incorporated herein by reference.

[0003] This disclosure relates to battery management systems and battery management methods. Background Technology

[0004] Unlike internal combustion engine vehicles, electric vehicles are much harder to extinguish when they catch fire, often burning the entire vehicle before it is destroyed. Furthermore, unlike internal combustion engine vehicles, electric vehicles are characterized by instantaneous combustion, and the number of casualties can increase if rescue efforts are delayed. This is caused by a phenomenon known as "thermal runaway," where battery temperatures can spike above 1000 degrees Celsius.

[0005] Research and development are currently underway to detect battery thermal runaway in advance. Methods that predict battery thermal runaway by collecting battery data such as temperature and voltage and analyzing changes in the collected data are already widely used.

[0006] However, when the battery is being charged using an external power source, the Battery Management System (BMS) is in sleep or shutdown mode. Therefore, the BMS cannot collect battery data or predict battery thermal runaway in advance. In other words, because battery thermal runaway is not detected early, most battery-related fires occur during battery charging. Summary of the Invention

[0007] Technical issues

[0008] This disclosure attempts to provide a battery management system and battery management method that can accurately diagnose battery thermal runaway even when the battery is being charged with power from an external charger or when the battery management system (BMS) is in sleep mode because the advanced system on which the battery is installed (e.g., a car, an energy storage system) is not in operation.

[0009] Technical solution

[0010] An exemplary embodiment of this disclosure provides a battery management system, which includes: a battery monitoring IC, i.e., a BMIC, for measuring the state of a battery; a processor for controlling the overall operation of the battery management system; a transceiver for identifying the measured state of the battery and transmitting the identified state to the processor; and a power management circuit for providing power to the processor, wherein the processor includes a first terminal for outputting a first signal controlling a first transistor, and provides a power signal for determining operation in a low-power mode by using the first signal to control the first transistor.

[0011] In some exemplary embodiments, the processor may further include a second terminal that outputs a second signal for controlling a second transistor, and use the second signal to control the second transistor to change the resistance value connected to a third terminal indicating whether a low-power mode is used.

[0012] In some exemplary embodiments, the value of the signal at the third terminal can be detected when the voltage level of the power supply signal changes.

[0013] In some exemplary embodiments, when an unexpected fault occurs, the signal at the fourth terminal of the transceiver can be switched from a second voltage level to a first voltage level, and the processor, transceiver, and BMIC can be woken up.

[0014] In some exemplary embodiments, after the processor, transceiver, and BMIC are woken up, the second signal output from the second terminal can change from the off state to the on state, and the resistance value connected to the third terminal can be changed to a state of 0 kΩ.

[0015] In some exemplary embodiments, when the resistance value connected to the third terminal is in the state of being connected to 0 kΩ, the first signal output from the first terminal can be changed from the off state to the on state, and can be changed so that no voltage is applied to the power supply terminal.

[0016] In some exemplary embodiments, the first signal output from the first terminal can change from an on state to an off state, and a voltage can be applied to the power terminal again. When a voltage is applied to the power terminal again, the value of the third terminal can be captured, and the battery management system can be set to not use a low-power mode based on the captured value.

[0017] In some exemplary embodiments, the second signal output from the second terminal can return from the on state to the off state, and the resistance value connected to the third terminal can be changed to a state where 20 kΩ is connected.

[0018] In some exemplary embodiments, when a low-power mode entry command occurs, the signal at the fifth terminal of the transceiver can change from a first voltage level to a second voltage level. The fifth terminal provides an output indicating whether the processor is in normal operation or low-power mode entry state, and the processor, transceiver, and BMIC can re-enter low-power mode.

[0019] Another exemplary embodiment of this disclosure provides a battery management method performed by a battery management system, the battery management system including: a battery monitoring IC, i.e., a BMIC, for measuring the state of a battery; a processor for controlling the overall operation of the battery management system, and including a first terminal for outputting a first signal controlling a first transistor and a second terminal for outputting a second signal controlling a second transistor; a transceiver for identifying the measured state of the battery and transmitting the identified state of the battery to the processor; and a power management circuit for providing power to the processor, the battery management method including the steps of: the processor controlling the first transistor by using the first signal to provide a power signal for determining operation in a low-power mode; and controlling the second transistor by using the second signal to change the resistance value connected to a third terminal indicating whether a low-power mode is used.

[0020] In some exemplary embodiments, the value of the signal at the third terminal can be detected when the voltage level of the power supply signal changes.

[0021] In some exemplary embodiments, the battery management method may further include the following steps: when an unexpected fault occurs, switching the signal at the fourth terminal of the transceiver from a second voltage level to a first voltage level; and waking up the processor, transceiver, and BMIC.

[0022] In some exemplary embodiments, the battery management method may further include the following steps: after the processor, transceiver and BMIC are woken up, changing the second signal output from the second terminal from the off state to the on state; and changing the resistance value connected to the third terminal to a state of 0 kΩ connection.

[0023] In some exemplary embodiments, the battery management method may further include the following steps: when the resistance value connected to the third terminal is in a state of 0 kΩ, changing the first signal output from the first terminal from a cut-off state to a conduction state; and changing it so that no voltage is applied to the power supply terminal.

[0024] In some exemplary embodiments, the battery management method may further include the following steps: transitioning a first signal output from a first terminal from an on state to an off state; applying voltage to the power terminal again; capturing the value of a third terminal when voltage is applied to the power terminal again; and setting the battery management system to not use a low-power mode based on the captured value.

[0025] In some exemplary embodiments, the battery management method may further include the following steps: returning a second signal output from the second terminal from the on state to the off state; and changing the resistance value connected to the third terminal to a state where 20 kΩ is connected.

[0026] In some exemplary embodiments, the battery management method may further include the following steps: when a low-power mode entry command occurs, switching a signal at a fifth terminal of the transceiver from a first voltage level to a second voltage level, the fifth terminal providing an output indicating whether the processor is in normal operation or in a low-power mode entry state; and causing the processor, transceiver, and BMIC to re-enter low-power mode.

[0027] Beneficial effects

[0028] According to an exemplary embodiment, even when the BMS is in sleep mode, thermal runaway of the battery can be accurately diagnosed to reduce personal injury and property damage. Specifically, it addresses the problem of vehicles failing to re-enter sleep mode after being awakened from low-power mode due to unexpected faults such as loss of communication and connector damage, rather than changes in cell voltage and temperature. Furthermore, by resolving this issue, it prevents the vehicle's lead-acid battery from being discharged due to its inability to enter sleep mode. Attached Figure Description

[0029] Figure 1 This is a circuit diagram illustrating a battery management system according to an exemplary embodiment.

[0030] Figure 2 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment.

[0031] Figure 3 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment.

[0032] Figure 4 It is a timing diagram used to illustrate a situation where a low-power mode is not allowed due to an unexpected fault.

[0033] Figure 5 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment. Detailed Implementation

[0034] In the following description, exemplary embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar constituent elements will be indicated by the same reference numerals, and repeated descriptions will be omitted. The suffixes “module” and / or “unit” used for the constituent elements described below are given or combined only for convenience of writing the specification, and the suffixes themselves have no distinguishing meaning or function. In describing the exemplary embodiments disclosed in this disclosure, detailed descriptions will be omitted where it is determined that detailed descriptions related to well-known functions or configurations would unnecessarily obscure the subject matter of the exemplary embodiments disclosed in this disclosure. Furthermore, the accompanying drawings are provided to aid in the easy understanding of the exemplary embodiments disclosed in this specification, and the technical spirit disclosed in this specification is not limited to the drawings. It should be understood that this disclosure includes all modifications, equivalents, and alternatives included within the spirit and scope of this disclosure.

[0035] Ordinal terms such as first and second are used to describe various components, but components are not limited by these terms. These terms are only used to distinguish one component from another.

[0036] It should be understood that when a component is indicated as "connected to" or "connected to" another component, the component may be directly connected to or connected to the other component, but there may also be intermediate components. In contrast, when a component is "directly connected to" or "directly connected to" another component, it should be understood that there are no intermediate components.

[0037] In this application, it should be understood that the terms "comprising" and "having" are intended to specify the presence of the features, numbers, steps, operations, components and parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components and parts or combinations thereof.

[0038] Figure 1 This is a circuit diagram illustrating a battery management system according to an exemplary embodiment.

[0039] Reference Figure 1 The battery management system (BMS) 1 according to an exemplary embodiment may include a processor 10, a transceiver 11, an isolator 12, battery monitoring ICs (BMICs) 13a and 13b, and a power management circuit 14.

[0040] The processor 10 can control the overall operation of the battery management system 1 and perform the functions required for battery management. For example, the processor 10 can continuously monitor the voltage, current, temperature, etc. of the battery cells, perform cell balancing to adjust the voltage difference between battery cells, or detect conditions that may damage the battery, such as overcharging, over-discharging, and overheating, and take protective measures. Furthermore, the processor 10 can predict, for example, the battery's state, lifespan, and charging time based on the data monitored for the battery, perform state assessment and diagnosis, and handle communication with other external devices. In some exemplary embodiments, the processor 10 can be implemented as a microcontroller unit (MCU).

[0041] A battery can have a discharged state, a charged state, or an idle state. A discharged state is a state in which the battery is discharged by supplying power to an external device (e.g., a load); a charged state is a state in which the battery is charged by receiving power from an external device (e.g., a charger); and an idle state is a state in which the battery and an external device are electrically connected but no power is being transferred. In the discharged state, the battery management system 1 can operate in an operating mode that executes setup logic to check the battery's state and perform safe operations. In the charged and idle states, the battery management system 1 can operate in a sleep mode where no logic is executed. However, since the battery management system 1 cannot monitor the battery's state when it is in sleep mode, it is difficult to prepare for battery fires in advance. To address this issue, in this exemplary embodiment, the battery management system 1 can operate in a low-power mode. In this low-power mode, the battery management system 1 monitors the battery's state by being periodically woken up to prevent thermal runaway, heat propagation, etc., in the charged and idle states.

[0042] The battery management system 1 operates in low-power mode during charging and idle states and is periodically woken up to monitor battery parameters such as cell overheating (OT), undervoltage (UV), and temperature difference (ΔT). Here, cell OT is a parameter indicating that the battery cell is overheating and the temperature of the battery cell exceeds the safe operating range, UV is a parameter indicating that the voltage of the battery cell has dropped below the normal operating range, indicating an over-discharge state, and ΔT is a parameter indicating the temperature difference between the battery cells.

[0043] When it is determined that the corresponding parameter value is not abnormal, the battery management system 1 can repeatedly enter and exit sleep mode and be woken up again to monitor the parameters in the next cycle. Specifically, when the corresponding parameter value is not abnormal, transceiver 11 and BMICs 13a and 13b periodically repeat wake-up and sleep cycles, while processor 10 remains in sleep mode. When it is determined that the corresponding parameter value that can predict the fire risk of the battery is abnormal, processor 10, transceiver 11, and BMICs 13a and 13b are all woken up, and processor 10 can notify the electronic control unit (ECU) of the vehicle 15 of the abnormal battery status via controller area network communication, etc., to execute a safety response such as disconnecting a relay to disconnect the electrical connection with external devices.

[0044] However, apart from detecting an abnormal battery state, the processor 10, transceiver 11, and BMICs 13a and 13b can all be woken up due to other factors. For example, the processor 10, transceiver 11, and BMICs 13a and 13b can all be woken up due to communication loss, connector damage, etc. In this specification, factors that stop the sleep mode based on the battery state in order to prevent battery fire are referred to as "expected faults," while factors that stop the sleep mode other than the symptoms of a battery fire are referred to as "unexpected faults."

[0045] In the event of an unexpected malfunction, the battery management system 1 needs to re-enter the low-power mode. However, if the battery management system 1 is unable to enter the low-power mode, there is a risk of wasting battery power or causing the vehicle's lead-acid battery to discharge in the worst case.

[0046] The processor 10 can control situations where the battery management system 1, awakened by the aforementioned unexpected fault, cannot enter low-power mode. This will be described in detail below.

[0047] Transceiver 11 can identify the status of BMICs 13a and 13b, and thereby perform the operation of waking up processor 10 or power management circuitry 14. For example, transceiver 12 can receive accumulated battery status from BMICs 13a to 13b. When an alarm indicating a battery status problem is received, transceiver 11 can output an interrupt signal INTR to wake up power management circuitry 14. Subsequently, the woken-up power management circuitry 14 can wake up processor 10. Although Figure 1 The diagram shows transceiver 11 outputting an interrupt signal INTR to power management circuit 14. However, unlike the diagram, transceiver 11 can directly wake up processor 10 by outputting an interrupt signal INTR to processor 10.

[0048] Isolator 12 can perform isolation for circuit regions in the battery management system 1, including processor 10, transceiver 11, and power management circuitry 14, as well as circuit regions including BMICs 13a and 13b. Here, processor 10, transceiver 11, and power management circuitry 14 may belong to a main BMS or battery pack control module (BPCM) that diagnoses battery states such as voltage, current, and temperature, and communicate with vehicle 15. Isolator 12 and BMICs 13a and 13b may belong to a slave BMS or cell monitoring circuitry. In some exemplary embodiments, isolator 12 may be implemented using a transformer or capacitor.

[0049] Each of BMICs 13a and 13b can measure the voltage of multiple electrically connected battery cells, perform cell balancing on the multiple battery cells, and perform temperature measurement using general purpose input / output (GPIO). Specifically, BMICs 13a and 13b can themselves perform low-power mode operation. Specifically, even in sleep mode, BMICs 13a and 13b can be woken up at preset intervals to detect changes in cell voltage, cell temperature, changes in the rate of temperature rise, etc., and generate an alarm when the detected value exceeds a predetermined threshold. In some exemplary embodiments, BMICs 13a and 13b are daisy-chained, such that alarms generated by BMIC 13a are sent to BMIC 13b, accumulated together with alarms generated by BMIC 13b, and sent to processor 10 via transceiver 11. Processor 10 can ultimately detect abnormal battery states based on the alarms.

[0050] In some exemplary embodiments, BMICs 13a and 13b can detect battery voltage fluctuations by being repeatedly woken up from sleep mode. When the battery voltage fluctuation exceeds a predetermined threshold, BMICs 13a and 13b can perform cell balancing. Cell balancing can be performed on individual cells or specific cells using, for example, a direct current (DC) method or a pulse width modulation (PWM) method. When cell balancing ends after a certain period of time, information related to the cell balancing progress from the lowest BMIC 13a to the highest BMIC 13b can be sent to transceiver 11. When transceiver 11 receives an alarm indicating a problem with the battery status, it can wake up the power management circuit 14 or processor 10 by sending an interrupt signal INTR. Processor 10 can eventually detect the abnormal battery status, notify the ECU of vehicle 15 of the abnormal battery status via CAN within a predetermined time, or perform a safety response. When there is no abnormality in the battery, the battery management system 1 can return to sleep mode.

[0051] In low-power mode, BMICs 13a and 13b are woken up according to a preset measurement cycle (e.g., 1 to 32 seconds) to monitor parameters such as cell OT, UV, and ΔT. When an anomaly is detected, processor 10 is woken up to take safety measures before an accident such as thermal runaway or heat propagation occurs. The measurement cycle of BMICs 13a and 13b can be set via software register settings, and the measurement cycle of transceiver 11 can be set without using registers by using an overload resistance (RTO) resistor. In this exemplary embodiment, the measurement cycle of BMICs 13a and 13b can be set in the range of 1 to 32 seconds, and the measurement cycle of transceiver 11 can be set to 48 seconds by using an 80.6 kΩ resistor at the RTO terminal.

[0052] Transceiver 11 can receive power through the VP and VDD terminals. The power supplied to the VP terminal can be a constant power supply PWR_12V for operation even in low-power mode, and the power supplied to the VDD terminal can be a power supply VAUX_5V for communication. Furthermore, transceiver 11 may include an XCVRMD terminal. A 20 kΩ resistor can be connected to the XCVRMD terminal when using low-power mode, and a 0 kΩ resistor can be connected to the XCVRMD terminal when not using low-power mode. Additionally, transceiver 11 may include an MSTR terminal. The MSTR terminal can be connected to the GPIO terminal of processor 10. The output from the GPIO terminal of processor 10 can indicate whether processor 10 is in normal operation or in low-power mode.

[0053] Processor 10 may include a VDDS_PowerControl terminal. The VDDS_PowerControl terminal outputs a signal for controlling transistor T1, and by controlling transistor T1, a power supply VDDS can be selectively provided to determine low-power mode operation. One end of transistor T1 can be connected to ground, and the other end of transistor T1 can be correlated with the VDDS signal level. When transistor T1 is turned on, the voltage level of the VDDS signal can transition to ground. When the voltage level of the VDDS signal transitions, the XCVRMD signal of transceiver 11 can be detected. Furthermore, processor 10 may include an XCVRMD_Control terminal. The XCVRMD_Control terminal outputs a signal for controlling transistor T2, and by controlling transistor T2, the XCVRMD terminal can be connected to a 20 kΩ resistor or a 0 kΩ resistor.

[0054] The following section describes a detailed method for controlling a situation where the battery management system is unable to enter a low-power mode due to an unexpected malfunction, based on the circuit configuration of the battery management system described above.

[0055] Figure 2 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment.

[0056] Reference Figure 2 The timing diagram shows the operation of the battery management system 1 when no low-power mode fault occurs.

[0057] In the first section I, a constant 12 V power supply can be applied to the VP terminal of the processor 10, and 5 V and 5 V can be applied to the VDD and VDDS terminals respectively. The XCVRMD terminal of the transceiver 11 is configured to use a low-power mode when connected to a 20 kΩ resistor, and the RTO terminal of the transceiver 11 is configured to read data in 48-second increments when connected to an 80.6 kΩ resistor.

[0058] The MSTR terminal of transceiver 11 can initially have a first voltage level (e.g., a 5 V voltage level), and the INTR terminal can initially have a second voltage level (e.g., a 0 V voltage level). Transceiver 11, indicated by "IC_6822", BMICs 13a and 13b, indicated by "BMIC_6830", and processor 10, indicated by "MCU_5777C", can perform normal operation. Here, normal operation can mean operation in a drive mode that executes logic configured to check battery status and safely operate the battery.

[0059] E21 indicates the time point at which a low-power mode entry command occurs in the main BMS. At time point E21, the signal at the MSTR terminal of transceiver 11 can transition from a first voltage level to a second voltage level. Simultaneously, the signal at the INTR terminal of transceiver 11 can transition from the second voltage level back to the first voltage level.

[0060] E22 indicates the time point at which the master BMS normally acknowledges the low-power mode-related communication messages received from the slave BMS. Specifically, after the low-power mode entry command is sent from the processor 10 to the transceiver 11, the slave BMS, including BMICs 13a and 13b, can send a normal acknowledgment message to the master BMS indicating that the low-power mode-related communication messages have been normally acknowledged. At time E22, the signal at the INTR terminal of the transceiver 11 can transition from a first voltage level to a second voltage level. Subsequently, the battery management system 1 can enter low-power mode.

[0061] In the second section II, no voltage needs to be applied to the VDD and VDDS terminals of processor 10. The signals at the MSTR and INTR terminals of transceiver 11 can maintain the second voltage level. Furthermore, transceiver 11, indicated by "IC_6822", can wake up every 32 seconds when operating in low-power mode, and BMICs 13a and 13b, indicated by "BMIC_6830", can wake up every 1 second when operating in low-power mode. Processor 10, indicated by "MCU_5777C", can remain in sleep mode.

[0062] In the third segment III, when no foreseeable anomaly is identified that poses a risk of battery fire—that is, when no fault occurs in low-power mode—the voltage is maintained without applying voltage to the VDD and VDDS terminals of processor 10, and the signals at the MSTR and INTR terminals of transceiver 11 can be maintained at the second voltage level. Furthermore, transceiver 11 can wake up every 32 seconds when operating in low-power mode, BMICs 13a and 13b can wake up every 1 second, and processor 10 can continue to remain in sleep mode.

[0063] In the fourth segment IV, E23 indicates the time point at which a wake-up occurs due to factors or causes other than a low-power mode fault. At E23, a 5V voltage can be applied again to the VDD and VDDS terminals of processor 10. Since the signal at the MSTR terminal of transceiver 11 transitions from the second voltage level to the first voltage level, and no low-power mode fault occurred, the signal at the INTR terminal of transceiver 11 can remain at the second voltage level as is. Furthermore, transceiver 11, indicated by "IC_6822", BMICs 13a and 13b, indicated by "BMIC_6830", and processor 10, indicated by "MCU_5777C", can resume normal operation.

[0064] Figure 3 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment.

[0065] Reference Figure 3 The timing diagram shows the operation of the battery management system 1 when a low-power mode fault (i.e., the expected fault) occurs.

[0066] In the first segment I, E31 can indicate the time point when a low-power mode entry command occurs in the primary BMS, and E32 can indicate the time point when the primary BMS normally acknowledges the low-power mode-related communication messages received from the secondary BMS. That is, E31 and E32 can be used in conjunction with... Figure 2 E21 and E22 correspond to each other. The operation of the battery management system 1 in the first segment I can be synchronized with that in Figure 2 The operation of the battery management system 1 in the first section I is the same. The operation of the second section II is also the same. Figure 2 The second section II is the same, so its redundant description will be omitted.

[0067] In section III, E33 indicates the time point at which a wake-up occurs due to a low-power mode fault. A low-power mode fault can indicate a situation where action needs to be taken before a battery fire occurs due to anomalies in parameter values ​​such as cell OT, UV, and ΔT. Because a low-power mode fault occurs in E33, the signal at the INTR terminal of transceiver 11 can transition from a second voltage level to a first voltage level. Processor 10, transceiver 11, and BMICs 13a and 13b may be woken up by an interrupt signal generated in this manner.

[0068] In other words, transceiver 11, indicated by "IC_6822", BMICs 13a and 13b, indicated by "BMIC_6830", and processor 10, indicated by "MCU_5777C", can resume normal operation and a 5V voltage can be applied to the VDD and VDDS terminals of processor 10 again. Furthermore, the signal at the MSTR terminal of transceiver 11 can be switched from the second voltage level to the first voltage level. Additionally, the signal at the INTR terminal of transceiver 11 can be switched from the first voltage level to the second voltage level again.

[0069] Figure 4 It is a timing diagram used to illustrate a situation where low-power mode entry is not allowed due to an unexpected fault.

[0070] Reference Figure 4 The timing diagram shows the operation of the battery management system 1 when a non-low power mode fault (i.e., an unexpected fault) occurs.

[0071] In the first segment I, E41 can indicate the time point when a low-power mode entry command occurs in the primary BMS, and E42 can indicate the time point when the primary BMS normally acknowledges the low-power mode-related communication messages received from the secondary BMS. That is, E41 and E42 can be used in conjunction with... Figure 3 E31 and E32 correspond to each other. The operation of the battery management system 1 in the first segment I can be synchronized with that in Figure 3 The operation of the battery management system 1 in the first section I is the same. The operation of the second section II is also the same. Figure 3 The second section II is the same, so its redundant description will be omitted.

[0072] In section III, E43 indicates the time point at which a wake-up occurs due to an unexpected fault. An unexpected fault can indicate abnormal parameter values, such as communication loss or connector damage. Because an unexpected fault occurs in E43, the signal at the INTR terminal of transceiver 11 can transition from a second voltage level to a first voltage level. Processor 10, transceiver 11, and BMICs 13a and 13b may be woken up by an interrupt signal generated in this manner.

[0073] In other words, transceiver 11, indicated by "IC_6822", BMICs 13a and 13b, indicated by "BMIC_6830", and processor 10, indicated by "MCU_5777C", can resume normal operation and a 5V voltage can be applied to the VDD and VDDS terminals of processor 10 again. Furthermore, the signal at the MSTR terminal of transceiver 11 can be switched from the second voltage level to the first voltage level. Additionally, the signal at the INTR terminal of transceiver 11 can be switched from the first voltage level to the second voltage level again.

[0074] E44 indicates the time point at which a low-power mode entry command occurs in the main BMS. At time E44, the signal at the MSTR terminal of transceiver 11 can transition from a first voltage level to a second voltage level. Since no low-power mode fault has occurred, the low-power mode entry command of the main BMS occurs, and therefore the battery management system 1 needs to re-enter low-power mode. However, if the unexpected fault is not resolved, the signal at the INTR terminal of transceiver 11 can again transition from the second voltage level to the first voltage level.

[0075] Therefore, in segment IV, transceiver 11 indicated by "IC_6822", BMICs 13a and 13b indicated by "BMIC_6830", and processor 10 indicated by "MCU_5777C" may fail to enter low-power mode. Subsequently, even if the low-power mode entry command occurs again in the main BMS in E46, in segment V, as shown in E47, transceiver 11 indicated by "IC_6822", BMICs 13a and 13b indicated by "BMIC_6830", and processor 10 indicated by "MCU_5777C" may still fail to enter low-power mode. (Refer to...) Figure 5 To describe a method to improve this problem.

[0076] Figure 5 This is a timing diagram used to illustrate the operation of a battery management system according to an exemplary embodiment.

[0077] Reference Figure 5The timing diagram shows the operation of the battery management system 1 when a non-low power mode fault (i.e., an unexpected fault) occurs.

[0078] and Figure 4 The timing diagram differs in that it additionally shows the VDDS_PowerControl and XCVRMD_Control signals. See also... Figure 1 The VDDS_PowerControl terminal is the output of processor 10 used to control the signal of transistor T1, and the XCVRMD_Control terminal is the output of processor 10 used to control the signal of transistor T2. By controlling transistor T1 via the VDDS_PowerControl signal, the power supply VDDS for determining low-power mode operation can be selectively provided, and by controlling transistor T2 via the XCVRMD_Control signal, the XCVRMD terminal can be connected to a 20 kΩ resistor or a 0 kΩ resistor.

[0079] In the first segment I and the second segment II, except for the VDDS_PowerControl and XCVRMD_Control signals which are both set to the off state, the remaining signals can be used in conjunction with... Figure 4 It operates in the same way as the first section I and the second section II. Therefore, redundant descriptions are omitted.

[0080] In section III, E51 indicates the time point at which a wake-up occurs due to an unexpected fault. An unexpected fault can indicate abnormal parameter values, such as communication loss or connector damage. Because an unexpected fault occurs in E51, the signal at the INTR terminal of transceiver 11 can transition from a second voltage level to a first voltage level. Processor 10, transceiver 11, and BMICs 13a and 13b may be woken up by an interrupt signal generated in this manner.

[0081] Next, E52 indicates when the low-power mode function will begin to switch to the off state to eliminate abnormal low-power mode operation. Specifically, in E52, the XCVRMD_Control signal can transition from the off state to the on state. Therefore, the XCVRMD terminal can be changed to a 0 kΩ connection state.

[0082] Subsequently, in segment IV, when the XCVRMD terminal indicates that the low-power mode is off, the VDDS_PowerControl signal can transition from the off state to the on state. Therefore, voltage can be removed from the VDDS terminal. Next, when the VDDS_PowerControl signal transitions from the on state to the off state, voltage can be applied to the VDDS terminal again. When voltage is applied to the VDDS signal, the value of the XCVRMD terminal can be captured, and the battery management system 1 can be set to not use the low-power mode based on the captured value. Subsequently, the XCVRMD_Control signal returns from the on state to the off state, thus the XCVRMD terminal can be switched to a 20 kΩ connection state.

[0083] Now, in the fifth segment, a low-power mode entry command occurs in the main BMS, and therefore, the signal at the MSTR terminal of transceiver 11 can be switched from a first voltage level to a second voltage level. Furthermore, transceiver 11, indicated by "IC_6822", BMICs 13a and 13b, indicated by "BMIC_6830", and processor 10, indicated by "MCU_5777C", can re-enter low-power mode.

[0084] According to an exemplary embodiment, even when the BMS is in sleep mode, thermal runaway of the battery can be accurately diagnosed to reduce personal injury and property damage. Specifically, it addresses the problem that the battery management system, after being awakened from low-power mode due to unexpected faults such as communication loss and connector damage rather than changes in cell voltage and temperature, cannot re-enter sleep mode. Furthermore, by resolving this issue, it prevents the vehicle's lead-acid battery from being discharged due to its inability to enter sleep mode.

[0085] Although the invention has been described in conjunction with embodiments which are now considered practical and exemplary, it should be understood that the invention is not limited to the disclosed exemplary embodiments.

Claims

1. A battery management system, the battery management system comprising: The battery monitoring IC, or BMIC, is used to measure the state of the battery. A processor, the processor being used to control the overall operation of the battery management system; A transceiver, the transceiver being used to identify the measured state of the battery and transmit the identified state of the battery to the processor; as well as A power management circuit, which provides power to the processor, The processor includes a first terminal that outputs a first signal to control a first transistor, and provides a power signal for determining operation in a low-power mode by controlling the first transistor using the first signal.

2. The battery management system according to claim 1, wherein, The processor also includes a second terminal that outputs a second signal for controlling the second transistor, and uses the second signal to control the second transistor to change the resistance value connected to a third terminal indicating whether the low-power mode is used.

3. The battery management system according to claim 2, wherein, When the voltage level of the power supply signal changes, the value of the signal at the third terminal is detected.

4. The battery management system according to claim 2, wherein, In the event of an unexpected malfunction, the signal at the fourth terminal of the transceiver changes from the second voltage level to the first voltage level, and The processor, the transceiver, and the BMIC are woken up.

5. The battery management system according to claim 4, wherein, After the processor, the transceiver, and the BMIC are woken up, the second signal output from the second terminal changes from the off state to the on state, and The resistance value connected to the third terminal is changed to a state where it is connected to 0 kΩ.

6. The battery management system according to claim 5, wherein, When the resistance value connected to the third terminal is 0 kΩ, the first signal output from the first terminal changes from the off state to the on state, and It was changed so that no voltage was applied to the power supply terminals.

7. The battery management system according to claim 6, wherein, The first signal output from the first terminal changes from the on state to the off state. Apply voltage to the power supply terminal again. When voltage is applied to the power supply terminal again, the value of the third terminal is captured, and The battery management system is set to not use the low-power mode based on the captured value.

8. The battery management system according to claim 7, wherein, The second signal output from the second terminal returns from the on state to the off state again, and The resistance value connected to the third terminal is changed to a state where it is connected to 20 kΩ.

9. The battery management system according to claim 8, wherein, When a low-power mode entry command is received, the signal at the fifth terminal of the transceiver changes from a first voltage level to a second voltage level. The fifth terminal provides an output indicating whether the processor is in normal operation or low-power mode entry state. The processor, the transceiver, and the BMIC re-enter the low-power mode.

10. A battery management method performed by a battery management system, the battery management system comprising: The battery monitoring IC, or BMIC, is used to measure the state of the battery. A processor for controlling the overall operation of the battery management system, and including a first terminal for outputting a first signal controlling a first transistor and a second terminal for outputting a second signal controlling a second transistor; A transceiver, the transceiver being used to identify the measured state of the battery and transmit the identified state of the battery to the processor; as well as A power management circuit is used to provide power to the processor, and the battery management method includes the following steps: The processor provides a power signal for determining operation in a low-power mode by controlling the first transistor using the first signal. as well as The second transistor is controlled by the second signal to change the resistance value connected to the third terminal indicating whether the low-power mode is used.

11. The battery management method according to claim 10, wherein, When the voltage level of the power supply signal changes, the value of the signal at the third terminal is detected.

12. The battery management method according to claim 10, further comprising the following steps: In the event of an unexpected malfunction, the signal at the fourth terminal of the transceiver will be switched from the second voltage level to the first voltage level. as well as Wake up the processor, the transceiver, and the BMIC.

13. The battery management method according to claim 12, further comprising the following steps: After the processor, the transceiver, and the BMIC are woken up, the second signal output from the second terminal will change from the off state to the on state. as well as Change the resistance value connected to the third terminal to a state where it is connected to 0 kΩ.

14. The battery management method according to claim 13, further comprising the following steps: When the resistance value connected to the third terminal is in the state of 0 kΩ, the first signal output from the first terminal will change from the cut-off state to the conduction state. as well as The change is made so that no voltage is applied to the power supply terminals.

15. The battery management method according to claim 14, further comprising the following steps: The first signal output from the first terminal will change from the on state to the off state; Apply voltage to the power supply terminal again; When voltage is applied to the power supply terminal again, the value of the third terminal is captured; as well as The battery management system is set to not use the low-power mode based on the captured value.

16. The battery management method according to claim 15, further comprising the following steps: The second signal output from the second terminal will return from the on state to the off state again; as well as Change the resistance value connected to the third terminal to 20 kΩ.

17. The battery management method according to claim 16, further comprising the following steps: When a low-power mode entry command is received, the signal at the fifth terminal of the transceiver is switched from a first voltage level to a second voltage level. The fifth terminal provides an output indicating whether the processor is in normal operation or low-power mode entry state. as well as The processor, the transceiver, and the BMIC are then brought back into the low-power mode.

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