Performance-based cache adjustment

Abstract

An apparatus includes a system cache accessible by a central processing unit (CPU) subsystem. The system cache includes a CPU portion allocated to the CPU subsystem. The apparatus also includes a cache allocation regulator configured to obtain a performance metric associated with at least one of the system cache or the CPU subsystem. The cache allocation regulator is further configured to resize the CPU portion based on the performance metric satisfying a cache adjustment criterion.

Description

Cross-reference to related applications

[0001] This application claims priority to jointly owned U.S. non-provisional patent application No. 18 / 466,171, filed on September 13, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to performance-based cache tuning. Related technical descriptions

[0003] Technological advancements have led to smaller and more powerful computing devices. For example, a wide variety of portable personal computing devices exist today, including small, lightweight, and easily portable cordless phones (such as mobile and smartphones, tablets, and laptops). These devices can transmit voice and data packets over wireless networks. Furthermore, many of these devices incorporate additional functionality, such as digital still cameras, digital camcorders, digital recorders, and audio file players. Moreover, such devices can process executable instructions, including software applications such as web browser applications that can be used to access the internet. Accordingly, these devices can include significant computing power.

[0004] Such computing devices typically include a system cache shared by multiple device components. For example, one portion of the system cache might be assigned to the central processing unit (CPU), another portion to the camera, yet another portion to the audio processor, and so on. A smaller CPU portion of the system cache can result in more cache misses. However, indiscriminately increasing the size of this CPU portion can reduce the space in the system cache available for allocation to other components. Summary of the Invention

[0005] According to one embodiment of this disclosure, an apparatus includes a system cache accessible by a central processing unit (CPU) subsystem. The system cache includes a CPU portion allocated to the CPU subsystem. The apparatus also includes a cache allocation regulator configured to obtain a performance metric associated with at least one of the system cache or the CPU subsystem. The cache allocation regulator is further configured to adjust the size of the CPU portion based on whether the performance metric meets cache adjustment criteria.

[0006] According to another embodiment of this disclosure, a method includes obtaining at a device a performance metric associated with at least one of the device's system cache or central processing unit (CPU) subsystem. The method further includes adjusting the size of a CPU portion in the system cache based on determining that the performance metric meets cache tuning criteria. This CPU portion is allocated to the CPU subsystem.

[0007] According to another embodiment of this disclosure, a non-transitory computer-readable medium storage instruction, when executed by one or more processors, causes the one or more processors to: obtain a performance metric associated with at least one of a system cache or a central processing unit (CPU) subsystem. The instructions also cause the one or more processors to: adjust the size of a CPU portion in the system cache based on determining that the performance metric meets a cache tuning criterion. This CPU portion is allocated to the CPU subsystem.

[0008] According to another embodiment of this disclosure, an apparatus includes: components for obtaining a performance metric associated with at least one of a system cache or a central processing unit (CPU) subsystem. The apparatus further includes: components for adjusting the size of a CPU portion in the system cache. This size is adjusted based on determining that the performance metric meets cache adjustment criteria. The CPU portion is allocated to the CPU subsystem.

[0009] Other aspects, advantages, and features of this disclosure will become apparent upon reading the entire application, which comprises the following sections: description of the drawings, detailed description, and claims. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating specific exemplary aspects of a system operable to perform performance-based cache tuning, based on some examples of this disclosure.

[0011] Figure 2 Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates the illustrative aspects of the operations performed by the system.

[0012] Figure 3 Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates the illustrative aspects of the operations performed by the system.

[0013] Figure 4A Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates the illustrative aspects of the operations performed by the system.

[0014] Figure 4B Based on some examples of this disclosure, it is possible to... Figure 1The diagram illustrates the illustrative aspects of the operations performed by the system.

[0015] Figure 5 Based on some examples of this disclosure, it is possible to... Figure 1 A diagram illustrating a specific implementation of a performance-based cache tuning method performed by the system. Detailed Implementation

[0016] Typically, devices include a system cache shared by multiple device subsystems. For example, a portion of the system cache might be allocated for the Central Processing Unit (CPU), another portion for the camera, yet another portion for the audio processor, and so on. A smaller CPU portion of the system cache can result in more cache misses. However, indiscriminately increasing the size of this CPU portion can reduce the space available in the system cache for other subsystems without a significant increase in CPU performance. In some cases, a larger CPU portion can reduce efficiency and increase data retrieval time.

[0017] Systems and methods for performance-based cache tuning are disclosed. For example, a device includes a system cache, a cache allocation tuner, and a performance monitoring unit (PMU). In some examples, the PMU includes a CPU PMU, a cache PMU, or both. The system cache includes a portion of the CPU allocated for use by the device's CPU.

[0018] The PMU monitors the performance of a device and generates performance metrics that indicate the device's performance during a sampling period (e.g., a monitoring time period). For example, the CPU PMU monitors the CPU's performance during the sampling period and generates a CPU performance metric (e.g., instruction count) that indicates the CPU's performance during the sampling period. As another example, the cache PMU monitors the performance of the system cache (e.g., a portion of the CPU) during the sampling period and generates a cache performance metric (e.g., MPKI count) that indicates the system cache's performance during the sampling period. The PMU generates performance metrics based on CPU performance metrics, cache performance metrics, or both.

[0019] The allocation regulator selects and executes an adjustment to the size of the CPU portion based on performance metrics. This adjustment may correspond to keeping the size of the CPU portion in the system cache unchanged, increasing its size, or decreasing its size. In some examples, this adjustment corresponds to reversing a previous adjustment. For example, in response to determining that a previous adjustment was to increase the size of the CPU portion by a first amount and that performance metrics indicate insufficient performance improvement during the sampling period, the allocation regulator reduces the size of the CPU portion by a first amount to reverse the first adjustment.

[0020] Reducing the size of the CPU portion may include freeing up one or more blocks of the system cache. In some examples, the device's cache controller may perform power degradation on one or more freed blocks to reduce the power consumption of the system cache. The technical advantages of performance-based cache tuning may include striking a balance between performance improvements and efficiently allocating space in the system cache for the device's subsystems.

[0021] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For example, Figure 1 It describes a system that includes one or more processors ( Figure 1 The device 102 (of which the “processor 190” is used) indicates that in some embodiments, device 102 includes a single processor 190, while in other embodiments, device 102 includes multiple processors 190. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect described relates to multiples of features.

[0022] As used herein, the term “comprise” may be used interchangeably with “include”. Additionally, the term “wherein” may be used interchangeably with “where”. As used herein, “exemplary” indicates an example, specific implementation, and / or aspect, and should not be construed as restrictive or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements (such as structures, components, operations, etc.) (e.g., “first,” “second,” “third,” etc.) do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using ordinal terms). As used herein, the term “set” refers to one or more specific elements within a set of specific elements, while the term “multiple” refers to multiple (e.g., two or more) specific elements.

[0023] As used herein, “coupling” can include “communicationally coupled,” “electrically coupled,” or “physically coupled,” and may also (or alternatively) include any combination thereof. Two devices (or components) may be coupled directly or indirectly (e.g., communicationally coupled, electrically coupled, or physically coupled) via one or more other devices, components, wires, buses, networks (e.g., wired networks, wireless networks, or combinations thereof). As an illustrative, non-limiting example, two electrically coupled devices (or components) may be included in the same device or in different devices and may be connected via electronics, one or more connectors, or inductive coupling. In some specific implementations, two communicationally coupled (such as electrical communication) devices (or components) may transmit and receive signals (e.g., digital or analog signals) directly or indirectly via one or more wires, buses, networks, etc. As used herein, “direct coupling” can include two devices coupled without intermediate components (e.g., communicationally coupled, electrically coupled, or physically coupled).

[0024] In this disclosure, terms such as “determine,” “calculate,” “estimate,” “shift,” and “adjust” can be used to describe how one or more operations are performed. It should be noted that such terms should not be construed as restrictive, and similar operations can be performed using other techniques. Additionally, as mentioned herein, “generate,” “calculate,” “estimate,” “use,” “select,” “access,” and “determine” can be used interchangeably. For example, “generating,” “calculating,” “estimate,” or “determining” a parameter (or signal) can refer to actively generating, estimating, calculating, or determining that parameter (or signal), or it can refer to using, selecting, or accessing a parameter (or signal) that has already been generated (e.g., by another component or device).

[0025] refer to Figure 1 This document discloses specific exemplary aspects of a system configured to perform performance-based cache tuning, and designates it generally as 100. System 100 includes device 102, which includes a component 192 coupled to system cache 194. Device 102 also includes a cache allocation tuner 196 coupled to system cache 194 and to a performance monitoring unit (PMU) 118. PMU 118 includes a central processing unit (CPU) PMU 104, a cache PMU 106, or both. Device 102 includes a cache controller 198 coupled to system cache 194.

[0026] In the example, component 192 includes one or more processors 190, video component 140, camera 150, display 160, low-power audio subsystem 170, modem 180, one or more additional components, or combinations thereof. One or more processors 190 include CPU subsystem 109, computational digital signal processor (DSP) 120, graphics processing unit (GPU) 130, one or more additional processing components, or combinations thereof. In the example, CPU subsystem 109 includes one or more CPU clusters 110. For example, CPU cluster 110 includes multiple CPU cores. In another example, CPU subsystem 109 may include a single CPU core.

[0027] According to some specific implementations, one or more components in component 192 include one or more local caches. In the example, CPU subsystem 109 (e.g., each CPU cluster 110 or CPU core) includes one or more L1 caches 112, compute DSP 120 includes one or more L1 caches 122, GPU 130 includes one or more L1 caches 132, video component 140 includes one or more L1 caches 142, camera 150 includes one or more L1 caches 152, display 160 includes one or more L1 caches 162, low-power audio subsystem 170 includes one or more L1 caches 172, modem 180 includes one or more L1 caches 182, or combinations thereof.

[0028] In some implementations, one or more components in component 192 include hierarchical local caches. For example, CPU subsystem 109 (e.g., each CPU cluster 110 or CPU core) includes L2 cache 114, compute DSP 120 includes L2 cache 124, GPU 130 includes L2 cache 134, low-power audio subsystem 170 includes L2 cache 174, modem 180 includes L2 cache 184, or combinations thereof.

[0029] System cache 194 is configured to be accessible by one or more components in component 192. For example, system cache 194 corresponds to the last-level cache (LLC) for one or more components in component 192. Portions of system cache 194 may be allocated to specific components or subsystems of device 102. For example, CPU sub-cache 116, compute sub-cache 126, GPU sub-cache 136, video sub-cache 146, camera sub-cache 156, display sub-cache 166, audio sub-cache 176, and modem sub-cache 186 correspond to portions of system cache 194 allocated to CPU subsystem 109, compute DSP 120, GPU 130, video component 140, camera 150, display 160, low-power audio subsystem 170, and modem 180, respectively. A system cache 194, comprising CPU sub-cache 116, compute sub-cache 126, GPU sub-cache 136, video sub-cache 146, camera sub-cache 156, display sub-cache 166, audio sub-cache 176, and modem sub-cache 186, is provided as an illustrative example. In other examples, the system cache 194 may include fewer, more, or different sub-caches.

[0030] PMU 118 is configured to monitor the performance of device 102 during a sampling period and generate a performance metric 119 indicating the performance of device 102 during the sampling period. For example, CPU PMU 104 is configured to monitor the performance of CPU subsystem 109 and generate a CPU performance metric 105 indicating the performance of CPU subsystem 109 during the sampling period. As another example, cache PMU 106 is configured to monitor the performance of system cache 194 (e.g., CPU sub-cache 116) and generate a cache performance metric 107 indicating the performance of system cache 194 during the sampling period. PMU 118 is configured to generate the performance metric 119 for the sampling period based on the CPU performance metric 105, the cache performance metric 107, or both.

[0031] Cache allocation regulator 196 is configured to selectively adjust the size of CPU sub-cache 116 based on determining that performance metric 119 meets cache adjustment criteria. For example, cache allocation regulator 196 is configured to decrease the size of CPU sub-cache 116 based on determining that performance metric 119 meets cache reduction criteria 191. As another example, cache allocation regulator 196 is configured to increase the size of CPU sub-cache 116 based on determining that performance metric 119 meets cache expansion criteria 193. In yet another example, cache allocation regulator 196 is configured to avoid changing the size of CPU sub-cache 116 based on determining that performance metric 119 fails to meet either cache expansion criteria 193 or cache reduction criteria 191.

[0032] In some implementations, cache allocation regulator 196 (or another component of device 102, such as a memory manager) is configured to deallocate one or more blocks (e.g., memory regions) of system cache 194 that are no longer assigned to CPU subsystem 109 when the size of CPU sub-cache 116 is reduced by cache allocation regulator 196. In some implementations of these implementations, cache controller 198 is configured to perform power degradation on the deallocated blocks to conserve power at device 102.

[0033] In some specific implementations, device 102 corresponds to or is included in one of a variety of types of devices. In exemplary examples, component 192, system cache 194, cache allocation regulator 196, PMU 118, cache controller 198, or combinations thereof are integrated into a head-mounted device, mobile phone, tablet computer device, wearable electronic device, voice-controlled speaker system, camera device, virtual reality head-mounted device, mixed reality head-mounted device, augmented reality head-mounted device, extended reality head-mounted device, vehicle, smart speaker, soundbar, mobile communication device, smartphone, cellular phone, laptop computer, computer, tablet computer, personal digital assistant, display device, television, game console, music player, radio, digital video player, digital video disc (DVD) player, tuner, navigation device, head-mounted device, aircraft, home automation system, voice-activated device, wireless speaker and voice-activated device, portable electronic device, automobile, computing device, communication device, Internet of Things (IoT) device, virtual reality (VR) device, base station, mobile device, or any combination thereof.

[0034] In some embodiments, device 102 includes a memory (e.g., a non-transitory storage medium) storing instructions that can be executed by one or more processors to implement the functionality described by reference cache allocation regulator 196, PMU 118, CPU PMU 104, cache PMU 106, cache controller 198, or combinations thereof. In certain embodiments, device 102 may be included in a system-in-package or system-on-a-chip device.

[0035] During operation, PMU 118 monitors the performance of device 102 during a first sampling period (e.g., a first time period) and generates a performance metric 119 indicating the performance of device 102 during the first sampling period. For example, CPU PMU 104 monitors the performance of CPU subsystem 109 during the first sampling period and generates a CPU performance metric 105 indicating the performance of CPU subsystem 109 during the first sampling period. For instance, CPU performance metric 105 indicates the count of instructions executed (e.g., implemented) at CPU subsystem 109 during the first sampling period.

[0036] In the example, cache PMU 106 monitors the performance of system cache 194 (e.g., CPU sub-cache 116) during the first sampling period and generates a cache performance metric 107 indicating the performance of system cache 194 during the first sampling period. For example, cache performance metric 107 indicates the hit count, miss count, memory access count, bus bandwidth, memory bandwidth, allocated block count, unallocated block count, active block count, or a combination thereof during the first sampling period.

[0037] In certain aspects, performance metric 119 is based on CPU performance metric 105, cache performance metric 107, or both. Depending on some specific implementations, performance metric 119 includes at least one of the following: MPKI (Millions of Instructions Missed), miss rate, CPI (Cycles Per Instruction), branch misprediction count, or active core count.

[0038] In the example, CPU performance metric 105 indicates CPI, where CPI = clock cycle count / instruction count. In the example, CPU performance metric 105 indicates the active core count. In the example, cache performance metric 107 indicates the branch misprediction count.

[0039] In the example, performance metric 119 includes MPKI, where MPKI = miss count / (instruction count / 1000), cache performance metric 107 indicates the miss count, and CPU performance metric 105 indicates the instruction count. In the example, performance metric 119 includes the miss rate, where the miss rate = miss count / instruction count, cache performance metric 107 indicates the miss count, and CPU performance metric 105 indicates the instruction count.

[0040] The cache allocation regulator 196 selectively adjusts the size of the CPU sub-cache 116 based on performance metrics 119, as referenced. Figures 2 to 4B Further described. For example, in response to determining that performance metric 119 meets cache reduction criterion 191, cache allocation regulator 196 reduces the size of CPU sub-cache 116. In another example, in response to determining that performance metric 119 meets cache expansion criterion 193, cache allocation regulator 196 increases the size of CPU sub-cache 116. Alternatively, in response to determining that performance metric 119 does not meet either cache reduction criterion 191 or cache expansion criterion 193, cache allocation regulator 196 avoids adjusting the size of CPU sub-cache 116.

[0041] In some implementations, when the cache allocation regulator 196 reduces the size of the CPU sub-cache 116, the cache allocation regulator 196 (or memory manager) reallocates one or more blocks of the system cache 194 previously assigned to the CPU sub-cache 116. In some of these implementations, the cache controller 198 performs power degradation on the reallocated one or more blocks to conserve power at the system cache 194.

[0042] Therefore, system 100 enables the size of CPU sub-cache 116 to be dynamically adjusted based on performance metric 119. The technical advantages of dynamic resizing may include achieving a balance between improved performance (e.g., lower MPKI) due to the increase in the size of CPU sub-cache 116 and reduced power consumption (e.g., through power degradation of deallocated blocks).

[0043] refer to Figure 2 This illustrates some examples of what can be achieved according to this disclosure. Figure 1 The diagram 200 illustrates an exemplary aspect of the operations performed by the system 100. In a particular aspect, one or more operations of the diagram 200 may be performed by the PMU 118, the CPU PMU 104, the cache PMU 106, the cache allocation regulator 196, or a combination thereof.

[0044] Figure 200 illustrates examples of one or more operations performed during initialization phase 250 and examples of one or more operations performed during each sampling cycle phase 252 following initialization phase 250. During initialization phase 250, at box 202, cache allocation regulator 196 initializes the CPU sub-cache allocation (CSA). For example, cache allocation regulator 196 initializes CPU sub-cache 116 to have an initial size (e.g., 0). In some respects, the initial size is based on configuration settings, default data, user input, or a combination thereof.

[0045] At block 204, cache allocation regulator 196 obtains a performance metric 119 (e.g., MPKI) and the size of CPU sub-cache 116 during the initialization sampling period (t0). For example, cache allocation regulator 196 determines that CPU sub-cache 116 has an initial size (e.g., 0) during the initialization sampling period (t0) and obtains an initialization sampling period performance metric 119 (e.g., MPKI) from PMU 118 that indicates the performance of device 102 during the initialization sampling period (t0). In some specific implementations, a higher value of performance metric 119 indicates lower performance of device 102. At block 206, cache allocation regulator 196 increases the size of CPU sub-cache 116 (e.g., CSA) by a first amount (M).

[0046] During sampling period phase 252, at box 208, cache allocation regulator 196 obtains the Nth sampling period performance metric 119 (e.g., MPKI) and the Nth sampling period (t) N The size of the CPU sub-cache 116 is given by N, where N is a positive integer indicating the time position of a sampling period in the sampling period sequence. In the example, the cache allocation regulator 196 determines that the CPU sub-cache 116 has a first size (e.g., initial size + M) during the first sampling period (t1) after the initial sampling period (t0), and obtains a first sampling period performance metric 119 (e.g., MPKI) from the PMU 118, indicating the performance of the device 102 during the first sampling period (t1).

[0047] At box 210, cache allocation regulator 196 determines whether the Nth sampling period performance metric 119 is less than a first performance threshold (e.g., a low MPKI threshold). In the example, cache allocation regulator 196 determines whether the first sampling period performance metric 119 is less than a first performance threshold (e.g., a low MPKI threshold).

[0048] In some respects, one or more thresholds are used to compare with values ​​based on performance metric 119 to determine whether cache reduction criterion 191 or cache expansion criterion 193 is met. In some respects, these one or more thresholds are based on default data, configuration settings, user input, or a combination thereof.

[0049] At box 212, in response to determining that the Nth sample-cycle performance metric 119 is less than a first performance threshold (e.g., a low MPKI threshold), the cache allocation regulator 196 determines that the Nth sample-cycle performance metric 119 meets the cache reduction criterion 191 and reduces the size of the CPU sub-cache 116 by a first amount (M). In this example, the cache allocation regulator 196 determines that the first sample-cycle performance metric 119 meets the cache reduction criterion 191 based on detecting that the first sample-cycle performance metric 119 is less than the first performance threshold, and reverts the size of the CPU sub-cache 116 to its initial size.

[0050] In some respects, a performance metric 119 (e.g., MPKI) less than a first performance threshold indicates that device 102 in the Nth sampling period (t N The performance during this period is better than tolerable, and the cache allocation regulator 196 reduces the size of the CPU sub-cache 116 to test performance in subsequent sampling cycles (t). N+1 In this context, will the performance (and any resulting degradation) remain at a tolerable level?

[0051] Alternatively, in response to determining at block 210 that the performance metric 119 of the Nth sampling period is greater than or equal to a first performance threshold, the cache allocation regulator 196 determines at block 214 whether the difference in performance metric 119 is less than a second performance threshold (Y). In the example, the cache allocation regulator 196 is based on the performance metric 119 of the previous (N-1) sampling periods (e.g., MPKI). N-1 ) and the performance metric 119 for the Nth sampling period (e.g., MPKI) N By comparing (e.g., the absolute difference between them), the difference in performance metric 119 is determined (e.g., |MPKI) N-1 -MPKI N |). For example, the cache allocation regulator 196 determines the difference in performance metric 119 (e.g., |MPKI0-MPKI1|) based on a comparison (e.g., absolute difference) between the initial sampling cycle performance metric 119 and the first sampling cycle performance metric 119.

[0052] At box 216, in response to determining that the difference in performance metric 119 is less than a second performance threshold (Y), cache allocation regulator 196 determines that performance metric 119 in the Nth sampling cycle fails to meet each of cache reduction criterion 191 and cache expansion criterion 193, and avoids adjusting the size of CPU sub-cache 116. In the example, in response to determining that the change in performance metric 119 (e.g., |MPKI0-MPKI1|) is less than the second performance threshold (Y), cache allocation regulator 196 determines that performance metric 119 in the first sampling cycle fails to meet each of cache reduction criterion 191 and cache expansion criterion 193, and avoids adjusting the size of CPU sub-cache 116.

[0053] In some respects, the performance metric 119 for the Nth sampling period is less than that for the previous (N-1) sampling periods (e.g., MPKI). N <MPKI N-1 This indicates that the performance of device 102 has improved. In some of these aspects, a change in performance metric 119 (e.g., a decrease in MPKI) less than the second performance threshold (Y) (marked "Yes" at box 214) indicates that device 102 has improved in the Nth sampling period (t). N The performance improvement during the period is insufficient to increase the size of the CPU sub-cache 116, and the cache allocation regulator 196 prevents the increase of the size of the CPU sub-cache 116 if it does not detect sufficient performance benefits from the previous cache adjustment (e.g., previous increase).

[0054] In some respects, the performance metric 119 of the Nth sampling period is equal to the performance metric 119 of the previous (N-1) sampling periods (e.g., MPKI). N =MPKI N-1 This indicates that the performance of device 102 has not changed. In some of these aspects, a change in performance metric 119 (e.g., no MPKI change) less than the second performance threshold (Y) (marked "Yes" at box 214) indicates that device 102 has not changed in the Nth sampling period (t). N There is no performance benefit during this period, and the cache allocation regulator 196 prevents the size of the CPU sub-cache 116 from increasing.

[0055] In some respects, the performance metric 119 of the Nth sampling period is greater than that of the previous (N-1) sampling period (e.g., MPKI). N MPKI N-1This indicates a performance degradation in device 102. In these respects, a change in performance metric 119 (e.g., an increase in MPKI) less than the second performance threshold (Y) (“Yes” at box 214) indicates that the performance degradation is tolerable, and cache allocation regulator 196 prevents an increase in the size of CPU sub-cache 116.

[0056] Alternatively, at box 218, in response to determining the difference in performance metric 119 (e.g., |MPKI) N-1 -MPKI N If the performance metric 119 is greater than or equal to the second performance threshold (Y), the cache allocation regulator 196 determines that the performance metric 119 of the Nth sampling cycle meets the cache extension criterion 193, and increases the size of the CPU sub-cache 116 (CSA) by a first amount (M). In the example, in response to determining that the change in performance metric 119 (e.g., |MPKI0-MPKI1|) is greater than or equal to the second performance threshold (Y), the cache allocation regulator 196 determines that the performance metric 119 of the first sampling cycle meets the cache extension criterion 193, and increases the size of the CPU sub-cache 116 by a first amount (M).

[0057] In some respects, the performance metric 119 for the Nth sampling period is less than that for the previous (N-1) sampling periods (e.g., MPKI). N <MPKI N-1 This indicates that the performance of device 102 has improved. In some of these aspects, a difference in performance metric 119 (e.g., a reduction in MPKI) greater than or equal to a second performance threshold (Y) (“No” at box 214) indicates that device 102 has improved in the Nth sampling period (t). N The performance benefits during this period are large enough to increase the size of the CPU sub-cache by 116.

[0058] In some respects, the performance metric 119 of the Nth sampling period is greater than that of the previous (N-1) sampling period (e.g., MPKI). N MPKI N-1 This indicates a performance degradation in device 102. In some of these aspects, a difference in performance metric 119 (e.g., an increase in MPKI) greater than or equal to a second performance threshold (Y) indicates that the performance degradation is intolerable, and cache allocation regulator 196 increases the size of CPU sub-cache 116.

[0059] Therefore, the cache allocation regulator 196 can dynamically adjust the size of the CPU sub-cache 116 based on the performance metric 119 indicating the performance of the indicator device 102 during the sampling period. The technical advantages of dynamically changing the size of the CPU sub-cache 116 include: dynamically balancing performance and efficiency for varying CPU sub-cache usage.

[0060] It should be understood that MPKI is used as an illustrative example of performance metric 119, and in other examples, one or more other metrics may be used as performance metric 119 to determine whether cache reduction criterion 191 or cache expansion criterion 193 is met. Figures 2 to 4B An exemplary example of the operations for determining whether cache reduction criterion 191 or cache extension criterion 193 is met is provided. In other examples, cache allocation regulator 196 may perform one or more fewer, more, or different operations to determine whether cache reduction criterion 191 or cache extension criterion 193 is met.

[0061] refer to Figure 3 This illustrates some examples of what can be achieved according to this disclosure. Figure 1 The diagram 300 illustrates an exemplary aspect of the operations performed by the system 100. In a particular aspect, one or more operations of the diagram 300 may be performed by the PMU 118, the CPU PMU 104, the cache PMU 106, the cache allocation regulator 196, or a combination thereof.

[0062] Figure 300 illustrates another example of one or more operations that may be performed during each sampling period phase 252 after initialization phase 250. For example, in response to determining at box 210 that the performance metric 119 of the Nth sampling period is less than a first performance threshold (e.g., a low MPKI threshold), or determining at box 214 a change in the performance metric 119 (e.g., |MPKI) N-1 -MPKI N If the value is less than the second performance threshold (Y), the cache allocation regulator 196 determines the size of the CPU sub-cache 116 (CSA) during the Nth sampling period at box 302. N Is it smaller than the size of the CPU sub-cache 116 during the previous (N-1) sampling period (CSA)? N-1 For example, cache allocation regulator 196 determines the size of CPU sub-cache 116 in the previous (N-1) sampling cycles (t). N-1 ) and the Nth sampling period (t) N Whether the difference between ) decreases.

[0063] At box 304, in response to determining the size of CPU sub-cache 116 (CSA) during the Nth sampling period. NIt is smaller than the size of the CPU sub-cache 116 during the previous (N-1) sampling period (CSA). N-1 The cache allocation regulator 196 determines that the performance metric 119 of the Nth sampling cycle fails to meet each of the cache reduction criterion 191 and the cache expansion criterion 193, and avoids adjusting the size of the CPU sub-cache 116. For example, in response to determining that the size of the CPU sub-cache 116 has decreased (e.g., between the previous (N-1) sampling cycle and the Nth sampling cycle), the cache allocation regulator 196 avoids adjusting the size of the CPU sub-cache 116.

[0064] Alternatively, at box 306, in response to determining the size of CPU sub-cache 116 (CSA) during the Nth sampling period. N () is greater than or equal to the size of CPU sub-cache 116 during the previous (N-1) sampling period (CSA) N-1 The cache allocation regulator 196 determines that the performance metric 119 of the Nth sampling cycle meets the cache reduction criterion 191, and reduces the size of the CPU sub-cache 116 by a first amount (M). For example, in response to determining that the size of the CPU sub-cache 116 has not decreased (e.g., it remains unchanged or increases between the previous (N-1) sampling cycle and the Nth sampling cycle), the cache allocation regulator 196 reduces the size of the CPU sub-cache 116 by a first amount (M).

[0065] In some respects, the performance metric 119 for the Nth sampling period is less than a first performance threshold ("Yes" at box 210), indicating that device 102 in the Nth sampling period (t N The performance during this period is better than tolerable. In some of these aspects, if CPU sub-cache 116 is reduced after a previous (N-1) sampling cycle ("Yes" at box 302), the cache allocation regulator 196 avoids reduction during the Nth sampling cycle (t... N After that, the CPU sub-cache 116 is reduced (at box 304). For example, the cache allocation regulator 196 waits to look at the performance metric 119 (e.g., MPKI) for the next (N+1) sampling cycle. N+1 Whether the size of CPU sub-cache 116 remains below a first performance threshold (indicating that the performance improvement persists for at least two sampling cycles) to further reduce the size of CPU sub-cache 116. In some examples, any performance degradation that may have been caused by the previous reduction can be offset by a lower utilization rate of CPU sub-cache 116.

[0066] In some respects, the performance metric 119 for the Nth sampling period is less than that for the previous (N-1) sampling periods (e.g., MPKI). N <MPKI N-1This indicates an improvement in the performance of device 102. In some of these aspects, the previous reduction in the size of CPU sub-cache 116 (e.g., CSA) contributes to this improvement. N <CSA N-1 After (Yes at box 302), if the difference in performance metric 119 (e.g., a reduction in MPKI) is less than the second performance threshold (Y) (Yes at box 214), it indicates that performance has improved after the previous reduction, and cache allocation regulator 196 avoids further reducing the CPU sub-cache 116 after the Nth sampling period (at box 304). For example, cache allocation regulator 196 waits to see if performance metric 119 has further improved in the next (N+1) sampling period (indicating that the performance improvement has continued for at least two sampling periods) before further reducing the size of CPU sub-cache 116.

[0067] Alternatively, in some of these aspects, the previous increase in the size of the CPU sub-cache 116 (e.g., CSA) N CSA N-1 ) or no change (e.g., CSA) N =CSA N-1 After (No at box 302), if the difference in performance metric 119 (e.g., a reduction in MPKI) is less than the second performance threshold (Y) (Yes at box 214), it indicates insufficient performance improvement, and cache allocation regulator 196 reduces the size of CPU sub-cache 116 by a first amount (M) (at box 306). In this example, cache allocation regulator 196 reduces the size of CPU sub-cache 116 by a first amount (M) to reverse a previous increase in the size of CPU sub-cache 116.

[0068] In some respects, the performance metric 119 of the Nth sampling period is equal to the performance metric 119 of the previous (N-1) sampling periods (e.g., MPKI). N =MPKI N-1 This indicates that the performance of device 102 has not changed. In some of these aspects, the previous reduction in the size of CPU sub-cache 116 (e.g., CSA)... N <CSA N-1 After (Yes at box 302), if the difference in performance metric 119 (e.g., no MPKI change) is less than the second performance threshold (Y) (Yes at box 214), it indicates that the performance remains the same after the previous reduction, and the cache allocation regulator 196 determines that the previous reduction will not be reversed and avoids adjusting the size of the CPU sub-cache 116.

[0069] Alternatively, the size of the CPU sub-cache 116 is increased previously (e.g., CSA).N CSA N-1 ) or no change (e.g., CSA) N =CSA N-1 After (No at box 302), if the difference in performance metric 119 (e.g., no MPKI change) is less than the second performance threshold (Y) (Yes at box 214), it indicates that there has been no change in performance, and cache allocation regulator 196 reduces the size of CPU sub-cache 116 by a first amount (M) (at box 306). In this example, cache allocation regulator 196 reduces the size of CPU sub-cache 116 to reverse a previous increase in the size of CPU sub-cache 116.

[0070] In some respects, the performance metric 119 of the Nth sampling period is greater than that of the previous (N-1) sampling period (e.g., MPKI). N MPKI N-1 This indicates a performance degradation in device 102. Some of these degradations are due to the previous reduction in the size of the CPU sub-cache 116 (e.g., CSA). N <CSA N-1 After (Yes at box 302), if the difference in performance metric 119 (e.g., an increase in MPKI) is less than the second performance threshold (Y) (Yes at box 214), it indicates that the previous reduction caused a tolerable performance degradation, and the cache allocation regulator 196 does not reverse the previous reduction and avoids adjusting the size of the CPU sub-cache 116.

[0071] Alternatively, in some of these aspects, the previous increase in the size of the CPU sub-cache 116 (e.g., CSA) N CSA N-1 ) or no change (e.g., CSA) N =CSA N-1 After (No at box 302), if the difference in performance metric 119 (e.g., an increase in MPKI) is less than the second performance threshold (Y) (Yes at box 214), it indicates a performance degradation, and cache allocation regulator 196 reduces the size of CPU sub-cache 116 (at box 306). In some examples, in response to detecting a performance degradation, cache allocation regulator 196 reduces the size of CPU sub-cache 116 to reverse a previous increase.

[0072] In response to the change in performance metric 119 determined at box 214 (e.g., |MPKI) N-1 -MPKI NIf |) is greater than or equal to the second performance threshold (Y), the cache allocation regulator 196 determines the size of the CPU sub-cache 116 (CSA) during the Nth sampling period at box 308. N Whether it is less than the maximum capacity. In the example, in response to determining that the system cache 194 has available space that can be allocated to the CPU sub-cache 116, the cache allocation regulator 196 determines the size of the CPU sub-cache 116 (CSA). N () is less than the maximum capacity.

[0073] At box 310, in response to determining the size of CPU sub-cache 116 (CSA) N If the capacity is less than the maximum capacity, the cache allocation regulator 196 determines that the performance metric 119 of the Nth sampling cycle meets the cache extension criterion 193, and increases the size of the CPU sub-cache 116 by a first amount (M).

[0074] Alternatively, at box 312, in response to determining CPU sub-cache 116 (CSA) N If the cache allocation regulator 196 is at maximum capacity, it determines that the performance metric 119 of the Nth sampling cycle fails to meet the cache expansion standard 193 and avoids adjusting the size of the CPU sub-cache 116.

[0075] In some respects, the performance metric 119 for the Nth sampling period is less than that for the previous (N-1) sampling periods (e.g., MPKI). N <MPKI N-1 This indicates that the performance of device 102 has improved. In some of these aspects, a difference in performance metric 119 (e.g., a reduction in MPKI) greater than or equal to a second performance threshold (Y) (“No” at box 214) indicates that the performance has improved sufficiently to correspond to any previous adjustments, and if the size of CPU sub-cache 116 has not yet reached its maximum capacity, cache allocation regulator 196 increases the size of CPU sub-cache 116 to further improve performance.

[0076] In some respects, the performance metric 119 of the Nth sampling period is greater than that of the previous (N-1) sampling period (e.g., MPKI). N MPKI N-1 This indicates a performance degradation in device 102. In some of these aspects, a difference in performance metric 119 (e.g., an increase in MPKI) greater than or equal to a second performance threshold (Y) (“No” at box 214) indicates that the performance degradation is intolerable, and if the size of CPU sub-cache 116 has not yet reached its maximum capacity, cache allocation regulator 196 increases the size of CPU sub-cache 116 to improve performance.

[0077] Therefore, the cache allocation regulator 196 can dynamically adjust the size of the CPU sub-cache 116 based on the performance metric 119 indicating the performance of the indicator device 102 during a sampling period. The technical advantages of dynamically changing the size of the CPU sub-cache 116 include: dynamically balancing performance and efficiency for varying CPU sub-cache usage. Adjusting based on whether the size of the CPU sub-cache 116 has been previously reduced allows the cache allocation regulator 196 to determine whether performance improvements are sustainable over multiple sampling periods before reducing the size of the CPU sub-cache 116.

[0078] refer to Figure 4A This illustrates some examples of what can be achieved according to this disclosure. Figure 1 The diagram 400 illustrates an exemplary aspect of the operations performed by the system 100. In a particular aspect, one or more operations of the diagram 400 may be performed by the PMU 118, the CPU PMU 104, the cache PMU 106, the cache allocation regulator 196, or a combination thereof.

[0079] Figure 400 illustrates another example of one or more operations that may be performed during each sampling period phase 252 after initialization phase 250. For example, in response to determining a change in performance metric 119 at box 214 (e.g., |MPKI) N-1 -MPKI N If the value is less than the second performance threshold (Y), the cache allocation regulator 196 determines the size of the CPU sub-cache 116 (CSA) at box 402. N Whether it is less than the maximum capacity and less than a specific size threshold. In some respects, this specific size threshold is based on the second highest specific size among a plurality of specific sizes (e.g., the second specific size (S2)), as referenced. Figure 4B Further description.

[0080] In response to determining the size of CPU sub-cache 116 (CSA) N The maximum capacity or a specific size threshold has been reached; cache allocation regulator 196 continues execution. Figure 3 Box 302 in the diagram describes one or more operations. For example, cache allocation regulator 196 determines whether the size of CPU sub-cache 116 should be reduced or kept unchanged. Alternatively, in response to determining the size of CPU sub-cache 116 (CSA... N If the cache size is less than the maximum capacity and less than the second specific size (S2), cache allocation regulator 196 continues to execute the reference. Figure 4BBox 404 in the diagram describes one or more operations. For example, cache allocation regulator 196 determines that cache expansion criterion 193 is met and increases the size of CPU sub-cache 116 to a selected specific size from a plurality of specific sizes. For instance, cache allocation regulator 196 tests whether increasing the size of one or more CPU sub-caches 116 provides an improved performance benefit due to at least one of a larger working set size or a non-linear sensitivity to cache size.

[0081] refer to Figure 4B An example of the operation corresponding to box 404 is illustrated. At box 406, cache allocation regulator 196 determines multiple sizes of CPU sub-cache 116. In some specific implementations, the multiple sizes include a first specific size (S1), a second specific size (S2), and a third specific size (S3). The first specific size (S1) is greater than the size of CPU sub-cache 116 during the Nth sampling period (CSA). N The second specific size (S2) is greater than the first specific size (S1), and the third specific size (S3) is greater than the second specific size (S2).

[0082] In some implementations, the cache allocation regulator 196 determines multiple sizes based on the space available in the system cache 194 for allocation to the CPU sub-cache 116. For example, a first specific size (S1) corresponds to the size of the CPU sub-cache 116 (CSA). N This is the sum of the first portion (e.g., 1 / 4) of the available space in the system cache 194. As another example, the second specific size (S2) corresponds to the size of the CPU sub-cache 116 (CSA). N This is the sum of the second portion (e.g., 1 / 2) of the available space in the system cache 194. As yet another example, the third specific size (S3) corresponds to the size of the CPU sub-cache 116 (CSA). N The sum of the third portion (e.g., 3 / 4) of the available space in the system cache 194. Multiple sizes including three specific sizes are provided as illustrative examples; in other examples, multiple sizes may include fewer than three specific sizes or more than three specific sizes.

[0083] Cache allocation regulator 196 sets the size of CPU sub-cache 116 to a first specific size (S1) before the first subsequent (N+1) sampling cycle, and PMU 118 generates a first subsequent (N+1) sampling cycle performance metric 119 indicating the performance of device 102 during the first subsequent (N+1) sampling cycle. Cache allocation regulator 196 sets the size of CPU sub-cache 116 to a second specific size (S2) before the second subsequent (N+2) sampling cycle, and PMU 118 generates a second subsequent (N+2) sampling cycle performance metric 119 indicating the performance of device 102 during the second subsequent (N+2) sampling cycle. Cache allocation regulator 196 sets the size of CPU sub-cache 116 to a third specific size (S3) before the third subsequent (N+3) sampling cycle, and PMU 118 generates a third subsequent (N+3) sampling cycle performance metric 119 indicating the performance of device 102 during the third subsequent (N+3) sampling cycle.

[0084] At box 408, cache allocation regulator 196 determines the first subsequent (N+1) sampling cycle performance metric 119 (e.g., MPKI). N+1 Whether it is greater than the second subsequent (N+2) sampling period performance metric 119 (e.g., MPKI) N+2 ) and the scaled version of the second performance threshold (L The sum of Y). In some implementations, L is a scaling factor with a value between 0 and 1.

[0085] In the example, cache allocation regulator 196 determines a first difference (e.g., MPKI) between the first subsequent (N+1) sampling cycle performance metric 119 and the second subsequent (N+2) sampling cycle performance metric 119. N+1 -MPKI N+2 In some respects, the first subsequent (N+1) sampling period performance metric 119 (e.g., MPKI) N+1 The performance metric 119 is greater than that of the second subsequent (N+2) sampling period (e.g., MPKI). N+2 This indicates a performance improvement in the second subsequent (N+2) sampling period compared to the first subsequent (N+1) sampling period. The cache allocation regulator 196 determines the first difference (e.g., MPKI). N+1 -MPKI N+2 Is the scaled version (L) greater than the second performance threshold? Y).

[0086] In response to determining the performance metric 119 for the first subsequent (N+1) sampling period (e.g., MPKI) N+1 The performance metric 119 (e.g., MPKI) is less than or equal to the second subsequent (N+2) sampling period.N+2 ) and the scaled version of the second performance threshold (L The cache allocation regulator 196 sets the size of the CPU sub-cache 116 to a first specific size (S1) at block 410, based on the sum of (Y). For example, in response to determining the first difference (e.g., MPKI) N+1 -MPKI N+2 Scaling version (L) less than or equal to the second performance threshold Y), cache allocation regulator 196 determines that the performance improvement associated with increasing CPU sub-cache 116 to a second specific size (S2) is insufficient, and allocates a first specific size (S1) as the size of CPU sub-cache 116.

[0087] Alternatively, in response to determining the first subsequent (N+1) sampling period performance metric 119 (e.g., MPKI) at box 408. N+1 The performance metric 119 is greater than that of the second subsequent (N+2) sampling period (e.g., MPKI). N+2 ) and the scaled version of the second performance threshold (L The sum of Y), cache allocation regulator 196 determines the second subsequent (N+2) sampling cycle performance metric 119 (e.g., MPKI) at box 412. N+2 Whether it is greater than the third subsequent (N+3) sampling period performance metric 119 (e.g., MPKI) N+3 ) and the scaled version of the second performance threshold (L The sum of Y). In the example, cache allocation regulator 196 determines a second difference (e.g., MPKI) between the second subsequent (N+2) sampling cycle performance metric 119 and the third subsequent (N+3) sampling cycle performance metric 119. N+2 -MPKI N+3 In some respects, the performance metric for the second subsequent (N+2) sampling period is 119 (e.g., MPKI). N+2 The performance metric 119 is greater than the third subsequent (N+3) sampling period (e.g., MPKI). N+3 This indicates a performance improvement in the third subsequent (N+3) sampling period compared to the second subsequent (N+2) sampling period. The cache allocation regulator 196 determines the second difference (e.g., MPKI). N+2 -MPKI N+3 Is the scaled version (L) greater than the second performance threshold? Y).

[0088] In response to determining the performance metric 119 for the second subsequent (N+2) sampling period (e.g., MPKI) N+2 The performance metric 119 (e.g., MPKI) is less than or equal to the third subsequent (N+3) sampling period.N+3 ) and the scaled version of the second performance threshold (L The cache allocation regulator 196 sets the size of the CPU sub-cache 116 to a second specific size at block 414 (S2) based on the sum of (Y). For example, in response to determining the second difference (e.g., MPKI) N+2 -MPKI N+3 Scaling version (L) less than or equal to the second performance threshold Y), cache allocation regulator 196 determines that the performance improvement associated with increasing CPU sub-cache 116 to a third specific size (S3) is insufficient, and allocates a second specific size (S2) as the size of CPU sub-cache 116.

[0089] Alternatively, in response to determining a second subsequent (N+2) sampling period performance metric 119 (e.g., MPKI) N+2 The performance metric 119 is greater than the third subsequent (N+3) sampling period (e.g., MPKI). N+3 ) and the scaled version of the second performance threshold (L The cache allocation regulator 196 allocates a third specific size (S3) at box 416 as the size of CPU sub-cache 116, based on the sum of the values ​​of Y and Y. For example, in response to determining the second difference (e.g., MPKI), N+2 -MPKI N+3 Scaling version (L) greater than or equal to the second performance threshold Y), cache allocation regulator 196 determines that sufficient performance improvement is associated with increasing the size of CPU sub-cache 116 to a third specific size (S3), and allocates the third specific size (S3) as the size of CPU sub-cache 116.

[0090] The technical advantage of testing performance improvements corresponding to multiple specific sizes is that it determines whether performance has a non-linear sensitivity to cache size. For example, a performance metric 119 corresponding to increasing the size of CPU sub-cache 116 by a first amount (M) may result in insufficient performance improvement, while a larger cache size (e.g., S3) may result in sufficient performance improvement.

[0091] refer to Figure 5 This illustrates a specific implementation of a performance-based cache tuning method 500. In a particular aspect, one or more operations of method 500 are performed by at least one of PMU 118, CPU PMU 104, cache PMU 106, cache allocation regulator 196, or a combination thereof.

[0092] Method 500 includes, at 502, obtaining a performance metric associated with at least one of the device's system cache or central processing unit (CPU) subsystem. For example, cache allocation regulator 196 obtains a performance metric 119 associated with at least one of the system cache 194 or CPU subsystem 109, as referenced. Figure 1 As described.

[0093] Method 500 further includes: at 504, adjusting the size of the CPU portion in the system cache, where the CPU portion is allocated to the CPU subsystem, based on determining that a performance metric 119 meets a cache reduction criterion 191 or a cache expansion criterion 193. For example, based on determining that a performance metric 119 meets a cache reduction criterion 191 or a cache expansion criterion 193, cache allocation regulator 196 adjusts the size of the CPU sub-cache 116, as referenced. Figures 1 to 4B As described.

[0094] In some aspects, adjusting the size of CPU sub-cache 116 includes reducing the size of CPU sub-cache 116 and reallocating one or more blocks of CPU sub-cache 116. In some specific implementations, Figure 1 The cache controller 198 performs power degradation on one or more blocks that have been disposed of, in order to reduce the power consumption of the device 102.

[0095] Therefore, method 500 enables the size of CPU sub-cache 116 to be dynamically adjusted based on performance metric 119. The technical advantages of dynamic resizing may include achieving a balance between improved performance (e.g., lower MPKI) due to the increase in the size of CPU sub-cache 116 and reduced power consumption (e.g., through power degradation of deallocated blocks).

[0096] Figure 5 Method 500 can be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit (such as a CPU), a DSP, a controller, another hardware device, a firmware device, or any combination thereof. As an example, Figure 5 Method 500 can be executed by a processor that executes instructions, such as reference Figure 1 As described.

[0097] In conjunction with the described specific implementation, an apparatus includes: a component for obtaining a performance metric associated with at least one of a system cache or a central processing unit (CPU) subsystem. For example, the component for obtaining the performance metric may correspond to... Figure 1The PMU 118, CPU PMU 104, cache PMU 106, cache allocation regulator 196, one or more processors 190, device 102, system 100, one or more other circuits or components or any combination thereof configured to obtain performance metrics.

[0098] The device also includes components for adjusting the size of the CPU portion in the system cache, the size being adjusted based on determining that performance metrics meet cache tuning criteria, wherein the CPU portion is allocated to the CPU subsystem. For example, the component for adjusting the size may correspond to... Figure 1 The cache allocation regulator 196, one or more processors 190, device 102, system 100, one or more other circuits or components or any combination thereof configured to adjust the size of CPU portions.

[0099] In some implementations, a non-transitory computer-readable medium (e.g., a computer-readable storage device, such as memory) includes instructions that, when executed by one or more processors (e.g., one or more processors 190, cache allocation regulator 196, or a combination thereof), cause the one or more processors to: obtain a performance metric (e.g., performance metric 119) associated with at least one of a system cache (e.g., system cache 194) or a central processing unit (CPU) subsystem (e.g., CPU subsystem 109). When executed by the one or more processors, these instructions also cause the one or more processors to: adjust the size of a CPU portion (e.g., CPU sub-cache 116) in the system cache, where the CPU portion is allocated to the CPU subsystem, based on determining that the performance metric meets a cache adjustment criterion (e.g., cache reduction criterion 191 or cache expansion criterion 193).

[0100] Specific aspects of this disclosure are described below in a collection of related embodiments:

[0101] According to Embodiment 1, a device includes a system cache and a cache allocation regulator. The system cache is accessible by a central processing unit (CPU) subsystem and includes a CPU portion allocated to the CPU subsystem. The cache allocation regulator is configured to: obtain a performance metric associated with at least one of the system cache or the CPU subsystem; and adjust the size of the CPU portion based on the performance metric meeting cache adjustment criteria.

[0102] Example 2 includes the device according to Example 1, wherein the cache allocation regulator is configured to: reduce the size of the CPU portion based on determining that the performance metric meets the cache reduction criteria, and wherein, in response to the reduction in the size of the CPU portion, one or more blocks of the system cache are disposed of.

[0103] Example 3 includes the device according to Example 2, the device further including a cache controller configured to power degrade one or more blocks of the system cache that have been disposed of.

[0104] Example 4 includes the device according to Example 2 or Example 3, wherein the cache allocation regulator is configured to: determine that the performance metric meets the cache reduction criterion based on detecting that the performance metric meets a performance threshold.

[0105] Example 5 includes a device according to any one of Examples 1 to 4, wherein the cache allocation regulator is configured to increase the size of the CPU portion based on determining that the performance metric meets the cache expansion criteria.

[0106] Example 6 includes the device according to Example 5, wherein the cache allocation regulator is configured to further increase the size of the CPU portion based on determining that the size of the CPU portion is less than a CPU portion size threshold, that the system cache has available space, or both.

[0107] Example 7 includes a device according to any one of Examples 1 to 6, wherein the cache allocation regulator is configured to prevent a second increase in the size of the CPU portion if no performance benefit is detected from the first increase in the size of the CPU portion.

[0108] Example 8 includes a device according to any one of Examples 1 to 7, wherein the cache allocation regulator is configured to: rescind the previous increase in the size of the CPU portion based on the detection that the performance benefit of the previous increase in the size of the CPU portion is insufficient.

[0109] Example 9 includes a device according to any one of Examples 1 to 8, wherein the cache allocation regulator is configured to: determine a plurality of performance metrics corresponding to a plurality of CPU portion sizes; select a specific CPU portion size from the plurality of CPU portion sizes based on a comparison of the plurality of performance metrics; and adjust the size of the CPU portion based on the specific CPU portion size.

[0110] Example 10 includes a device according to any one of Examples 1 to 9, wherein the cache allocation regulator is configured to: determine a second performance metric corresponding to a second CPU portion size based on the detection that the performance benefit from a previous increase in the size of the CPU portion is less than a performance benefit threshold, and to test whether one or more other CPU portion sizes provide improved performance benefits due to at least one of a larger working set size or nonlinear sensitivity to cache size; and increase the size of the CPU portion based on a scaled version that determines the difference between the performance metric and the second performance metric is greater than the performance benefit threshold.

[0111] Example 11 includes a device according to any one of Examples 1 to 10, wherein the performance metric includes at least one of the following: MPKI (Million Instructions Miss Count), miss rate, CPI (Cycle Per Instruction), branch misprediction count, or active core count.

[0112] Example 12 includes a device according to any one of Examples 1 to 11, wherein the cache allocation regulator is configured to: obtain a first performance metric from a CPU performance monitoring unit (PMU), the first performance metric indicating the performance of the CPU; and obtain a second performance metric from a cache PMU, the second performance metric indicating the performance of the system cache, wherein the performance metric is based on the first performance metric and the second performance metric.

[0113] Example 13 includes the device according to Example 12, wherein the performance of the system cache includes hit count, miss count, memory access count, bus bandwidth, memory bandwidth, allocated block count, unallocated block count, active block count, or a combination thereof.

[0114] Example 14 includes the device according to Example 12 or Example 13, wherein the performance of the CPU includes instruction counting.

[0115] Example 15 includes a device according to any one of Examples 1 to 14, wherein the system cache is also accessible by one or more additional subsystems.

[0116] Example 16 includes the device according to Example 15, wherein the one or more additional subsystems include at least one of the following: a graphics processing unit (GPU), a digital signal processor (DSP), an audio processor, a video processor, a modem, a low-power audio subsystem, or a display.

[0117] Example 17 includes a device according to any one of Examples 1 to 16, wherein the system cache includes a last-level cache (LLC).

[0118] According to embodiment 18, a method includes: obtaining at a device a performance metric associated with at least one of the device's system cache or central processing unit (CPU) subsystem; and adjusting the size of a CPU portion in the system cache, wherein the CPU portion is allocated to the CPU subsystem, based on determining that the performance metric meets a cache adjustment criterion.

[0119] Example 19 includes the method according to Example 18, the method further comprising: in response to a reduction in the size of the CPU portion, deallocating one or more blocks of the system cache, wherein the cache adjustment criterion includes a cache reduction criterion, and wherein adjusting the size of the CPU portion includes reducing the size of the CPU portion.

[0120] Example 20 includes the method according to Example 19, the method further comprising: power degradation of the one or more blocks of the system cache that have been deallocated.

[0121] Example 21 includes the method according to Example 19 or Example 20, wherein determining that the performance metric meets the cache reduction criterion includes detecting that the performance metric meets a performance threshold.

[0122] Example 22 includes the method according to any one of Examples 18 to 21, wherein the cache adjustment criterion includes a cache expansion criterion, and wherein adjusting the size of the CPU portion includes increasing the size of the CPU portion.

[0123] Example 23 includes the method according to Example 22, wherein the size of the CPU portion is further increased based on determining that the size of the CPU portion is less than a CPU portion size threshold, that the system cache has available space, or both.

[0124] Example 24 includes the method according to any one of Examples 18 to 23, and further includes: preventing a second increase in the size of the CPU portion if no performance benefit is detected from the first increase in the size of the CPU portion.

[0125] Example 25 includes the method according to any one of Examples 18 to 24, and further includes: reversing the previous increase in the size of the CPU portion based on the detection that the performance benefit from the previous increase in the size of the CPU portion is insufficient.

[0126] Example 26 includes the method according to any one of Examples 18 to 25, further comprising: determining a plurality of performance metrics corresponding to a plurality of CPU portion sizes; selecting a specific CPU portion size from the plurality of CPU portion sizes based on a comparison of the plurality of performance metrics; and adjusting the size of the CPU portion based on the specific CPU portion size.

[0127] Example 27 includes the method according to any one of Examples 18 to 26, and further includes: determining a second performance metric corresponding to a second CPU portion size based on detecting that the performance benefit from a previous increase in the size of the CPU portion is less than a performance benefit threshold, and in order to test whether one or more other CPU portion sizes provide improved performance benefits due to at least one of a larger working set size or nonlinear sensitivity to cache size; and increasing the size of the CPU portion based on a scaled version that determines the difference between the performance metric and the second performance metric is greater than the performance benefit threshold.

[0128] Example 28 includes the method according to any one of Examples 18 to 27, wherein the performance metric includes at least one of the following: MPKI (Million Instructions Miss Count), miss rate, CPI (Cycle Per Instruction), branch misprediction count, or active core count.

[0129] Example 29 includes the method according to any one of Examples 18 to 28, further comprising: obtaining a first performance metric from a CPU performance monitoring unit (PMU), the first performance metric indicating the performance of the CPU; and obtaining a second performance metric from a cache PMU, the second performance metric indicating the performance of the system cache, wherein the performance metric is based on the first performance metric and the second performance metric.

[0130] Example 30 includes the method according to Example 29, wherein the performance of the system cache includes hit count, miss count, memory access count, bus bandwidth, memory bandwidth, allocated block count, unallocated block count, active block count, or a combination thereof.

[0131] Example 31 includes the method according to Example 29 or Example 30, wherein the performance of the CPU includes instruction counting.

[0132] Example 32 includes the method according to any one of Examples 18 to 31, wherein the system cache is also accessible by one or more additional subsystems.

[0133] Example 33 includes the method according to Example 32, wherein the one or more additional subsystems include at least one of the following: a graphics processing unit (GPU), a digital signal processor (DSP), an audio processor, a video processor, a modem, a low-power audio subsystem, or a display.

[0134] Example 34 includes the method according to any one of Examples 18 to 33, wherein the system cache includes a last-level cache (LLC).

[0135] According to Embodiment 35, a non-transitory computer-readable medium storage instruction, when executed by a processor, causes the processor to perform the method according to any one of Embodiments 18 to 34.

[0136] According to embodiment 36, an apparatus includes: components for performing the method according to any one of embodiments 18 to 34.

[0137] According to embodiment 37, a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: obtain a performance metric associated with at least one of a system cache or a central processing unit (CPU) subsystem; and, based on determining that the performance metric meets a cache adjustment criterion, adjust the size of a CPU portion in the system cache, wherein the CPU portion is allocated to the CPU subsystem.

[0138] According to embodiment 38, an apparatus includes: components for obtaining a performance metric associated with at least one of a system cache or a central processing unit (CPU) subsystem; and components for adjusting the size of a CPU portion in the system cache, the size being adjusted based on determining that the performance metric meets a cache adjustment criterion, wherein the CPU portion is allocated to the CPU subsystem.

[0139] Those skilled in the art will also understand that the various exemplary logic blocks, configurations, modules, circuits, and algorithm steps described in connection with the specific embodiments disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of both. The various exemplary components, blocks, configurations, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or processor-executable instructions depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, and such implementation decisions shall not be construed as departing from the scope of this disclosure.

[0140] The steps of the methods or algorithms described in conjunction with the specific embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, compressed optical disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. Alternatively, the processor and storage medium may reside as discrete components in a computing device or a user terminal.

[0141] The prior description of the disclosed aspects is provided to enable those skilled in the art to make or use the disclosed aspects. Various modifications to these aspects will be apparent to those skilled in the art, and the principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but should be granted the broadest scope that may be consistent with the principles and novel features as defined by the following claims.

Claims

1. An apparatus, said apparatus comprising: A system cache accessible by a central processing unit (CPU) subsystem, the system cache including a CPU portion allocated to the CPU subsystem; and A cache allocation regulator, wherein the cache allocation regulator is configured to: Obtain a performance metric associated with at least one of the system cache or the CPU subsystem; as well as Based on the performance metrics meeting the cache adjustment criteria, the size of the CPU portion is adjusted.

2. The device of claim 1, wherein the cache allocation regulator is configured to: reduce the size of the CPU portion based on determining that the performance metric meets the cache reduction criterion, and wherein, in response to the reduction in the size of the CPU portion, one or more blocks of the system cache are disposed of.

3. The device of claim 2, further comprising a cache controller configured to: perform power degradation on the one or more blocks of the system cache that have been disposed of.

4. The device of claim 2, wherein the cache allocation regulator is configured to: determine that the performance metric meets the cache reduction criterion based on detecting that the performance metric meets a performance threshold.

5. The device of claim 1, wherein the cache allocation regulator is configured to: increase the size of the CPU portion based on determining that the performance metric meets the cache expansion criteria.

6. The device of claim 5, wherein the cache allocation regulator is configured to further increase the size of the CPU portion based on determining that the size of the CPU portion is less than a CPU portion size threshold, that the system cache has available space, or both.

7. The device of claim 1, wherein the cache allocation regulator is configured to prevent a second increase in the size of the CPU portion if no performance benefit is detected from the first increase in the size of the CPU portion.

8. The device of claim 1, wherein the cache allocation regulator is configured to: rescind the previous increase in the size of the CPU portion based on the detection that the performance benefit of the previous increase in the size of the CPU portion is insufficient.

9. The device of claim 1, wherein the cache allocation regulator is configured to: Determine multiple performance metrics corresponding to multiple CPU segment sizes; Based on a comparison of the multiple performance metrics, a specific CPU partition size is selected from the multiple CPU partition sizes; and The size of the CPU portion is adjusted based on the specific CPU portion size.

10. The apparatus of claim 1, wherein the cache allocation regulator is configured to: based on the detection that the performance benefit from a previous increase in the size of the CPU portion is less than a performance benefit threshold, and in order to test whether one or more other CPU portion sizes provide improved performance benefits due to at least one of a larger working set size or a non-linear sensitivity to cache size: Determine a second performance metric corresponding to the size of the second CPU portion; and The size of the CPU portion is increased based on a scaled version that determines the difference between the performance metric and the second performance metric is greater than the performance benefit threshold.

11. The device of claim 1, wherein the performance metric includes at least one of the following: MPKI (Million Instructions Miss Count), miss rate, CPI (Cycle Per Instruction), branch misprediction count, or active core count.

12. The device of claim 1, wherein the cache allocation regulator is configured to: A first performance metric is obtained from the CPU performance monitoring unit (PMU), the first performance metric indicating the performance of the CPU; and A second performance metric is obtained from the cache PMU, the second performance metric indicating the performance of the system cache. The performance metric is based on the first performance metric and the second performance metric.

13. The device of claim 12, wherein the performance of the system cache includes hit count, miss count, memory access count, bus bandwidth, memory bandwidth, allocated block count, unallocated block count, active block count, or a combination thereof.

14. The device of claim 12, wherein the performance of the CPU includes instruction counting.

15. The device of claim 1, wherein the system cache is also accessible by one or more additional subsystems.

16. The device of claim 15, wherein the one or more additional subsystems include at least one of: a graphics processing unit (GPU), a digital signal processor (DSP), an audio processor, a video processor, a modem, a low-power audio subsystem, or a display.

17. The device of claim 1, wherein the system cache includes a last-level cache (LLC).

18. A method comprising: Obtain at the device a performance metric associated with at least one of the device’s system cache or central processing unit (CPU) subsystem; as well as Based on the determination that the performance metric meets the cache adjustment criteria, the size of the CPU portion in the system cache is adjusted, wherein the CPU portion is allocated to the CPU subsystem.

19. The method according to claim 18, further comprising: In response to the reduction in the size of the CPU portion, one or more blocks of the system cache are disposed of, wherein the cache adjustment criteria include a cache reduction criterion, and wherein adjusting the size of the CPU portion includes reducing the size of the CPU portion.

20. The method according to claim 19, further comprising: Power degradation is applied to one or more blocks of the system cache that have been deallocated.

21. The method of claim 19, wherein determining that the performance metric meets the cache reduction criterion includes detecting that the performance metric meets a performance threshold.

22. The method of claim 18, wherein the cache adjustment criterion includes a cache expansion criterion, and wherein adjusting the size of the CPU portion includes increasing the size of the CPU portion.

23. The method of claim 22, wherein the size of the CPU portion is further increased based on determining that the size of the CPU portion is less than a CPU portion size threshold, that the system cache has available space, or both.

24. The method according to claim 18, further comprising: If no performance benefit is detected from the first increase in the size of the CPU portion, a second increase in the size of the CPU portion is prevented.

25. The method according to claim 18, further comprising: The previous increase in the size of the CPU portion was revoked because the performance benefits from the previous increase in the size of the CPU portion were found to be insufficient.

26. The method according to claim 18, further comprising: Determine multiple performance metrics corresponding to multiple CPU segment sizes; Based on the comparison of the multiple performance metrics, a specific CPU portion size is selected from the multiple CPU portion sizes; as well as The size of the CPU portion is adjusted based on the specific CPU portion size.

27. The method of claim 18, further comprising: Based on the detection that the performance benefit from a previous increase in the size of the CPU portion is less than a performance benefit threshold, and in order to test whether one or more other CPU portion sizes provide improved performance benefits due to at least one of a larger working set size or non-linear sensitivity to cache size: Determine a second performance metric corresponding to the size of the second CPU portion; as well as The size of the CPU portion is increased based on a scaled version that determines the difference between the performance metric and the second performance metric is greater than the performance benefit threshold.

28. The method of claim 18, wherein the performance metric includes at least one of the following: MPKI (Million Instructions Miss Count), miss rate, CPI (Cycle Per Instruction), branch misprediction count, or active core count.

29. A non-transitory computer-readable medium storing instructions, said instructions causing said one or more processors, when executed, to: Obtain a performance metric associated with at least one of the system cache or central processing unit (CPU) subsystem; and Based on the determination that the performance metric meets the cache adjustment criteria, the size of the CPU portion in the system cache is adjusted, wherein the CPU portion is allocated to the CPU subsystem.

30. An apparatus comprising: A component used to obtain a performance metric associated with at least one of the system cache or central processing unit (CPU) subsystem; and A component for adjusting the size of the CPU portion in the system cache, the size being adjusted based on determining that the performance metric meets cache tuning criteria, wherein the CPU portion is allocated to the CPU subsystem.

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