Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. According to the preparation method, in the process of forming a first metal layer, a shielding ring is adopted to shield a part of the top surface of a Taiko ring along the periphery of the Taiko ring, so that the part of the top surface, shielded by the shielding ring, of the Taiko ring cannot be sputtered by metal, and cannot be covered by the first metal layer. Namely, a part of the top surface of the Taiko ring is covered by the first metal layer, and the remaining part of the top surface is in an exposed state. On the basis, when the chemical coating film is attached, the chemical coating film covers the first metal layer and is also bonded with part of the top surface of the exposed Taiko ring. Furthermore, the roughness of the top surface of the Taiko ring is large, so that the chemical plating film is pasted and covered on the exposed part of the top surface of the Taiko ring, the adhesion stability between the chemical plating film and the Taiko ring is improved, the chemical plating film can be ensured to be completely and firmly pasted on the back surface of the wafer in the chemical plating process, the problem of crystal back seepage and diffusion coating is avoided, and the service life of the wafer is prolonged. The chemical plating process effect is guaranteed, and the device yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor preparation, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Electroless plating, also known as chemical plating or non-electrolytic plating, is a process of depositing a metal plating layer on the surface of a substrate by the oxidation-reduction reaction in the plating solution without relying on an external power supply. It is suitable for power semiconductor devices in a high-current working environment, such as vehicle-grade Insulated Gate Bipolar Transistor (IGBT). Due to the high requirement for heat dissipation performance of IGBT, a special packaging method, double-sided copper welding, is needed. This packaging method is more prone to stress concentration, resulting in a high risk of welding cracks. Therefore, additional electroless plating of nickel-palladium-gold as a plating layer on the surface of the aluminum-copper pad can relieve stress, optimize the temperature distribution at the wiring site, and significantly improve the service life of the packaging module.

[0003] Before performing electroless plating, the areas in the wafer that do not need electroless plating need to be covered with an electroless plating film to prevent the formation of an electroless plated metal layer on these areas. Please refer to Figure 1 and Figure 2 Taiko ring technology is usually used to ensure the strength of the wafer 100 during the processing of IGBT products; that is, the central area C of the back surface of the wafer 100 is selectively ground and thinned to tens of microns, while a Taiko ring T with a certain width is reserved on the peripheral edge. Since the Taiko ring T on the back surface of the wafer 100 has a convex topography, it is a serious challenge to cover the electroless plating film 101 on the non-planar back surface of the wafer 100. When the electroless plating film 101 is improperly covered, the air gap G at the step position of the Taiko ring T close to the central area C is easily penetrated into the plating solution, causing the electroless plating film 101 to bulge and fall off, resulting in the formation of an electroless plated metal layer on the back gold structure 102 of the wafer 100, which affects the device yield.

[0004] Therefore, there is an urgent need for a new electroless plating method to solve the above technical problems. SUMMARY

[0005] The present application aims to provide a semiconductor device and a preparation method thereof to solve at least one of the problems of how to improve the stability and reliability of covering an electroless plating film on a wafer with a Taiko ring and how to avoid liquid penetration and plating in the wafer back during the electroless plating process.

[0006] To solve the above technical problems, the present application provides a preparation method of a semiconductor device, comprising:

[0007] providing a wafer, wherein the back surface of the wafer is formed with a Taiko ring arranged around the edge of the wafer;

[0008] a sputtering process is performed on the remaining area of the back surface of the wafer to form a first metal layer; wherein the portion of the top surface of the Taiko ring that is shielded by the shielding ring is not covered by the first metal layer;

[0009] a plating film is attached on the portion of the top surface of the Taiko ring that is not covered by the first metal layer and the first metal layer;

[0010] a plating process is performed on the front surface of the wafer to form a second metal layer.

[0011] Optionally, in the method of manufacturing the semiconductor device, the roughness of the top surface of the Taiko ring is greater than the roughness of the surface of the first metal layer.

[0012] Optionally, in the method of manufacturing the semiconductor device, the adhesion of the plating film to the top surface of the Taiko ring is greater than the adhesion of the plating film to the surface of the first metal layer.

[0013] Optionally, in the method of manufacturing the semiconductor device, the portion of the top surface of the Taiko ring that is not covered by the first metal layer is annular, and the annular width of the portion of the top surface of the Taiko ring that is not covered by the first metal layer is greater than or equal to 10% of the annular width of the top surface of the Taiko ring, and less than the annular width of the top surface of the Taiko ring.

[0014] Optionally, in the method of manufacturing the semiconductor device, the shielding ring shields the outer ring of the top surface of the Taiko ring, and extends towards the inner ring of the top surface of the Taiko ring to shield an annular area with a preset annular width.

[0015] Optionally, in the method of manufacturing the semiconductor device, the top surface of the shielding ring is hollow, and has a plurality of hollow areas arranged at intervals; wherein,

[0016] After the sputtering process is performed, each of the hollow areas is covered by the first metal layer relative to the portion of the top surface of the Taiko ring, so that the portion of the top surface of the Taiko ring that is shielded by the shielding ring is in a discontinuous state.

[0017] Optionally, in the method of manufacturing the semiconductor device, in the top surface of the shielding ring, each of the hollow areas is arranged along the circumference of the shielding ring, and encloses at least one hollow ring; and,

[0018] When the number of the hollow rings is greater than or equal to 2, the hollow rings are concentrically distributed; and in the radial direction of the shielding ring, the hollow areas within the hollow rings are staggered.

[0019] Optionally, in the method for fabricating the semiconductor device, the inner ring of the shielding ring is serrated or irregular, so that one side of the inner ring of the Taiko ring, which is not covered by the first metal layer, faces the top surface of the Taiko ring and is also serrated or irregular.

[0020] Optionally, in the semiconductor device fabrication method, a portion of the back side of the wafer surrounded by the Taiko ring is a central region; and after the chemical coating is applied, the inner ring sidewall of the Taiko ring and the surface of the central region adjacent to the inner ring sidewall of the Taiko ring are wrapped by the chemical coating to form a sealed cavity.

[0021] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising: a wafer and a first metal layer and a second metal layer respectively located on the back side and the front side of the wafer; wherein, a Taiko ring is formed on the back side of the wafer and disposed around the edge of the wafer, and the first metal layer and the second metal layer are fabricated using the semiconductor device fabrication method described above.

[0022] In summary, this invention provides a semiconductor device and its fabrication method. Compared to existing technologies, the fabrication method provided by this invention employs a shielding ring to shield a portion of the top surface of the Taiko ring along its periphery during the formation of the first metal layer. This prevents the shielded portion of the top surface of the Taiko ring from being sputtered by metal and thus from being covered by the first metal layer. In other words, a portion of the top surface of the Taiko ring is covered by the first metal layer, while the remaining portion is exposed. Based on this, when applying the electroless plating film, the electroless plating film not only covers the first metal layer but also adheres to the exposed portion of the top surface of the Taiko ring. Furthermore, because the top surface of the Taiko ring has a relatively large roughness, attaching the electroless plating film to the exposed portion of the top surface of the Taiko ring improves the adhesion stability between the electroless plating film and the Taiko ring. This ensures that during the electroless plating process, the electroless plating film can be completely and firmly adhered to the back side of the wafer, avoiding back-side liquid seepage and ensuring the electroless plating process effect, thereby improving device yield. Attached Figure Description

[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0024] Figure 1 This is a top view of a wafer with a Taiko ring, as described in the prior art.

[0025] Figure 2 In existing technology Figure 1 A schematic diagram of the cross-section at point A-A'.

[0026] Figure 3 This is a flowchart of the semiconductor device fabrication method in an embodiment of the present invention.

[0027] Figure 4 This is a top view of the back side of a wafer with a Taiko ring in an embodiment of the present invention.

[0028] Figure 5 This is before thinning in the embodiments of the present invention. Figure 4 A schematic diagram of the cross-section at point B-B' is shown.

[0029] Figure 6 This is the thinning process in the embodiments of the present invention. Figure 4 A schematic diagram of the cross-section at point B-B' is shown.

[0030] Figure 7 This is a cross-sectional schematic diagram of the shielding ring and the bearing groove in an embodiment of the present invention.

[0031] Figure 8 This is a three-dimensional schematic diagram of the shielding ring and the bearing groove in an embodiment of the present invention.

[0032] Figure 9 This is a top view of the first type of shielding ring in an embodiment of the present invention.

[0033] Figure 10 This is a top view of the second type of shielding ring in an embodiment of the present invention.

[0034] Figure 11 This is a top view of the third type of shielding ring in this embodiment of the invention.

[0035] Figure 12 After the first metal layer is formed in the embodiment of the present invention Figure 4 A schematic diagram of the cross-section at point B-B' is shown.

[0036] Figure 13 After the chemical coating is formed in the embodiments of the present invention Figure 4 A schematic diagram of the cross-section at point B-B' is shown.

[0037] And, in the attached image:

[0038] 100 - Wafer; 101 - Chemical coating; 102 - Back gold structure;

[0039] 200 - Wafer; 201 - First metal layer; 202 - Chemical coating;

[0040] 300 - Shielding ring; 301 - Bearing groove;

[0041] T - Taiko ring; C - Central region; G - Air gap; S - Sealed cavity; E - Shielded area; D - Location where the Taiko ring meets the central region; d1 - Width of the first ring; d2 - Width of the second ring; H1 - First hollowed-out ring; H2 - Second hollowed-out ring. Detailed Implementation

[0042] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0043] Furthermore, the X-axis, Y-axis, and Z-axis directions referred to in this application specification are three mutually perpendicular directions in three-dimensional space, and the direction from the front side of the wafer to the back side is the extension direction of the positive half-axis of the Z-axis.

[0044] Please see Figure 3 This embodiment provides a method for fabricating a semiconductor device, including:

[0045] Step 1 S10: Provide a wafer, wherein a Taiko ring is formed on the back side of the wafer and surrounds the edge of the wafer;

[0046] Step 2 S20: A shielding ring is used to shield a portion of the top surface of the Taiko ring around its perimeter, and a sputtering process is performed on the remaining area of ​​the back side of the wafer to form a first metal layer; wherein the portion of the top surface of the Taiko ring shielded by the shielding ring is not covered by the first metal layer;

[0047] Step 3 S30: Apply a chemical coating to the top surface of the portion of the Taiko ring not covered by the first metal layer and to the first metal layer;

[0048] Step 4S40: Perform a chemical plating process on the front side of the wafer to form a second metal layer.

[0049] Based on this, the semiconductor device fabrication method provided in this embodiment retains a portion of the top surface of the Taiko ring that is not covered by the first metal layer. This allows the electroplating film to be bonded to the exposed top surface of the Taiko ring during the electroplating process, which improves the adhesion of the electroplating film and ensures that the electroplating film can be completely and firmly attached to the back side of the wafer during the electroplating process. This avoids the problem of back-side liquid seepage, ensures the electroplating process effect, and improves device yield.

[0050] The following describes in detail, with reference to the accompanying drawings, the method for fabricating the semiconductor device provided in this embodiment.

[0051] Specifically, the method for fabricating the semiconductor device includes:

[0052] Step 1 S10: Please refer to Figures 4 to 6 A wafer 200 is provided, wherein a Taiko ring T is formed on the back side of the wafer 200 and is disposed around the edge of the wafer 200.

[0053] It should be noted that the Taiko ring T is a ring-shaped support structure retained at the wafer edge in the Taiko process, which enhances the mechanical strength of the ultrathin wafer. The Taiko ring T can be fabricated using methods such as chemical mechanical polishing or laser dicing.

[0054] For example Figure 5 and Figure 6 As shown, the wafer 200 is a silicon wafer with low hardness. A chemical mechanical polishing (CMP) method is used to thin the central region C on the back side of the wafer 200, while leaving a ring of the edge of the wafer 200 unpolished, thus maintaining the initial thickness of the wafer 200. After the thinning process is completed, a wafer can be formed... Figure 4 and Figure 6 The structure shown indicates that the thickness of the central region C of the wafer 200 is significantly thinner than the thickness of the unpolished edge region of the wafer 200. The unpolished edge region of the wafer 200 serves as the Taiko ring T, and the junction D between the Taiko ring T and the polished, thinned central region C is stepped.

[0055] Step 2 S20: Please refer to Figures 7 to 12 A shielding ring 300 is used to shield a portion of the top surface of the Taiko ring T around its periphery, and a sputtering process is performed on the remaining area of ​​the back side of the wafer 200 to form a first metal layer 201; wherein the portion of the top surface of the Taiko ring T shielded by the shielding ring 300 is not covered by the first metal layer 201.

[0056] For example, if an IGBT device layer structure has already been formed in the wafer 200, a first metal layer 201 and a second metal layer (not shown) need to be formed on the back and front sides of the wafer 200, respectively. The first metal layer 201 is located on the back side of the wafer 200 to provide electrode leads. Since the current path of the IGBT flows from the collector on the back side of the wafer 200 through the drift region to the emitter on the front side, the first metal layer 201 needs to withstand high current and high temperature stress. Therefore, the first metal layer 201 is required to meet the conditions of low contact resistance, high thermal conductivity, and high adhesion. The sputtering process precisely meets these three requirements for the first metal layer 201. Therefore, the sputtering process is preferred for forming the first metal layer 201. The second metal layer is located on the front side of the wafer 200 to serve as the electrode leads for the gate and emitter, and simultaneously needs to meet the requirements of precise wiring, low contact resistance, and solder compatibility on the front side of the wafer 200. Because chemical plating has the characteristics of good uniformity, strong selectivity, and thin and dense structure, it is preferred to use chemical plating to prepare the second metal layer.

[0057] However, the electroless plating process requires pre-applying an electroless plating film to the non-electroless plating area to avoid affecting it. Therefore, the back side of the wafer 200 needs to be covered with this electroless plating film. Furthermore, because the back side of the wafer 200 has a protruding Taiko ring T, directly applying the film using existing processes easily leads to bulging and peeling of the electroless plating film, causing liquid seepage and plating on the back side of the wafer 200, affecting product yield. Therefore, to improve the adhesion of the electroless plating film, in this embodiment, before preparing the first metal layer 201, a shielding ring 300 is used to shield part of the top surface of the Taiko ring T. This prevents the formation of a metal film layer on the shielded top surface of the Taiko ring T during the sputtering process, maintaining the original silicon material surface.

[0058] Furthermore, the surface roughness of the portion of the top surface of the Taiko ring T not covered by the first metal layer 201 is greater than the surface roughness of the first metal layer 201. That is, the surface roughness of the silicon material is greater than the surface roughness of the first metal layer 201. Consequently, the adhesion of the electroless plating film to the top surface of the Taiko ring T is greater than the adhesion of the electroless plating film to the surface of the first metal layer 201. In other words, the adhesion of the electroless plating film to the portion of the top surface of the Taiko ring T not covered by the first metal layer 201 is significantly greater than the adhesion to the first metal layer 201, which helps improve the adhesion stability of the electroless plating film and reduces the probability of blistering and peeling of the electroless plating film during the electroless plating process.

[0059] Furthermore, such as Figure 7 ,Figure 8 and Figure 12 As shown, the shielding ring 300 shields the outer ring of the top surface of the Taiko ring T and extends towards the inner ring of the top surface of the Taiko ring T, shielding an annular region of a predetermined ring width. Specifically, the shielding ring 300 is disposed on the top surface of a support groove 301, and the two can be integrally formed to form a receiving structure for supporting the wafer 200 in the sputtering process. The support groove 301 is cylindrical and has a groove. The sidewall height of the groove is higher than the thickness of the Taiko ring T, and the diameter of the bottom wall of the groove is larger than the diameter of the wafer 200, so that the wafer 200 can be accommodated in the groove. The outer diameter of the shielding ring 300 is the same as the outer diameter of the support groove 301, and the outer ring edge of the shielding ring 300 is connected to the outer ring edge of the top surface of the sidewall of the support groove 301; and the surface where the shielding ring 300 is located is parallel to the surface where the bottom wall of the support groove 301 is located. The shielding ring 300 has a certain ring width, such that the projection of the inner ring edge of the shielding ring 300 relative to the surface of the wafer 200 is located on the top surface of the Taiko ring T, and forms an annular region of the preset ring width.

[0060] Furthermore, this embodiment does not limit the specific morphology of the shielding ring 300. For example... Figure 9 and Figure 12 As shown, the shielding ring 300 is a standard annular structure, enabling the formation of a standard annular shielding region E on the top surface of the Taiko ring T. To further enhance the adhesion between the chemical coating and the shielding region E, such as... Figure 10 and Figure 12 As shown, the top surface of the shielding ring 300 is perforated and has multiple spaced perforated regions. After the sputtering process, each of the perforated regions is covered by the first metal layer 201 relative to a portion of the top surface of the Taiko ring T, so that the portion of the top surface of the Taiko ring T shielded by the shielding ring 300 is discontinuous. In other words, during the sputtering process, sputtered ions are incident on the corresponding portion of the top surface of the Taiko ring T through the perforated regions of the shielding ring 300, resulting in the formation of multiple small metal film structures on the corresponding portion of the top surface of the Taiko ring T with morphologies similar to the perforated regions. Therefore, other areas of the shielding ring 300 relative to the top surface of the Taiko ring T are separated into discontinuous regions by these small metal film structures, i.e., in a discontinuous state. Understandably, such discontinuous regions can increase their own roughness, thereby improving the adhesion of the electroplating film to the discontinuous regions in subsequent processes, ensuring that the electroplating film stably covers the back side of the wafer 200 and avoids affecting the electroplating process.

[0061] Preferably, within the top surface of the shielding ring 300, each of the hollowed-out areas is arranged circumferentially around the shielding ring, forming at least one hollowed-out ring. In other words, the hollowed-out ring is formed by multiple hollowed-out areas surrounding the shielding ring circumferentially, and the hollowed-out areas within the same hollowed-out ring remain spaced apart. Furthermore, when the number of hollowed-out rings is greater than or equal to two, the hollowed-out rings are concentrically distributed. And in the radial direction of the shielding ring, the hollowed-out areas within each hollowed-out ring are staggered. That is, the hollowed-out areas in two adjacent hollowed-out rings are not perfectly aligned on the same radial line, but are distributed in a staggered manner.

[0062] For example, such as Figure 10 As shown, the hollowed-out areas within the top surface of the shielding ring 300 respectively form a first hollowed-out ring H1 and a second hollowed-out ring H2. The first hollowed-out ring H1 and the second hollowed-out ring H2 are radially spaced apart. The second hollowed-out ring H2 is embedded within the first hollowed-out ring H1, and the two have the same center, i.e., they are concentrically distributed. The hollowed-out areas in the first hollowed-out ring H1 and the second hollowed-out ring H2 have a certain degree of overlap on any diameter, and their projections along the diameter direction do not completely overlap. Based on this, Figure 10 The shielding ring 300 shown is designed to prevent the exposed top surface of the Taiko ring, which has the same morphology as the first and second hollow rings H1 and H2, from being covered by the first metal layer 201 after the sputtering process. Therefore, when the electroplated film 202 is applied to the back side of the wafer 200, the spaced and staggered top surfaces of the Taiko rings T further enhance the adhesion stability between them, reducing the likelihood of bulging and peeling of the electroplated film 202 during the electroplating process, ensuring process effectiveness, and improving device yield.

[0063] Based on the same concept, in other examples, such as Figure 11 and Figure 12 As shown, the inner annular shape of the shielding ring 300 is serrated, so that one side of the inner ring of the portion of the top surface of the Taiko ring T not covered by the first metal layer 201 facing the top surface of the Taiko ring T is also serrated. That is, the inner annular shape of the shielding region E is not a complete circle, but is serrated, which can increase the roughness of the shielding region E itself and improve the adhesion stability of the chemical coating. Figure 11The inner ring of the shielding ring 300 shown is a strictly symmetrical, regularly serrated shape. However, this embodiment does not limit the shape of the inner ring of the shielding ring 300 to a symmetrical, regular shape or an irregular shape. Therefore, in other examples, the inner ring of the shielding ring 300 can also be irregular, such as wavy, petal-shaped, or other asymmetrical shapes. Preferably, based on the inner ring of the shielding ring 300 being serrated or irregular, the ring surface of the shielding ring 300 can also simultaneously have multiple hollow areas; that is, constituting... Figure 10 and Figure 11 The combined morphology further ensures that the electroplating film 202 can be completely and firmly adhered to the back side of the wafer 200 during the electroplating process, avoiding the problem of back-side liquid seepage and improving the electroplating process effect.

[0064] Please continue reading. Figure 7 In the Z-axis direction, there is a certain gap between the shielding ring 300 and the wafer 200 within the bearing groove 301. The size of this gap can be adaptively adjusted according to the sputtering angle of the sputtering process and the area to be shielded by the Taiko ring T, so that the shielded area of ​​the Taiko ring T reaches a preset requirement, thereby ensuring the adhesion stability and reliability of the chemical coating in subsequent processes. And, as... Figure 12 As shown, based on the shielding of the shielding ring 300, after the sputtering process, the annular region on the top surface of the Taiko ring T near the outer ring is not covered by the first metal layer 201, while the remaining annular region on the top surface of the Taiko ring T near the inner ring is covered by the first metal layer 201. To balance the area of ​​the back gold region of the first metal layer 201 and the adhesion stability of the electroplated film, preferably, the width of the annular region on the top surface of the Taiko ring not covered by the first metal layer 201 is greater than or equal to 10% of the width of the top surface of the Taiko ring T, and less than the width of the top surface of the Taiko ring T. The width of the annular region on the top surface of the Taiko ring T not covered by the first metal layer 201 is denoted as the first annular width d1, and the width of the top surface of the Taiko ring is denoted as the second annular width d2, where d2 > d1 ≥ 10%d2.

[0065] Preferably, a magnetron sputtering deposition system is used to perform the sputtering process to form the first metal layer 201. The material of the first metal layer 201 includes, but is not limited to, one or more of gold, silver, nickel, titanium, tungsten, and platinum. Furthermore, the first metal layer 201 covers the central region C, the inner ring sidewall of the Taiko ring T, and extends to cover a portion of the top surface of the Taiko ring T that is in contact with the inner ring sidewall of the Taiko ring T.

[0066] Step 3 S30: Please refer to Figure 13 A chemical coating 202 is applied to the top surface of the portion of the Taiko ring T that is not covered by the first metal layer 201 and to the first metal layer 201.

[0067] After the sputtering process, the wafer 200 is removed from the sputtering machine, separating it from the shielding ring 300. Due to the shielding effect of the shielding ring 300, a portion of the top surface of the Taiko ring T is not covered by the first metal layer 201, allowing the electroless coating 202 to adhere to this portion of the top surface; that is, to directly contact the silicon material of the Taiko ring T. Because the roughness of the silicon material of the Taiko ring T is much greater than the roughness of the first metal layer 201, the adhesion of the electroless coating 202 to the silicon material of the Taiko ring T is also greater than its adhesion to the first metal layer 201. Furthermore, if the top surface of the Taiko ring T, which is not covered by the first metal layer 201, surrounds the outer perimeter of the wafer 200, the electroplating film 202 can firmly adhere and cover the outermost ring of the back side of the wafer 200, effectively improving the stability of the electroplating film 202 and avoiding problems such as bulging or peeling of the electroplating film 202 in subsequent electroplating processes, which is conducive to ensuring better electroplating process results.

[0068] like Figure 13 As shown, because the side of the Taiko ring T near the central region C on the back side of the wafer 200 is stepped, that is, there is a height difference between the top surface of the Taiko ring T and the top surface of the central region C on the back side of the wafer 200, the electroplating film 202 applied to the top surface of the Taiko ring T and the top surface of the central region C on the back side of the wafer 200 will completely cover the Taiko ring T and a portion of the back side of the wafer 200 adjacent to the Taiko ring T; and the inner ring sidewall of the Taiko ring T and the surface of the portion of the central region C adjacent to the inner ring sidewall of the Taiko ring T are covered by the electroplating film 202 to form a sealed cavity S. It can be understood that, based on the stable adhesion between the electroplating film 202 and the silicon material of the Taiko ring, the sealed cavity S also has strong stability, avoiding the penetration of plating solution in subsequent electroplating processes, which could cause problems such as peeling and damage to the electroplating film 202.

[0069] Preferably, the chemical coating 202 has strong adhesiveness, and its material includes, but is not limited to, polyimide, polyester silicone resin or epoxy resin.

[0070] Step 4S40: Perform a chemical plating process on the front side of the wafer 200 to form a second metal layer (not shown).

[0071] After completing the protective covering of the non-chemical plating area, that is, covering the back side of the wafer 200 with the chemical plating film 202, the wafer 200 can be immersed in the chemical plating solution to achieve coating deposition on the front side of the wafer 200 through liquid phase chemical reaction and form the required second metal layer.

[0072] Based on the same concept, this embodiment also provides a semiconductor device. Please refer to... Figure 13 The semiconductor device includes a wafer 200, a first metal layer 201, and a second metal layer; and a Taiko ring T is formed on the edge of the back side of the wafer 200; and the first metal layer 201 and the second metal layer are fabricated using the above-described semiconductor device fabrication method and are located on the back side and front side of the wafer 200, respectively.

[0073] In this process, the first metal layer 201 covers the central region C on the back side of the wafer 200, extending to cover the inner ring sidewall and part of the top surface of the Taiko ring T, thus exposing the remaining top surface of the Taiko ring T. The second metal layer covers the front side of the wafer 200. During the fabrication of the second metal layer, a chemical plating film 202 is first applied to the exposed remaining top surface of the Taiko ring T and the first metal layer 201, and then the wafer 200 is immersed in the chemical plating solution to form the second metal layer. Due to the strong adhesion between the chemical plating film 202 and the exposed remaining top surface of the Taiko ring T, the chemical plating film 202 can firmly adhere to the back side of the wafer 200 throughout the entire chemical plating process, ensuring the effectiveness of the chemical plating process, avoiding back-side seepage problems, and improving device yield.

[0074] It should be noted that the semiconductor device referred to in this embodiment can be an IGBT chip device before it is packaged and cut, or it can be other types of semiconductor devices.

[0075] In summary, the semiconductor device and its fabrication method provided in this embodiment, during the formation of the first metal layer 201, employs a shielding ring 300 to shield a portion of the top surface of the Taiko ring T along its periphery. This prevents the portion of the top surface of the Taiko ring T shielded by the shielding ring 300 from metal sputtering and thus from being covered by the first metal layer 201. That is, a portion of the top surface of the Taiko ring T is covered by the first metal layer 201, while the remaining portion of the top surface remains exposed. Based on this, when the electroplating film 202 is applied, the electroplating film 202 not only covers the first metal layer 201 but also adheres to the exposed portion of the top surface of the Taiko ring T. Furthermore, since the top surface of the Taiko ring T has a relatively large roughness, the chemical plating film 202 is adhered to the exposed top surface of the Taiko ring T. This helps to improve the adhesion stability between the chemical plating film 202 and the Taiko ring T, ensuring that the chemical plating film 202 can be completely and firmly adhered to the back side of the wafer 200 during the chemical plating process. This avoids the problem of back-side liquid seepage, ensures the effect of the chemical plating process, and improves the device yield.

[0076] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A wafer is provided, wherein a Taiko ring is formed on the back side of the wafer and is disposed around the edge of the wafer; A shielding ring is used to shield a portion of the top surface of the Taiko ring around its perimeter, and a sputtering process is performed on the remaining area of ​​the back side of the wafer to form a first metal layer; wherein the portion of the top surface of the Taiko ring shielded by the shielding ring is not covered by the first metal layer; A chemical coating is applied to the top surface of the portion of the Taiko ring not covered by the first metal layer and to the first metal layer; A chemical plating process is performed on the front side of the wafer to form a second metal layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The roughness of the top surface of the Taiko ring is greater than the roughness of the surface of the first metal layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The adhesion of the chemically coated film to the top surface of the Taiko ring is greater than the adhesion of the chemically coated film to the surface of the first metal layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The portion of the top surface of the Taiko ring not covered by the first metal layer is annular, and the ring width of the portion of the top surface of the Taiko ring not covered by the first metal layer is greater than or equal to 10% of the ring width of the top surface of the Taiko ring, and less than the ring width of the top surface of the Taiko ring.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The shielding ring shields the outer ring of the top surface of the Taiko ring and extends toward the inner ring of the top surface of the Taiko ring to shield an annular area of ​​a predetermined ring width.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The top surface of the shielding ring is hollowed out and has multiple spaced-apart hollowed-out areas; wherein, After the sputtering process is performed, each of the hollowed-out areas is covered by the first metal layer on the top surface of the Taiko ring relative to the portion of the top surface of the Taiko ring that is shielded by the shielding ring, so that the portion of the top surface of the Taiko ring that is shielded by the shielding ring is discontinuous.

7. The method for fabricating a semiconductor device according to claim 6, wherein within the top surface of the shielding ring, each of the hollowed-out regions is arranged circumferentially along the shielding ring and forms at least one hollowed-out ring; and, When the number of the hollow rings is greater than or equal to 2, the hollow rings are concentrically distributed; and in the radial direction of the shielding ring, the hollow areas within the hollow rings are staggered.

8. The method for fabricating a semiconductor device according to any one of claims 1 to 7, characterized in that, The inner ring of the shielding ring is serrated or irregular in shape, so that one side of the inner ring of the Taiko ring, which is not covered by the first metal layer, is also serrated or irregular in shape.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, On the back side of the wafer, a portion of the back side of the wafer surrounded by the Taiko ring is the central region; and after the chemical coating is applied, the inner ring sidewall of the Taiko ring and the surface of the central region adjacent to the inner ring sidewall of the Taiko ring are wrapped by the chemical coating to form a sealed cavity.

10. A semiconductor device, characterized in that, include: The wafer and a first metal layer and a second metal layer located on the back and front sides of the wafer, respectively; wherein, a Taiko ring is formed on the back side of the wafer and surrounding the edge of the wafer, and the first metal layer and the second metal layer are fabricated using the semiconductor device fabrication method according to any one of claims 1 to 9.

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