Novel integrated circuit exposure method
By dividing the wafer exposure field into several exposure units and stitching the photomasks together, the problem of photomask size being limited by the maximum effective exposure field of the lithography machine is solved. This enables normal exposure of large-size wafers and precise transfer of chip patterns, meeting the requirements of high integration and large-size interposers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-10
AI Technical Summary
The maximum effective exposure field of existing lithography machines limits the size of the photomask, which means that normal packaging cannot be performed when the wafer exposure field size exceeds the maximum photomask capacity of the machine. Especially with the increasing demand for multi-chip designs and large-size interposers, the size limitations of traditional photomasks and stepper lithography machines have become a bottleneck for bump packaging.
The wafer exposure field is divided into several exposure units, each containing an integer multiple of the number of chips. Exposure is completed by stitching photomasks together, ensuring that the size of each unit is within the maximum photomask range of the machine. The photomask position is adjusted by coordinate calculation and alignment marks are set to achieve overall stitching.
It effectively solves the problem of photomask size limitation, realizes normal exposure of large-size wafers, ensures accurate transfer of chip patterns, avoids pattern misalignment and overlap defects, and meets the needs of high integration and large-size interposer layers.
Smart Images
Figure CN121832207A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a novel integrated circuit exposure method. BACKGROUND
[0002] The bump package uses a stepper photolithography machine, and when photolithography is performed, the wafer is divided into exposure fields according to the mask size, and the mask pattern is sequentially projected onto the wafer according to the exposure field sequence. One exposure field is equal to one mask size, and the maximum effective exposure field of the photolithography machine limits the mask size and further affects the wafer exposure field size. When the wafer is a multi-chip (two or more different design chips in one exposure field) design product, and when the exposure field size of the product exceeds the maximum mask capacity of the machine, the chips in the range of the exceeded mask size cannot be exposed, resulting in that the chips cannot be normally bump packaged.
[0003] The exposure field size of the product exceeding the maximum mask capacity of the machine is as follows: 1. both the X and Y directions exceed the maximum mask capacity of the machine; 2. only the X direction exceeds the maximum mask capacity of the machine, and the Y direction is normal; and 3. only the Y direction exceeds the maximum mask capacity of the machine, and the X direction is normal.
[0004] With the continuous improvement of the requirement for integration of chip and high-performance computing (HPC) products, the number of functional chips to be accommodated in a single exposure field is continuously increasing, and the exposure field size is continuously increasing. The size limitation of the traditional mask and the stepper photolithography machine has become a core technical bottleneck of the bump packaging process. At the same time, the popularization of advanced packaging technologies such as fan-out wafer-level packaging and panel-level packaging has led to a surge in demand for large-size interposers, further forcing the exposure field size to break through the limitation of the existing equipment. SUMMARY
[0005] In view of the above situation, in order to overcome the defects of the prior art, the application provides a novel integrated circuit exposure method, which effectively solves the problem that the maximum effective exposure field of the photolithography machine limits the mask size and further affects the wafer Shot size. When the wafer is a multi-chip design product, and when the exposure field size of the product exceeds the maximum mask capacity of the machine, the machine cannot perform exposure.
[0006] The technical scheme adopted by the application is as follows: the application provides a novel integrated circuit exposure method, which comprises the following steps: step one: setting the step moving amount of the machine according to the size of the target exposure area of the wafer, setting the X direction size of the target exposure area of the wafer as M, and setting the Y direction size as N;
[0007] Step two: split the wafer target exposure area into several groups of exposure units, the X and Y directions of the exposure units should contain an integer multiple of the number of chips, split the wafer target exposure area range into corresponding several groups of masks, the masks correspond to the exposure units, the X and Y directions of the masks should be an integer multiple of one or more chip numbers, and the splicing of the masks is arranged in the cutting path, and the position of the cutting path is not windowed.
[0008] Step three: adjust the position of each mask to the corresponding exposure unit through coordinate calculation, complete the splicing of the exposure area, and repeat the above operation to complete the overall splicing of the wafer target exposure area.
[0009] Step four: select the unique pattern of the center of the cutting path of the wafer target exposure area as the alignment mark, and set the alignment coordinates.
[0010] Step five: exposure and development.
[0011] Preferably, in step four, the setting method of the alignment coordinates is: the coordinates of the upper right corner alignment mark are (M / 2, N / 2), the coordinates of the lower right corner alignment mark are (M / 2, -N / 2), the coordinates of the upper left corner alignment mark are (-M / 2, N / 2), and the coordinates of the lower left corner alignment mark are (-M / 2, -N / 2).
[0012] Preferably, in step four, the alignment mark is selected on the four corners of the wafer target exposure area.
[0013] Preferably, in step two, the splitting method of the wafer target exposure area includes splitting methods of the wafer target exposure area exceeding the maximum exposure area of the machine in the X direction, the wafer target exposure area exceeding the maximum exposure area of the machine in the Y direction, and the wafer target exposure area exceeding the maximum exposure area of the machine in the X / Y direction.
[0014] Preferably, the splitting method of the wafer target exposure area exceeding the maximum exposure area of the machine in the X direction is:
[0015] Suppose the X direction size of the maximum exposure area of the machine is M-X, and the Y direction size is M-Y, and suppose the wafer target exposure area is X direction size S-X and Y direction size S-Y.
[0016] When the X-direction size of the wafer target exposure area and the X-direction size of the maximum exposure area of the machine are S-X > M-X, and the Y-direction size of the wafer target exposure area and the Y-direction size of the maximum exposure area of the machine are S-Y < M-Y, the maximum exposure area of the machine is split into two exposure units, i.e., exposure unit one and exposure unit two, along the X-direction, the exposure unit one and the exposure unit two correspond to mask one and mask two respectively, and the entire wafer is exposed by sequentially performing mask splicing on the wafer target exposure area.
[0017] Preferably, the X-direction sizes S-X1 and S-X2 of the two exposure units satisfy S-X1 + S-X2 = S-X, and the sizes of X1 and X2 are integer multiples of one or more chip numbers, ensuring that the splicing position is located in the scribe lane.
[0018] Preferably, the splitting method of the Y-direction of the wafer target exposure area beyond the maximum exposure area of the machine is:
[0019] When the Y-direction size of the wafer target exposure area and the Y-direction size of the maximum exposure area of the machine are S-Y > M-Y, and the X-direction size of the wafer target exposure area and the X-direction size of the maximum exposure area of the machine are S-X < M-X, the maximum exposure area of the machine is split into two exposure units, i.e., exposure unit three and exposure unit four, along the Y-direction, the exposure unit three and the exposure unit four correspond to mask three and mask four respectively, and the wafer target exposure area is exposed by sequentially performing mask splicing.
[0020] Preferably, the Y-direction sizes S-Y1 and S-Y2 of the two exposure units satisfy S-Y1 + S-Y2 = S-Y, and S-Y1 and S-Y2 are integer multiples of chip numbers.
[0021] Preferably, the splitting method of the X / Y-direction of the wafer target exposure area beyond the maximum exposure area of the machine is:
[0022] When the X-direction size of the wafer target exposure area and the X-direction size of the maximum exposure area of the machine are S-X > M-X, and the Y-direction size of the wafer target exposure area and the Y-direction size of the maximum exposure area of the machine are S-Y > M-Y, the wafer target exposure area is split into four exposure units, i.e., exposure unit five, exposure unit six, exposure unit seven, and exposure unit eight, along the X-direction and the Y-direction, the exposure unit five, the exposure unit six, the exposure unit seven, and the exposure unit eight correspond to mask five, mask six, mask seven, and mask eight respectively.
[0023] Preferably, the X-directional sizes S-X1, S-X2, S-X3 and S-X4 of the four exposure units satisfy S-X1+S-X2+S-X3+S-X4=S-X, the Y-directional sizes S-Y1, S-Y2, S-Y3 and S-Y4 satisfy S-Y1+S-Y2+S-Y3+S-Y4=S-Y, and S-X1~S-X4 and S-Y1~S-Y4 are all integral multiples of the number of chips.
[0024] The beneficial effects achieved by the application with the above structure are as follows: the present application proposes a novel integrated circuit exposure method, which uses a mask splicing exposure method to complete the exposure of the special wafer. The wafer exposure field is divided into several small exposure units, the exposure units X and Y after splitting need to contain an integral multiple of the number of chips, and the sizes of the final exposure units X and Y need to be within the range of the maximum mask of the machine. One exposure unit corresponds to one mask, and several exposure units correspond to several masks. The masks are spliced according to the positions of the exposure units to fill the entire exposure unit. Each mask is exposed in turn during exposure, and the exposure of the entire exposure field is completed. From the structure of the back-end bump packaging, the size of two maximum masks in one direction is sufficient, so one exposure field is generally divided into two masks or four masks. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 A schematic diagram of a wafer target exposure area exceeding the maximum exposure area of a machine for a novel integrated circuit exposure method proposed by the application;
[0026] Figure 2 A splitting schematic diagram of a wafer target exposure area for a novel integrated circuit exposure method proposed by the application;
[0027] Figure 3 A corresponding mask splicing schematic diagram for a novel integrated circuit exposure method proposed by the application;
[0028] Figure 4 A mask splicing exposure schematic diagram for a novel integrated circuit exposure method proposed by the application;
[0029] Figure 5 A wafer target exposure area splitting into masks schematic diagram for a novel integrated circuit exposure method proposed by the application;
[0030] Figure 6 A mask one adjustment to exposure unit one schematic diagram for a novel integrated circuit exposure method proposed by the application;
[0031] Figure 7 A mask two adjustment to exposure unit two schematic diagram for a novel integrated circuit exposure method proposed by the application;
[0032] Figure 8 A wafer target exposure area Y direction exceeds the maximum exposure area of the machine table schematic diagram of a new integrated circuit exposure method proposed in the application;
[0033] Figure 9 A wafer target exposure area splitting schematic diagram of a new integrated circuit exposure method proposed in the application;
[0034] Figure 10 A corresponding mask splicing schematic diagram of a new integrated circuit exposure method proposed in the application;
[0035] Figure 11 A mask splicing exposure schematic diagram of a new integrated circuit exposure method proposed in the application;
[0036] Figure 12 A wafer target exposure area splitting into a mask schematic diagram of a new integrated circuit exposure method proposed in the application;
[0037] Figure 13 A mask three adjustment to exposure unit three schematic diagram of a new integrated circuit exposure method proposed in the application;
[0038] Figure 14 A mask four adjustment to exposure unit four schematic diagram of a new integrated circuit exposure method proposed in the application;
[0039] Figure 15 A wafer target exposure area X and Y direction exceeds the maximum exposure area of the machine table schematic diagram of a new integrated circuit exposure method proposed in the application;
[0040] Figure 16 A wafer target exposure area splitting schematic diagram of a new integrated circuit exposure method proposed in the application;
[0041] Figure 17 A corresponding mask splicing schematic diagram of a new integrated circuit exposure method proposed in the application;
[0042] Figure 18 A mask splicing exposure schematic diagram of a new integrated circuit exposure method proposed in the application;
[0043] Figure 19 A wafer target exposure area splitting into a mask schematic diagram of a new integrated circuit exposure method proposed in the application;
[0044] Figure 20 A mask five adjustment to exposure unit five schematic diagram of a new integrated circuit exposure method proposed in the application;
[0045] Figure 21A mask six adjustment to exposure unit six schematic view of a novel integrated circuit exposure method proposed in the present application;
[0046] Figure 22 A mask seven adjustment to exposure unit seven schematic view of a novel integrated circuit exposure method proposed in the present application;
[0047] Figure 23 A mask eight adjustment to exposure unit eight schematic view of a novel integrated circuit exposure method proposed in the present application;
[0048] Figure 24 An exposure area coordinate schematic view of a novel integrated circuit exposure method proposed in the present application.
[0049] 1, wafer target exposure area; 11, machine maximum exposure area; 12, exposure unit one; 13, exposure unit two; 14, exposure unit three; 15, exposure unit four; 16, exposure unit five; 17, exposure unit six; 18, exposure unit seven; 19, exposure unit eight; 2, mask one; 21, mask two; 23, mask three; 24, mask four; 25, mask five; 26, mask six; 27, mask seven; 28, mask eight.
[0050] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with embodiments of the present application, and do not constitute a limitation on the present application. DETAILED DESCRIPTION
[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0052] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0053] As Figures 1-24As shown, the present invention proposes a novel integrated circuit exposure method, including step one: according to the actual product size requirements of the target exposure area 1 of the wafer, the stepping movement amount of the machine is set: the overall size of the target exposure area 1 of the wafer in the X direction is defined as M and the overall size in the Y direction is defined as N, which are used as the reference size for subsequent area splitting and photomask splicing to ensure that the machine movement path matches the exposure area.
[0054] Step 2: Set the relevant information for each photomask to be split in the target exposure area 1 of the wafer, and split the target exposure area 1 of the wafer into several exposure units. The X and Y directions of each exposure unit must contain an integer multiple of the number of chips, such as Die1-X*number N+Die2-X*number N+...DieN-X*number N, and finally the X and Y dimensions of each exposure unit are within the range of the target exposure area 1 of the wafer.
[0055] Each exposure unit corresponds to an independent photomask, meaning it is divided into several exposure units corresponding to several photomasks. The X and Y dimensions of the photomasks must be integer multiples of the number of one or more chips, satisfying the following condition: Die1-X number N + Die2-X number N + ... + Die... n -X*Quantity N.
[0056] It should be noted that all photomask splicing points must be precisely positioned within the cutting channel. The cutting channel area has no product window pattern, and splicing at this point will not interfere with the chip pattern, thereby avoiding defects such as pattern misalignment and overlap.
[0057] Step 3: Adjust the position of each photomask to the corresponding exposure unit using coordinate calculations to complete the stitching of the target exposure area 1 of a single wafer. Repeat this operation to complete the stitching of all exposure units on the entire wafer. The specific method for splitting the target exposure area 1 of the wafer needs to be determined based on the dimensional relationship between the target exposure area 1 of the wafer and the maximum exposure area 11 of the machine.
[0058] Let the X-direction dimension of the maximum exposure area 11 of the machine be MX, and the Y-direction dimension be MY. Let the X-direction dimension of the target exposure area 1 of the wafer be SX, and the Y-direction dimension be SY.
[0059] like Figures 1-4 As shown, the splitting method includes when the X-direction dimension of the target exposure area 1 of the wafer exceeds the X-direction limit of the maximum exposure area 11 of the machine, but does not exceed it in the Y-direction:
[0060] Split the wafer target exposure area 1 along the X direction into two exposure units, namely exposure unit one 12 and exposure unit two 13, exposure unit one 12 and exposure unit two 13 correspond to independent mask one 2 and mask two 21 respectively, the X direction size S-X1, S-X2 of the two exposure units needs to meet S-X1+S-X2=S-X, that is, the total size after splitting is consistent with the X direction size of the original machine table maximum exposure area 11, and S-X1, S-X2 are both integer multiples of the chip quantity, at the same time, the Y direction size of both is consistent with the Y direction size S-Y of the machine table maximum exposure area 11.
[0061] As shown in the figure, Figures 5-7 , the coordinate adjustment mode takes the splicing of two masks in the X direction as an example:
[0062] Suppose the X direction size of the wafer target exposure area 1 is M and the Y direction size is N;
[0063] Split the wafer target exposure area 1 into two groups of exposure units, and the two groups of exposure units correspond to mask one 2 and mask two 21 respectively, suppose the X direction size of mask one 2 is M1 and the Y direction size is N, suppose the X direction size of 13 is M2 and the Y direction size is N, M1 and M2 meet M1+M2=M, M1&M2<M.
[0064] a: first adjust mask one 2 to the position corresponding to exposure unit one 12: the X direction moving distance is-(M-M1) / 2, and the Y direction moving distance is 0;
[0065] b: adjust mask two 21 to the position corresponding to exposure unit two 13: the X direction moving distance is (M-M1) / 2, and the Y direction moving distance is 0;
[0066] c: complete the splicing of all wafer target exposure areas 1 of the whole wafer according to a and b.
[0067] As shown in the figure, Figures 8-11 , when the Y direction size of the wafer target exposure area 1 exceeds the Y direction limit of the machine table maximum exposure area 11, but the X direction does not exceed:
[0068] Split the wafer target exposure area 1 along the Y direction into two exposure units, namely exposure unit three 14 and exposure unit four 15, exposure unit three 14 and exposure unit four 15 correspond to independent mask three 23 and mask four 24 respectively, the Y direction size S-Y1, S-Y2 of the two exposure units needs to meet S-Y1+S-Y2=S-Y, and S-Y1, S-Y2 are both integer multiples of the chip quantity, at the same time, the X direction size of both is consistent with the X direction size S-X of the machine table maximum exposure area 11.
[0069] As shown in the figure, Figures 12-14 , the coordinate adjustment mode takes the splicing of two masks in the Y direction as an example:
[0070] Let the dimension of the target exposure area 1 on the wafer be M in the X direction and the dimension in the Y direction be N;
[0071] The wafer target exposure area 1 is divided into two sets of exposure units, and the two sets of exposure units correspond to photomask 3 23 and photomask 4 24 respectively. Let the X-direction dimension of photomask 3 23 be M and the Y-direction dimension be N1; let the X-direction dimension of photomask 4 24 be M and the Y-direction dimension be N2; N1 and N2 satisfy N1+N2=N and N1&N2<N.
[0072] a: First, adjust the photomask 323 to the position of the corresponding exposure unit 314: the X-direction movement distance is 0, and the Y-direction movement distance is (N-N1) / 2;
[0073] b: Then adjust the photomask 24 to the position of the corresponding exposure unit 15: the X-direction movement distance is 0, and the Y-direction movement distance is -(N-N1) / 2;
[0074] c: Complete the splicing of all wafer target exposure areas 1 according to a and c.
[0075] like Figures 15-18 As shown, when the dimensions of the target exposure area 1 in both the X and Y directions exceed the limit of the maximum exposure area 11 of the machine:
[0076] The target exposure area 1 of the wafer is divided into four exposure units along the X and Y directions: exposure unit 5 (16), exposure unit 6 (17), exposure unit 7 (18), and exposure unit 8 (19). Exposure units 5 (16), 6 (17), 7 (18), and 8 (19) correspond to photomask 5 (25), photomask 6 (26), photomask 7 (27), and photomask 8 (28), respectively. The X-direction dimensions S-X1, S-X2, S-X3, and S-X4 of the four exposure units must satisfy S-X1 + S-X2 + S-X3 + S-X4 = SX. The Y-direction dimensions S-Y1, S-Y2, S-Y3, and S-Y4 of the four exposure units must satisfy S-Y1 + S-Y2 + S-Y3 + S-Y4 = SY, and S-X1~S-X4 and S-Y1~S-Y4 are all integer multiples of the number of chips.
[0077] like Figures 19-23 As shown, the coordinate adjustment method is based on the splicing of four photomasks as an example:
[0078] Let the dimension of the target exposure area 1 on the wafer be M in the X direction and the dimension in the Y direction be N;
[0079] The wafer target exposure area 1 is divided into four groups of exposure units, and the four groups of exposure units correspond to the mask five 25, the mask six 26, the mask seven 27 and the mask eight 28 respectively. The X direction size of the mask five 25 is M1, and the Y direction size is N1. The X direction size of the mask six 26 is M2, and the Y direction size is N2. The X direction size of the mask seven 27 is M3, and the Y direction size is N3. The X direction size of the mask eight 28 is M4, and the Y direction size is N4. The X and Y direction sizes of the four groups of masks satisfy M1+M2+M3+M4=M, M1&M2&M3&M4<M, N1+N2+N3+N4=N, N1&N2&N3&N4<N.
[0080] The coordinate adjustment mode takes four masks spliced as an example:
[0081] a: The mask five 25 is adjusted to the position corresponding to the exposure unit five 16: the X direction moving distance is -(M-M1) / 2, and the Y direction moving distance is -(N-N1) / 2;
[0082] b: The mask six 26 is adjusted to the position corresponding to the exposure unit six 17: the X direction moving distance is (M-M2) / 2, and the Y direction moving distance is (N-N1) / 2;
[0083] c: The mask seven 27 is adjusted to the position corresponding to the exposure unit seven 18: the X direction moving distance is -(M-M3) / 2, and the Y direction moving distance is -(N-N3) / 2;
[0084] d: The mask eight 28 is adjusted to the position corresponding to the exposure unit eight 19: the X direction moving distance is -(M-M4) / 2, and the Y direction moving distance is -(N-N4) / 2;
[0085] e: According to a to b, the splicing of all wafer target exposure areas 1 of the whole wafer is completed.
[0086] As shown in the figure, Figure 24 Step four: select the unique pattern of the cutting path center of the wafer target exposure area 1 as the alignment mark. The alignment mark needs to be selected on the four corners of the wafer target exposure area 1. The selected pattern is unique to the exposure area, which avoids confusion with other area marks.
[0087] The accurate alignment coordinates are set according to the following rules:
[0088] The coordinates of the upper right corner alignment mark are (M / 2, N / 2);
[0089] The coordinates of the lower right corner alignment mark are (M / 2, -N / 2);
[0090] The coordinates of the upper left corner alignment mark are (-M / 2, N / 2);
[0091] The coordinates of the lower left corner alignment mark are (-M / 2, -N / 2);
[0092] Through the coordinate setting, the position of each wafer target exposure area 1 can be accurately identified by the machine, and exposure misalignment is avoided.
[0093] Step five: after the splicing adjustment and alignment mark setting of all masks are completed, the exposure process of the machine is started: the machine moves according to the set step movement amount in turn, and exposes the exposure unit corresponding to each mask. After exposure, the unexposed photoresist is dissolved by developing solution to realize pattern transfer, and finally the pattern preparation of the whole wafer target exposure area is completed.
[0094] It should be noted that in the current process, before PR exposure, the edge invalid wafer area is not exposed by means of the WEP (Wafer edge Protect) function of the photoetch machine, and the other areas of the wafer are normally exposed. Since it is a positive photoresist, the edge invalid area will not be exposed after being shielded by the ring, the edge invalid area will not be windowed, and the photoresist will not be broken during the pressing of the electroplating clamp, and there will be no plating leakage after electroplating.
[0095] It should be noted that in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment.
[0096] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.
[0097] The above describes the present application and its embodiments, which are not restrictive, and the embodiments shown in the drawings are only one of the embodiments of the present application, and the actual structure is not limited thereto. In general, if a person skilled in the art is inspired by it, without departing from the purpose of the present application, without creative design, similar structure and embodiments of the technical solution can be designed, which should belong to the protection scope of the present application.
Claims
1. A novel integrated circuit exposure method characterized by: The exposure method comprises the following steps: Step 1: Set the stepping movement amount of the machine according to the size of the wafer target exposure area (1), set the X direction size of the wafer target exposure area (1) as M and the Y direction size as N; Step 2: Split the wafer target exposure area (1) into a plurality of exposure units, the X and Y directions of the exposure units need to contain an integer multiple of the number of chips, split the range of the wafer target exposure area (1) into a plurality of corresponding mask groups, the mask groups correspond to the exposure units, the X and Y direction sizes of the mask groups need to be an integer multiple of one or more chip numbers, and the splicing position of the mask groups is set in the cutting path, and the position of the cutting path is not provided with a window pattern; Step 3: Adjust the position of each mask group to the corresponding exposure unit through coordinate calculation, complete the splicing of the exposure area, and repeat the above operation to complete the overall splicing of the wafer target exposure area (1); Step 4: Select the unique pattern at the center of the cutting path of the wafer target exposure area (1) as the alignment mark, and set the alignment coordinates; Step 5: Expose and develop.
2. The novel integrated circuit exposure method according to claim 1, wherein: In step 4, the setting method of the alignment coordinates is that the coordinates of the upper right corner alignment mark are (M / 2, N / 2), the coordinates of the lower right corner alignment mark are (M / 2, -N / 2), the coordinates of the upper left corner alignment mark are (-M / 2, N / 2), and the coordinates of the lower left corner alignment mark are (-M / 2, -N / 2).
3. The novel integrated circuit exposure method according to claim 1, wherein: In step 4, the alignment marks are selected on the four corners of the wafer target exposure area (1).
4. The novel integrated circuit exposure method according to claim 1, wherein: In step 2, the splitting mode of the wafer target exposure area (1) comprises a splitting mode in which the X direction of the wafer target exposure area (1) exceeds the maximum exposure area (11) of the machine, a splitting mode in which the Y direction of the wafer target exposure area (1) exceeds the maximum exposure area (11) of the machine, and a splitting mode in which the X / Y direction of the wafer target exposure area (1) exceeds the maximum exposure area (11) of the machine.
5. The novel integrated circuit exposure method according to claim 4, wherein: The splitting mode in which the X direction of the wafer target exposure area (1) exceeds the maximum exposure area (11) of the machine is as follows: Set the X direction size of the maximum exposure area (11) of the machine as M-X and the Y direction size as M-Y, set the X direction size of the wafer target exposure area (1) as S-X and the Y direction size as S-Y; When the X-direction size of the wafer target exposure area (1) and the X-direction size of the maximum exposure area (11) of the machine are S-X > M-X, and the Y-direction size of the wafer target exposure area (1) and the Y-direction size of the maximum exposure area (11) of the machine are S-Y < M-Y, the maximum exposure area (11) of the machine is split into two exposure units, i.e. exposure unit one (12) and exposure unit two (13) along the X-direction, the exposure unit one (12) and the exposure unit two (13) correspond to mask one (2) and mask two (21) respectively, and then the entire wafer is exposed according to the wafer target exposure area (1) in sequence.
6. The novel integrated circuit exposure method according to claim 5, characterized in that: The X-direction sizes S-X1 and S-X2 of the two exposure units satisfy S-X1 + S-X2 = S-X, and X1 and X2 are integer multiples of one or more chip quantities, ensuring that the splicing position is arranged in the cutting path.
7. The novel integrated circuit exposure method according to claim 4, characterized in that: The splitting mode of the wafer target exposure area (1) exceeding the maximum exposure area (11) of the machine in the Y-direction is: When the Y-direction size of the wafer target exposure area (1) and the Y-direction size of the maximum exposure area (11) of the machine are S-Y > M-Y, and the X-direction size of the wafer target exposure area (1) and the X-direction size of the maximum exposure area (11) of the machine are S-X < M-X, the maximum exposure area (11) of the machine is split into two exposure units, i.e. exposure unit three (14) and exposure unit four (15) along the Y-direction, the exposure unit three (14) and the exposure unit four (15) correspond to mask three (23) and mask four (24) respectively, and then the wafer target exposure area (1) is exposed in sequence after mask splicing.
8. The novel integrated circuit exposure method according to claim 7, characterized in that: The Y-direction sizes S-Y1 and S-Y2 of the two exposure units satisfy S-Y1 + S-Y2 = S-Y, and S-Y1 and S-Y2 are integer multiples of chip quantities.
9. The novel integrated circuit exposure method according to claim 4, characterized in that: The splitting mode of the wafer target exposure area (1) exceeding the maximum exposure area (11) of the machine in the X / Y-direction is: When the X-direction size of the wafer target exposure area (1) and the X-direction size of the maximum exposure area (11) of the machine are S-X>M-X, and the Y-direction size of the wafer target exposure area (1) and the Y-direction size of the maximum exposure area (11) of the machine are S-Y>M-Y, the wafer target exposure area (1) is split into four exposure units, i.e., exposure unit five (16), exposure unit six (17), exposure unit seven (18), and exposure unit eight (19) along the X-direction and the Y-direction, and the exposure unit five (16), the exposure unit six (17), the exposure unit seven (18), and the exposure unit eight (19) correspond to the mask five (25), the mask six (26), the mask seven (27), and the mask eight (28) respectively.
10. The novel integrated circuit exposure method according to claim 9, characterized in that: The X-direction sizes S-X1, S-X2, S-X3, S-X4 of the four exposure units satisfy S-X1+S-X2+S-X3+S-X4=S-X, the Y-direction sizes S-Y1, S-Y2, S-Y3, S-Y4 satisfy S-Y1+S-Y2+S-Y3+S-Y4=S-Y, and S-X1~S-X4, S-Y1~S-Y4 are all integral multiples of the chip quantity.