Pre-erasing method and device of memory, memory management method and device and storage system

Abstract

The invention discloses a pre-erasing method and device of a memory, a memory management method and device and a storage system, and relates to the technical field of mobile terminals. The method comprises the steps that the memory receives a second erasing instruction sent by a host; the second erasing instruction is responded, pre-erasing operation is executed, and the pre-erasing operation refers to the operation of erasing the block where the written data is located in advance before the memory writing operation is carried out. Therefore, the host can trigger the memory to execute pre-erasure by sending the second erasure instruction, so that the stability risk caused by long-term existence of a pre-erasure block in the memory is avoided.

Description

[0001] Cross-reference to related applications This application is a divisional application of the invention patent application filed on December 6, 2023, with application number 202311672217.2 and title "Memory Management Method, Apparatus, Memory System and Computer-Readable Medium". Technical Field

[0002] This application relates to the field of mobile terminal technology, and more specifically, to a pre-erasure method and apparatus for a memory, a memory management method and apparatus, and a storage system. Background Technology

[0003] Currently, flash memory, especially NAND flash memory, typically requires a pre-erase operation. Generally, when switching to a new block after the current block is full, this type of memory first erases the new block before writing data. Summary of the Invention

[0004] This application proposes a pre-erasure method and apparatus for a memory, a memory management method and apparatus, and a storage system.

[0005] In a first aspect, this application provides a pre-erasure method for a memory, applied to a memory in a storage system, the storage system further including a host, the method comprising: receiving a second erase command sent by the host; and responding to the second erase command by performing a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

[0006] Secondly, this application provides a memory management method applied to a host in a storage system, the storage system further including the memory, the host being connected to the memory, the method comprising: sending a second erase command to the memory, triggering the memory to respond to the second erase command and perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

[0007] Thirdly, this application also provides a pre-erasing device for a memory, applied to a memory in a storage system, wherein the storage system further includes a host, and the device includes a receiving unit and an execution unit. The receiving unit is configured to receive a second erase command sent by the host; the execution unit is configured to respond to the second erase command and perform a pre-erasing operation, wherein the pre-erasing operation refers to the operation of erasing the block containing the data to be written before performing a memory write operation. Fourthly, this application also provides a memory management device applied to a host in a storage system, the storage system further including the memory, the host being connected to the memory, the device comprising: a sending unit, configured to send a second erase command to the memory, triggering the memory to respond to the second erase command and perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

[0008] Fifthly, this application also provides a storage system, including: a host; a memory; wherein the host is connected to the memory, and the host is used to send a second erase command to the memory; the memory is used to receive the second erase command sent by the host, and in response to the second erase command, to perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

[0009] The pre-erasure method and apparatus, memory management method and apparatus, and storage system provided in this application enable the memory to receive a second erase command sent by the host. Then, in response to the second erase command, the memory performs a pre-erasure operation. The pre-erasure operation refers to erasing the block containing the data to be written before performing a memory write operation. Therefore, the host can trigger the memory to perform pre-erasure by sending a second erase command, avoiding the long-term presence of pre-erasable blocks in the memory and thus preventing stability risks.

[0010] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the storage system provided in an embodiment of this application is shown; Figure 2 A flowchart of a memory management method provided in an embodiment of this application is shown; Figure 3 A schematic diagram illustrating the interaction between automatic mode and active mode provided in another embodiment of this application is shown; Figure 4 This illustration shows the effects of automatic mode and active mode provided in another embodiment of this application; Figure 5 A schematic diagram of the UPIP format provided in an embodiment of this application is shown; Figure 6 A schematic diagram of an EHS field provided in an embodiment of this application is shown; Figure 7 A flowchart of a memory management method according to another embodiment of this application is shown; Figure 8 It shows Figure 7 A schematic diagram of step S780 in the diagram; Figure 9 A block diagram of a memory management device according to an embodiment of this application is shown; Figure 10 An embodiment of the present application shows a storage unit for storing or carrying program code that implements the method according to the embodiment of the present application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0014] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0015] Currently, flash memory, especially NAND flash memory, typically requires a pre-erase operation. In host systems using universal flash storage (UFS) as the storage device, the UFS firmware manages the NAND flash media in units of virtual blocks (VBs). When a UFS device switches to a new block after the current block is full, it first erases the new block (at the millisecond level) before writing data. This is because the erased media has poor stability and cannot be used for data writing after a certain period.

[0016] Pre-erase operation refers to the process of erasing the block containing the data to be written to before performing a write operation on a flash memory. This process is typically managed and executed by the controller. In NAND flash memory, data can only be erased and written in blocks. Therefore, if new data is to be written to a block that already contains old data, the entire block must be erased first, and then the write operation can be performed. This results in an operation flow called "Erase-Write". The purpose of the pre-erase operation is to erase the block containing the data before performing the actual write operation to reduce write latency. In this way, the controller does not need to perform an erase operation during the actual write operation, thereby speeding up the memory write speed and reducing the possibility of errors during writing. In practical applications, for flash memory, the pre-erase operation is usually managed and executed by the controller. When the controller receives a write operation request, it checks whether the block containing the data has been erased. If the block has not been erased, the controller will automatically perform an erase operation before performing the write operation.

[0017] Due to the erase-before-write strategy described above, flash memory (e.g., UFS devices) will always experience a period of time, on the order of milliseconds, where writing is impossible under high write pressure. Therefore, pre-erasing a portion of blocks and reducing the block switching time of UFS can significantly improve the device's write performance while minimizing the maximum latency caused by the erasure action during block switching.

[0018] However, the inventors discovered in their research that current pre-erasing methods typically have the following drawbacks: 1) Relatively Fixed Pre-erase Capacity Threshold: In current device-autonomous pre-erase schemes, the pre-erase capacity is determined by the device itself, and pre-erase to a set threshold is performed during idle periods. To obtain greater performance gains, the threshold should be increased as much as possible; however, considering stability and the possibility of insufficient free blocks, the threshold cannot be too large. Therefore, the device will choose a threshold that strikes a balance between gains and risks. This threshold is relatively fixed and cannot adapt to changes in host write operations.

[0019] 2) Stability risks associated with pre-erased blocks: Currently, devices cannot detect host write operations, and the pre-erasing threshold is relatively fixed, meaning there will always be some pre-erased blocks remaining within the device. If the host does not write to these blocks for a period of time, the pre-erased blocks are prone to stability risks.

[0020] Therefore, setting a reasonable pre-erasure strategy is extremely important.

[0021] To overcome the above-mentioned defects, this application provides a memory management method that can adaptively adjust the pre-erase mode according to the actual data writing situation of the electronic device.

[0022] It should be noted that the memory management method provided in this application is applied to a system composed of a host computer using flash memory, such as... Figure 1 As shown, the storage system 10 includes a host 100 and a memory 200, with the host 100 connected to the memory 200. Exemplarily, the storage system 10 can be an electronic device, such as a smartphone, tablet, e-reader, or other device capable of running applications. In this embodiment, the host 100 is a smartphone's processor (e.g., a central processing unit) or a system-on-a-chip (e.g., an application processor). The memory 200 can be the aforementioned flash memory, for example, UFS.

[0023] It is understood that the memory 200 can be the built-in memory of the host 100, that is, the memory 200 can be integrated into the motherboard of the host 100 and used as the ROM of the mobile phone to store the operating system, applications, and user data. Alternatively, the memory 200 can be an external memory of the host 100, that is, a peripheral device belonging to the host 100. For example, taking the memory 200 as a UFS, the host 100 and the memory 200 are connected via a USB interface. Of course, the UFS storage device can also be designed as a pluggable memory card, similar to a traditional SD card or microSD card. In this way, the user can insert the UFS storage device into the USB interface of the mobile phone for data transfer and access via the USB interface. In the embodiments of this application, there is no limitation on whether the memory 200 is an external or built-in memory of the host 100; the host is used to execute the following embodiments.

[0024] Please see Figure 2 The method is applied to the host mentioned above. For ease of description, the following embodiments use UFS as an example of storage. Of course, the storage can also be other types, which are not limited. The method includes: S201 to S202.

[0025] S201: Determine the target pre-erasure mode in automatic and active modes.

[0026] As one implementation method, the host typically uses two pre-erasure modes: automatic mode and active mode. In automatic mode, the UFS automatically performs the pre-erasure operation. When the host sends a write command, the UFS device automatically detects the state of the target physical block and performs an erase operation if necessary. In this mode, the host does not need to explicitly send a pre-erasure command; the erase operation is handled automatically by the UFS device. In active mode, the host needs to explicitly send a pre-erasure command to trigger the erase operation. After the host sends the pre-erasure command, the UFS device performs the erase operation according to the command's requirements. In this mode, the host can more precisely control when to perform the erase operation. In other words, in automatic mode, the memory automatically performs pre-erasure operations on the memory itself; in active mode, the memory performs pre-erasure operations based on instructions sent by the host.

[0027] Please see Figure 3 , Figure 3The difference between automatic mode and active mode is shown. In automatic mode, the host sends a first erase command, i.e., Write (10) EHS: open auto pre-erase. The storage device responds to this first erase command and enters automatic mode. In automatic mode, 2GB of free physical blocks are pre-erased to obtain 2GB of pre-erased blocks. Then, the host performs a write operation, applying the pre-erased blocks, i.e., Write cmds, use pre-erase blocks. The memory detects that the pre-erased blocks have been used and automatically pre-erases another 2GB of free physical blocks, and so on, until automatic mode is closed, i.e., Write (10) EHS: close auto pre-erase. Figure 3 As can be seen, in active mode, each pre-erase operation is actively triggered by the host. Specifically, it can be actively triggered based on the return information from the memory, which will be described in detail later.

[0028] Specifically, the beneficial effects of the automatic mode and the active mode are as follows: Figure 4 As shown.

[0029] It can be seen that the active mode (host trigger mode) allows the host to fully control the pre-erase amount, effectively preventing stability risks caused by pre-erase block residue. However, the IO coverage is lower than that of the automatic mode (auto mode). This is mainly because the host trigger mode triggers pre-erase only after a large number of write IO operations, resulting in a certain lag and making it impossible to guarantee that all IO operations benefit from pre-erase. Based on the aforementioned conditions for sending the second erase operation, it can be seen that the second erase command is only sent when the write rate is determined to be greater than the current first specified threshold. Therefore, multiple write operations may have already been performed before the write rate reaches the first specified threshold. Figure 4 As shown, in active mode, write operations within the time period filled with diagonal lines cannot benefit from pre-wipe.

[0030] While auto mode offers higher I / O coverage, it doesn't provide complete control over the host. If it's always enabled, erased blocks might remain unused, leading to stability issues. Therefore, for the first scenario—where there are a significant number of sequential writes—auto mode can be enabled to maximize the pre-erase benefits of write operations. I / O coverage refers to the percentage of time a write operation benefits from pre-erase operations relative to the total write operation time. Pre-erase benefits refer to the amount of pre-erase blocks that can be used by write operations.

[0031] Based on the characteristics of the aforementioned active mode and automatic mode, this application can select one of the automatic mode and active mode as the target pre-erasure mode according to actual needs, so as to perform the pre-erasure operation.

[0032] As one implementation method, embodiments of this application can determine the target pre-erase mode based on the application scenario of the storage system. For example, this application scenario could be writing data to the UFS of the storage system. As mentioned earlier, the purpose of the pre-erase operation is to erase the data in the storage device before writing new data, ensuring the stability and security of the data write operation. Therefore, the capacity of the physical blocks for the pre-erase operation should have different requirements for different data write volumes. To make the pre-erase operation more reasonable, it is necessary to determine the current data write situation of the storage system, i.e., the application scenario, before determining the pre-erase operation mode.

[0033] As one implementation method, this application scenario can reflect the data write volume of the storage system currently or within a certain future time period. Therefore, multiple scenarios can be pre-defined, each with a different data write volume. The data write volume represents the amount of data that may occur in that scenario; for example, it could be the maximum data write volume in that scenario, the historical peak value of the data write volume in that scenario, or the historical average value of the data write volume in that scenario. Therefore, for different scenarios, the data range corresponding to the current historical time period can be determined by analyzing the amount of data written to the UFS in the historical time period prior to the current moment. Based on the statistical analysis of the amount of data written to the UFS in that historical time period, the data range corresponding to the current historical time period can be determined. Based on the scenarios corresponding to the pre-defined different data ranges, the current application scenario is determined.

[0034] As one implementation method, after determining the application scenario, a target pre-erasure mode is determined based on the application scenario in the automatic mode and the active mode.

[0035] In this embodiment, the application scenarios of the storage system can be divided into a first scenario and a second scenario, wherein the data write volume in the first scenario is greater than the data write volume in the second scenario. It should be noted that the preset data write volume represents the data write capability corresponding to that scenario, i.e., it is an estimate of the maximum data write volume under that scenario.

[0036] It is understood that, in the embodiments of this application, the first scenario is a scenario of writing a large amount of data compared to the second scenario. That is to say, in the first scenario, the storage system may write a large amount of data sequentially into the memory, while in the second scenario, the amount of data written into the memory is usually smaller.

[0037] As another implementation, the target pre-erase mode can also be determined by the application running on the host. For example, the application currently running on the host can be identified, and based on this application, the target pre-erase mode can be determined between the automatic mode and the active mode. Since different applications have different write volume requirements and write speed requirements, their needs for automatic and active modes may differ. Therefore, different modes corresponding to different applications can be pre-set to obtain a mode correspondence. Based on this mode correspondence, it can be determined whether the current application should use the active mode or the automatic mode. Specific details will be elaborated in subsequent embodiments.

[0038] In the embodiments of this application, the different pre-erase modes correspond to different pre-erase strategies. The pre-erase strategy can specify the timing of the pre-erase operation, the capacity of the pre-erase block, etc., wherein the pre-erase block refers to the physical block in the memory that is subjected to the pre-erase operation, and the capacity of the pre-erase block can refer to the number of physical blocks of a specified capacity in the memory that are subjected to the pre-erase operation.

[0039] Therefore, through the above correspondence, the pre-erasure mode corresponding to the current application scenario of the storage system can be determined as the target pre-erasure mode for the memory.

[0040] S202: Perform a pre-erasure operation on the memory based on the target pre-erasure mode.

[0041] As mentioned earlier, different pre-erase modes define the timing of pre-erase, the capacity of the pre-erase block, and the entity responsible for executing the pre-erase operation, among other pre-erase strategies. Therefore, after determining the target pre-erase mode corresponding to the current application scenario of the storage system, a pre-erase operation is performed on the memory based on the target pre-erase strategy corresponding to that target pre-erase mode. Subsequent embodiments will describe different pre-erase operations based on different pre-erase modes.

[0042] It should be noted that after determining the target pre-erasure mode, the pre-erasure instruction corresponding to the target pre-erasure mode can be determined, and the pre-erasure instruction can be sent to the memory so that the memory performs a pre-erasure operation based on the pre-erasure instruction. In the embodiments of this application, the host can send the pre-erasure instruction to the memory in three ways.

[0043] The first method involves adding the pre-erase command to a preset field of a specified instruction to be sent to the memory to obtain a target instruction; then sending the target instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase command. The specified instruction to be sent to the memory can be a write or read instruction that the host currently needs to send to the memory, i.e., a WRITE / READ command. The preset field can be the EHS field of the specified instruction or other fields.

[0044] In this embodiment, the specified instruction is a read or write instruction in the UFS Protocol Information Unit (UPIU), and the preset field is an Extra header segment (EHS). The format of the UPIU is as follows: Figure 5 As shown, UPIU includes the EHS field, and the definition of the EHS field in UPIU is as follows: Figure 6 As shown in the figure, it can be seen that the EHS allows defining the type of specific instructions, parameters, and the specific content of the instructions, thereby enabling the addition of pre-erase commands in the EHS.

[0045] As is understandable, UPIU is the fundamental protocol used for communication within UFS. It's a standard command format used for control and data transfer between UFS devices, containing commands and data structures for communication. UPIU includes various commands for reading and writing, status information, error codes, and additional header information, such as the Extra Header Segment (EHS). The EHS, a part of UPIU, contains extended header information to carry additional control information or metadata. The EHS can be used to transmit command- or data transfer-specific auxiliary information to support more complex operations or provide additional contextual information.

[0046] For example, the identifier of the pre-erase command can be determined first. Then, the EHS data structure is configured. According to the definition in the UFS specification, the data structure of the pre-erase command to be added to the EHS needs to be determined. This may include command type, command parameters, length field, etc. Then, the data structure and identifier of the pre-erase command are encapsulated in the UPIU's EHS field. It should be noted that this EHS field is an extension of the aforementioned specified instruction.

[0047] In addition, the memory needs to be adapted so that after receiving the specified instruction, it can parse the EHS field of the instruction to obtain the pre-erase command, and execute the pre-erase command if the execution conditions are met. The implementation of the execution conditions can be referred to in the following embodiments, and will not be repeated here.

[0048] Therefore, by adding the pre-erase command to a preset field of the specified instruction to be sent to the memory, the specified instruction that was originally to be sent to the memory also includes the pre-erase command, so that there is no need to send a separate pre-erase command in addition to the specified instruction. In other words, there is no need to generate additional interaction due to sending a separate pre-erase command, which can prevent the impact on the user's real-time performance.

[0049] The second method involves obtaining the pre-erase command corresponding to the target pre-erase mode, generating a pre-erase instruction based on the UPIU protocol, and sending the pre-erase instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase instruction. For example, by creating an Erase Command data packet, encapsulating the Erase Command into a UPIU, configuring the UPIU header information, and sending the UPIU, a UPIU instruction containing the Erase Command (i.e., the pre-erase instruction) is sent to the UFS device to trigger the pre-erase operation. For instance, a single UPIU can be used to issue the pre-erase instruction; for example, a pre-erase vendor command can be defined using the WRITE BUFFER command. The WRITE BUFFER command may include the following functions: Writing data: This command instructs the storage device to receive a certain amount of data and write it into the device's buffer; Buffer management: The WRITE BUFFER command may involve managing the device's internal buffers, including clearing, flushing, or allocating buffers; Data transfer preparation: Some storage devices may use the WRITE BUFFER command to prepare for data transfer, ensuring that data can be efficiently transferred to a specific location in the memory. For example, according to the UFS storage specification, a specific vendor command is defined using the WRITE BUFFER command to perform an erase operation. The specific vendor command structure and content need to be constructed according to the UFS storage specification document. The vendor command can define command codes and parameters to instruct the storage device to perform the erase operation. Sending the Vendor Command: The constructed vendor command is sent to the UFS storage device using UPIU.

[0050] It's important to note that the difference between the second and first methods lies in their scope. In the first method, the host sends a specified instruction, and this instruction includes a pre-erase command within its preset field. This pre-erase command serves as extended information for the specified instruction within the preset field. For example, if the specified instruction is a UPIU protocol write instruction, then the pre-erase command is an extension of that write instruction. The host sends the specified instruction to the memory, and the memory obtains the pre-erase command by parsing the content of the specified instruction's preset field. Simultaneously, the memory responds to the specified instruction by executing the operation corresponding to it. For instance, if the specified instruction is a write instruction, the memory will simultaneously respond to the write instruction by performing a write operation and respond to the pre-erase command by performing a pre-erase operation. In the second method, however, the pre-erase command sent by the host is a pre-erase command directly defined by the UPIU protocol. Therefore, the memory receives this instruction and responds by performing a pre-erase operation.

[0051] The third method involves issuing pre-erase commands through other requests such as query requests and task management requests. Query requests are used to query the memory's attributes and status, while task management requests can be used to manage and control the execution of tasks on the memory. In other words, pre-erase commands can be added to these requests.

[0052] It should be noted that, of the three methods described above, any one of these methods can be used to send the pre-erase command in this embodiment. However, to reduce the impact on memory interaction, this embodiment uses the first method to send the pre-erase command corresponding to the target pre-erase mode.

[0053] Therefore, the embodiments of this application can determine the pre-erase mode for the memory based on the current data writing situation of the storage system, so that the pre-erase operation of the memory can be combined with the application scenario of the storage system, thereby making the pre-erase operation more in line with the current data writing needs of the storage system and making the setting of the pre-erase operation more reasonable.

[0054] Please see Figure 7 The method is applied to the host mentioned above. For ease of description, the following embodiments use UFS as an example of storage. Of course, the storage can also be other types, which is not limited. The method includes: S710 to S780.

[0055] S710: Determine the application that is running on the host.

[0056] As mentioned above, the target pre-erasure mode can be determined by the application running on the host. Therefore, in this embodiment, the application running on the host is determined first.

[0057] In one implementation, the running application can be an application running in the foreground and / or background of the smartphone. In the embodiments of this application, the running application can be an active application, which can refer to an application that has run in the foreground during the current time period and is currently running in the foreground or background, an application that has written data to the memory during the current time period, an application currently running in the foreground, or an application currently reading and / or writing data.

[0058] For active applications that have run in the foreground and are currently running in the foreground or background within the current time period (which can be a specified time period prior to the current moment), active applications can include applications currently running in the foreground and applications that have been switched from the foreground to the background within the current time period. In other words, considering that applications recently switched to the background may be switched back to the foreground, all applications that have run in the foreground within the current time period are considered active applications, i.e., the aforementioned running applications.

[0059] For active applications that have written data to memory within the current time period and are currently running in the foreground or background, the electronic device identifies applications currently running in the foreground or background as candidate applications. Then, from these candidate applications, it searches for applications that have written data to memory within the current time period, classifying them as active applications—that is, the aforementioned currently running applications. The application that has written data to memory can be further specified as having written more than a specified amount of data. Therefore, among the various applications currently running in the foreground and background of the electronic device, those that have recently written data can be considered active applications, i.e., applications currently running on the host.

[0060] In the embodiments of this application, the active application refers to the application currently running in the foreground of the electronic device. That is, the implementation method for determining the application currently running on the host determines the application currently running in the foreground, i.e., the application currently running in the foreground of the electronic device.

[0061] S720: Determines whether the specified application exists among the currently running applications.

[0062] In one implementation, the designated application can be an application from a list of pre-selected applications exhibiting a large number of sequential write operations. For example, a game application might have a large number of sequential write operations when performing installation or version update operations. A large number of sequential write operations refers to continuously performing write operations within a preset time period, with the amount of data written exceeding a preset data volume. It is understood that the applications in this list can be added manually or determined by the host based on whether each application exhibits a large number of sequential write operations within the statistical time period; the specific method is not limited here.

[0063] Therefore, after the host identifies the running application, it treats the running application as the active application and matches it against each specified application in the application list to determine if there is an application identical to that specified application. Assuming the running application is currently running in the foreground, it determines whether that application belongs to the specified applications in the application list; if so, it executes step S730; otherwise, it executes step S750.

[0064] As one implementation, if the specified application exists in the running application, the application scenario where the target pre-erasure mode is determined to be the automatic mode host is designated as the first scenario; if the specified application does not exist in the running application, the application scenario where the target pre-erasure mode is determined to be the active mode host is designated as the second scenario. In the embodiments of this application, the two application scenarios of having a specified application in the running application and not having a specified application in the running application can be named the first scenario and the second scenario, respectively. It is understood that in some embodiments, the first and second scenarios may not be set. If the specified application is determined to exist in the running application, the target pre-erasure mode is directly determined to be the automatic mode, and if the specified application does not exist in the running application, the target pre-erasure mode is directly determined to be the active mode. By using the first and second scenarios, it is more convenient to describe the active mode scenario and the automatic mode scenario.

[0065] S730: The application scenario of the host is determined to be the first scenario.

[0066] In other words, if it is determined that a specific application exists among the running applications, the application scenario of the host is determined to be the first scenario.

[0067] As mentioned earlier, this application scenario can include a first scenario and a second scenario, where the data write volume in the first scenario is greater than that in the second scenario. The specified applications in this application list are pre-determined applications that perform a large number of sequential write operations. Therefore, when a specified application is running, it may perform a large number of sequential write operations. Thus, the application scenario with the specified application running is defined as the first scenario, and correspondingly, the application scenario without the specified application running is defined as the second scenario. This aligns with the setting that the data write volume in the first scenario is greater than that in the second scenario.

[0068] S740: Determine the target pre-erasure mode for the memory as automatic mode.

[0069] If the application scenario is the first scenario, the target pre-erasure mode for the memory is determined to be automatic mode. That is, for application scenarios with a large number of sequential writes, an application list is pre-set, and automatic mode is enabled during these application activities.

[0070] S750: Send a first erase command to the memory to trigger the memory to enter automatic mode.

[0071] The pre-erase instruction corresponding to the automatic mode is the first erase instruction, which triggers the memory to enter automatic mode. It is understood that the first erase instruction can be sent using any of the three methods mentioned above. In this embodiment, the first erase instruction can be sent using the first method. Therefore, when the host detects that a specified application is active at the application layer, it determines the application scenario as the first scenario and sends an instruction to the driver layer to start the automatic mode, i.e., the "open auto pre-erase" instruction. Then, the driver layer sends a pre-erase command to the memory to enable the auto mode, i.e., the first erase instruction. For example, the driver layer uses the EHS field of commands such as write (10) to send a pre-erase command to enable the auto mode, i.e., sends the first erase instruction to the memory using the first method described above. Here, write (10) is a write command, and "(10)" represents a 10-byte write command used to write data.

[0072] In one implementation, the memory corresponds to a device management unit, which can be a controller within the memory. Additionally, in storage systems using universal flash storage (UFS) as the storage device, the UFS firmware manages the NAND flash media using virtual blocks (VBs) as units. In UFS, the storage area is divided into multiple physical blocks, each containing multiple sectors, with each sector typically being 512 bytes or 4KB in size. Virtual blocks are a logical mapping layer built on top of physical blocks, combining multiple physical blocks into a single logical block and assigning a virtual address to it. Through virtual block mapping, more efficient data read / write and management can be achieved. For example, in UFS, if a bad block occurs, the virtual block can automatically remove that block from the logical block list and migrate the data to other available physical blocks, thus ensuring data integrity and reliability. Furthermore, virtual blocks also enable high-speed random read / write operations in UFS, as well as optimization and support for TRIM commands.

[0073] Understandably, in UFS storage, pre-erasure operations are typically performed by the storage's internal controller, i.e., the aforementioned device management unit. For example, the UFS controller within the storage is responsible for managing and executing erase operations. This controller can use a VB (Virtual Block Controller) to locate free physical blocks and perform the erase operation.

[0074] For example, an implementation method that sends a first erase command to the memory to trigger the memory to enter automatic mode can be: In the automatic mode, a first erase command is sent to the memory; the memory erases a first-capacity free physical block within the memory as a pre-erase block; if the amount of data written to the pre-erase block is detected to be greater than a threshold, the operation of erasing the first-capacity free physical block within the memory as a pre-erase block is executed again until the automatic mode ends. The first capacity can be a pre-erase capacity specified by the host in the first erase command; that is, the host triggers the memory to automatically trigger the pre-erase operation and reserves a first-capacity physical space for pre-erase, i.e., a pre-erase block. A free physical block refers to a storage block on a storage medium (such as a solid-state drive, flash memory, etc.) that has not yet been used or allocated any data. A physical block is the smallest writable unit of a storage medium, and they typically have a fixed size. In storage devices, physical blocks are organized into contiguous blocks for storing data. When data is deleted or moved, the corresponding physical block becomes a free physical block and can be reused to store new data. Therefore, the capacity of a pre-erase block usually refers to the number of physical blocks for which a pre-erase operation has been performed.

[0075] In other words, in automatic mode, the host initiates pre-erasure in Auto mode of the memory via the first erase command, specifying the pre-erasure capacity (i.e., the first capacity) and the VB usage mode. The UFS device will automatically pre-erase to the first capacity during idle periods of read and / or write operations. The VB usage mode will be described later. After the pre-erased blocks are consumed by write operations, the device automatically pre-erases based on its available space, replenishing the pre-erased blocks to the set capacity. When the host issues a command to disable Auto mode, the device stops automatic pre-erasing. The pre-erased blocks will gradually be consumed by subsequent write operations.

[0076] Therefore, the host can specify the following in the pre-erase command: a) Pre-erase mode: Automode or Host trigger mode; b) VB usage mode: including commonly used NAND flash SLC / TLC / QLC modes, including but not limited to the media usage modes of new media such as MRAM / PCM / XL-Flash; c) Capacity configuration: the host can configure the pre-erase capacity within a certain range.

[0077] S760: The application scenario of the host is determined to be the second scenario.

[0078] In other words, if it is determined that the specified application does not exist among the running applications, the application scenario of the host is determined to be the second scenario.

[0079] S770: Determine the target pre-erasure mode for the memory as active mode.

[0080] The implementation methods for the second scenario and the active mode can refer to the foregoing content.

[0081] S780: Send a second erase command to the memory, instructing the memory to perform a pre-erasure operation on the free physical blocks in the memory to obtain pre-erasure space.

[0082] In the active mode, a second erase command is sent to the memory, instructing the memory to perform a pre-erasure operation on the free physical blocks in the memory to obtain pre-erasure space. In other words, in the active mode, the host specifies the capacity of the pre-erasure space as a second capacity, and the memory erases the free physical blocks of the second capacity to obtain a pre-erasure space of the second capacity, i.e., a pre-erasure block.

[0083] It should be noted that in automatic mode, the host also needs to determine whether the automatic mode has ended. If the automatic mode has ended, the host needs to send a first shutdown command to the memory, which is used to close the automatic mode. Determining whether the automatic mode has ended can involve returning to the application that is currently running on the host. Therefore, the end of the automatic mode can include entering active mode, or it can include neither active nor automatic mode, for example, when no application is currently running. Similarly, active mode can also determine whether it has ended in this way.

[0084] Furthermore, since NAND flash has different usage modes for a physical block, namely SLC / MLC / TLC / QLC modes, and the number of bits that can be stored in each smallest unit is different in different modes, typically the storage bits of the smallest unit corresponding to SLC / MLC / TLC / QLC are 1 bit / 2 bit / 3 bit / 4 bits respectively, in the case of a pre-erase operation on the memory, at the same time as sending the pre-erase instruction corresponding to the target pre-erase mode, the usage mode corresponding to the pre-erase operation is also sent, so that the memory performs the pre-erase operation in that usage mode. In other words, the host can specify the usage mode of the pre-erase VB.

[0085] In one implementation, the preconditions for the memory to perform a pre-erase operation in response to the pre-erase instruction are different under different usage modes.

[0086] For example, if the host specifies the VB usage mode for this pre-erase operation as SLC (Single-Level Cell) mode, the prerequisite for the memory to respond to the pre-erase instruction is that the memory's Write Booster (WB) buffer is available. That is, if the WB available buffer size != 0, meaning the WB buffer is not empty, the pre-erase operation in SLC mode issued by the host can be executed by the memory. If the memory's WB buffer is unavailable, and the memory capacity is insufficient, the memory will return a failure message to the host, and the host will know from this failure message that the pre-erase operation cannot be successfully executed.

[0087] As is understandable, SLC mode is a memory operation mode in UFS devices that uses higher cell density (i.e., each storage cell stores one bit) to achieve greater capacity and provide faster data transfer speeds. In SLC mode, UFS devices typically have a dedicated WB (Write Booster) buffer. The WB buffer is usually a high-speed storage area used to temporarily store write data so that it can be written to the UFS device's storage medium in batches at the appropriate time.

[0088] When the host system needs to perform a write operation, data is first written to the WB buffer of the UFS device. However, before performing an erase operation, the UFS device must ensure that all data in the WB buffer has been written to the storage medium to avoid data loss or inconsistency. Therefore, in SLC mode, the UFS device typically checks whether the WB buffer is empty before performing an erase operation. If the WB buffer still contains data to be written, the UFS device will first organize this data appropriately and write it to the memory in batches before performing the erase operation. Therefore, if the WB buffer is not empty, a failure message is returned, and the host needs to send the pre-erase command again.

[0089] Furthermore, if the host specifies that the usage mode for this pre-erase operation is TLC or QLC mode, the prerequisite for the memory to respond to the pre-erase command is that the number of current free physical blocks meets a preset requirement. This preset requirement may be that the number of free physical blocks is greater than a first number, where the first number can be set according to actual usage needs. If the number of free physical blocks is less than or equal to the first number, it indicates that the memory has insufficient free physical blocks. Therefore, if the memory determines that the current number of free physical blocks is less than or equal to the first number, it returns a failure message to the host.

[0090] It should be noted that if the application currently running on the electronic device is not the specified application, this indicates that the current application scenario does not involve large-scale data writing, i.e., there is no large amount of sequential writing. This suggests that there may be data writing operations, but the amount of data being written is small. It also indicates that the current scenario may involve data writing or that the amount of data being written is very small. Therefore, it is necessary to determine whether this falls under the category of small-scale data writing by analyzing the write rate. Figure 8 As shown, S780 may include S781 to S789.

[0091] S781: In the active mode, obtain the current write rate of the memory.

[0092] It should be noted that the current write rate is the write rate within a preset time period corresponding to the current moment. In other words, the write rate can be the amount of data written to the memory within the preset time period corresponding to the current moment. Therefore, one implementation method for obtaining the current write rate of the memory can be to obtain the number of specified write commands sent to the memory within the preset time period corresponding to the current moment, and use this number as the write rate. The specified write command is used to write a data block of a specified data size. For example, the specified data size is 512KB. Typically, for larger data write operations, the operating system's block layer will divide the data to adapt to the characteristics of the underlying storage device. In current storage devices, data read and write operations are performed in blocks, and the block size can be configured according to the specific storage device and file system. Common block sizes are 512 KB, 1KB, 2KB, 4KB, etc. In this embodiment, the data block size is 512 KB, so the specified write command is used to write a 512 KB data block. Therefore, the number of data blocks written can measure the amount of data written over a period of time. Since a specified write command is used to write a data block of a specified size, the number of specified write commands can reflect the amount of data written. Therefore, the number of specified write commands sent to the memory within a preset time length corresponding to the current moment is used as the write rate. For example, if the preset time length is 100ms, the write rate is represented by the number of 512KB chunksize write commands (n) within 100ms, where chunksize refers to a parameter used to control the block size or buffer size of the data write operation.

[0093] It is understandable that the preset time length corresponding to the current moment is the corresponding time period that can be named the current time period. The length of the current time period is the preset time length, and the end time of the current time period is the current moment. Therefore, if the current moment changes, although the preset time length is the same, the current time period will still be different.

[0094] S782: Get the current first specified threshold.

[0095] The first specified threshold is used to determine whether a pre-erase operation needs to be triggered in active mode at the current write rate. This first specified threshold can be variable, and the method of change can be referred to the following description. Since this first specified threshold is variable, the current first specified threshold needs to be obtained before each time the determination of whether the write rate is greater than the current first specified threshold is executed.

[0096] S783: Determine whether the write rate is greater than the current first specified threshold.

[0097] S784: Send the second erase command to the memory.

[0098] If the write rate is greater than the current first specified threshold, then execute S784; if the write rate is less than or equal to the current first specified threshold, return to execute S781. Alternatively, it can return to execute the step of determining the application that the host is running and subsequent steps.

[0099] It should be noted that the method for sending the second erase command to the memory can be referred to the above description, and will not be repeated here.

[0100] S785: Obtain the response information returned by the memory in response to the currently sent second erase command.

[0101] In the embodiments of this application, after the memory receives the first erase instruction or the second erase instruction, it sends a response message to the host. This response message may include failure information, success information, first information, and second information. The failure message indicates that the memory cannot perform the current pre-erasure operation, such as a command requesting the pre-erasure of VB in SLC mode, but the WB buffer is 0, or there are insufficient free blocks. The implementation of the memory sending the failure message can be referred to the aforementioned embodiments and will not be repeated here. If the memory successfully performs the pre-erasure operation, it sends a success message to the host. "Success" indicates that the pre-erasure of the set capacity corresponding to the pre-erasure operation has been completed. For example, the first erase instruction instructs the memory to automatically erase free physical blocks of the first capacity, meaning that each pre-erasure operation can obtain a pre-erased block of the first capacity; the second erase instruction instructs the memory to obtain a pre-erased block of the second capacity. Therefore, after the memory successfully obtains a pre-erased block of the corresponding capacity, it returns a success message.

[0102] In one implementation, when the host determines that the current write rate is greater than a first specified threshold, it sends a second erase command to the memory. Upon receiving the second erase command, the memory determines whether the remaining capacity of the pre-erased space obtained from the previous pre-erasing operation is lower than the second specified threshold. If it is lower, it returns first information; if it is greater than or equal to the second specified threshold, it returns second information. After returning either the first or second information, a pre-erasing operation is performed based on the second erase command. The previous pre-erasing operation refers to the pre-erasing operation performed before receiving the second erase command. The first and second information reflect the efficiency of sending the second erase command in this instance.

[0103] Understandably, the first information, "efficient," indicates that the current remaining capacity of the pre-erased space obtained from the previous pre-erasing operation in the memory is lower than a second specified threshold. The second information, "inefficient," indicates that the current remaining capacity of the pre-erased space obtained from the previous pre-erasing operation in the memory is higher than or equal to the second specified threshold. It can be seen that after receiving the first information, the host can determine that the capacity of the pre-erased space obtained from the previous pre-erasing operation in the memory is insufficient, meaning there is not enough space to write data. Therefore, the host returns the first information to notify the host that the utilization efficiency of the pre-erased block obtained from the current pre-erasing operation is relatively high, meaning the issuance efficiency of the second erase instruction is relatively high. Similarly, after receiving the second information, the host can determine that the capacity of the pre-erased space obtained from the previous pre-erasing operation in the memory is still sufficient, meaning there is still some space that has not been written data. Therefore, the host returns the second information to notify the host that the utilization efficiency of the pre-erased block obtained from the current pre-erasing operation is relatively low, meaning the issuance efficiency of the second erase instruction is relatively low.

[0104] S786: Determine whether the response information is the first information or the second information.

[0105] S787: Increase the first specified threshold.

[0106] S788: Decrease the first specified threshold.

[0107] As mentioned earlier, sending the second erase command to the memory requires that the current mode is active and that the current write rate of the memory is greater than the current first specified threshold. Therefore, by changing the first specified threshold, the frequency of sending the second erase command to the memory can be adjusted, thus helping the host dynamically adjust the pre-erase sending frequency. It can be seen that if the first specified threshold is increased this time, the write rate needs to be higher to satisfy the condition that the next write rate is greater than the first specified threshold when determining whether to send the second erase command based on the write rate. In other words, the write operation needs to be more aggressive to send the second erase command, which can reduce the sending frequency of the second erase command to some extent. Similarly, if the first specified threshold is decreased this time, the write rate can be lower to satisfy the condition that the next write rate is greater than the first specified threshold when determining whether to send the second erase command based on the write rate. In other words, it is easier to trigger the sending of the second erase command, thus increasing the sending frequency of the second erase command.

[0108] Therefore, it is determined whether the response information is the first information or the second information. If it is the first information, the first specified threshold is decreased; if it is the second information, the first specified threshold is increased.

[0109] S789: Waiting for the current pre-erase block to be written with data.

[0110] After receiving the first or second information, the memory performs a pre-erase operation, waiting for the data to be written to the current pre-erase block. It should be noted that if this active mode has not ended, i.e., if the application scenario is still the second scenario, the process returns to obtaining the current write rate of the memory and subsequent steps. In other words, write rate detection continues, and the first specified threshold used next is the first specified threshold adjusted based on the first or second information.

[0111] In one implementation, the first specified threshold has an initial value, which is initialized when the current active mode ends or the next active mode begins, i.e., set to the initial value. Furthermore, the first specified threshold also has an upper limit and a lower limit, preventing it from blindly increasing or decreasing. Therefore, the implementation of decreasing the first specified threshold if the response information is the first information involves determining whether the current first specified threshold is less than or equal to the lower limit. If it is less than or equal to the lower limit, the first specified threshold remains at the lower limit; if it is greater than the lower limit, the first specified threshold is decreased. Similarly, the implementation of increasing the first specified threshold if the response information is the second information involves determining whether the current first specified threshold is greater than or equal to the upper limit. If it is greater than or equal to the upper limit, the first specified threshold remains at the upper limit; if it is less than the upper limit, the first specified threshold is increased.

[0112] Therefore, in the first scenario, that is, when there are a large number of write operations, the automatic mode is used, allowing the memory to automatically perform pre-erase operations based on its current idle physical state, avoiding delays in host-triggered pre-erase operations. In scenarios without a large number of write operations, the active mode can be used to prevent pre-erase blocks from remaining in the memory for extended periods, which could lead to stability risks.

[0113] Therefore, by detecting the running specified application, it is possible to determine whether to enter active mode or automatic mode. In scenarios with a large number of sequential writes, automatic mode can increase the pre-erase benefit of write operations.

[0114] Please see Figure 9The diagram shows a structural block diagram of a memory management device 900 provided in an embodiment of this application. The device may include a determination unit 901 and a transmission unit 902.

[0115] The determining unit 901 is used to determine a target pre-erasure mode in automatic mode and active mode, wherein in automatic mode, the memory automatically performs a pre-erasure operation on the memory, and in active mode, the memory performs a pre-erasure operation based on instructions sent by the host.

[0116] Furthermore, the determining unit 901 is also used to determine the application that the host is running; and based on the running application, to determine the target pre-erasure mode in the automatic mode and the active mode.

[0117] Furthermore, the determining unit 901 is also configured to determine the target pre-erasure mode as the application scenario of the automatic mode host as a first scenario if the specified application exists in the running application; and to determine the target pre-erasure mode as the application scenario of the active mode host as a second scenario if the specified application does not exist in the running application.

[0118] The sending unit 903 is used to perform a pre-erasure operation on the memory based on the target pre-erasure mode.

[0119] Furthermore, the sending unit 903 is also used to send a first erase command to the memory to trigger the memory to enter an automatic mode, wherein in the automatic mode, the memory automatically performs a pre-erasure operation on the free physical blocks in the memory to obtain pre-erasure space.

[0120] Furthermore, the sending unit 903 is also configured to send a second erase command to the memory in the active mode, instructing the memory to perform a pre-erasure operation on the free physical blocks in the memory to obtain pre-erasure space.

[0121] Furthermore, the sending unit 903 is also configured to obtain the current write rate of the memory in the active mode; if the write rate is greater than the current first specified threshold, send the second erase command to the memory.

[0122] Furthermore, the sending unit 903 is also used to obtain the number of specified write commands sent to the memory within a preset time length corresponding to the current time, and use the number as the write rate, wherein the specified write command is used to write a data block of a specified data size.

[0123] Furthermore, the sending unit 903 is also configured to, if the write rate is greater than a specified threshold, send an erase command to the memory and then obtain the response information returned by the memory in response to the currently sent second erase command; if the response information is first information, then the first specified threshold is decreased, wherein the first information is used to indicate that the current remaining capacity of the pre-erased space obtained by the previous pre-erasing operation of the memory is lower than a second specified threshold, wherein the previous pre-erasing operation refers to the pre-erasing operation performed before the second erase command is received this time; if the response information is second information, then the first specified threshold is increased, wherein the second information is used to indicate that the current remaining capacity of the pre-erased space obtained by the previous pre-erasing operation of the memory is higher than or equal to the second specified threshold; if the application scenario is still the second scenario, return to the step of obtaining the current write rate of the memory and subsequent steps.

[0124] Furthermore, the sending unit 903 is also used to obtain the pre-erase command corresponding to the target pre-erase mode; add the pre-erase command to a preset field of the specified instruction to be sent to the memory to obtain the target instruction; and send the target instruction to the memory so that the memory performs a pre-erase operation based on the pre-erase command.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0126] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0127] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0128] Please refer to Figure 10 This diagram illustrates a structural block diagram of a computer-readable medium provided in an embodiment of this application. The computer-readable medium 1000 stores program code that can be called by a processor to execute the methods described in the above method embodiments.

[0129] The computer-readable medium 1000 may be an electronic storage device such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable medium 1000 includes a non-transitory computer-readable storage medium. The computer-readable medium 1000 has storage space for program code 1010 that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code 1010 may, for example, be compressed in a suitable form.

[0130] In summary, the memory management method, apparatus, storage system, and computer-readable medium provided in this application determine the application scenario of the storage system, and based on the application scenario, determine a target pre-erasure mode for the memory from a plurality of preset pre-erasure modes; and perform a pre-erasure operation on the memory based on the target pre-erasure mode. Therefore, it is possible to determine the pre-erasure mode for the memory based on the current data writing situation of the storage system, so that the pre-erasure operation of the memory can be combined with the application scenario of the storage system, thereby making the pre-erasure operation more in line with the current data writing needs of the storage system and making the setting of the pre-erasure operation more reasonable.

[0131] Furthermore, pre-erasing VB saves significant time spent erasing VB during sequential writes, improving the sequential write performance of the storage system and reducing latency spikes (i.e., maximum latency) caused by VB erasure. Host and device work together, identifying scenarios and pre-erasing as needed. While maximizing benefits, pre-erased blocks do not persist indefinitely, mitigating stability risks associated with existing solutions. Solution 1 does not use independent commands but instead utilizes UPIU's EHS field or reserved fields, thus not impacting user performance.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A pre-erasure method for a memory, characterized in that, A memory used in a storage system, the storage system further including a host, the method comprising: Receive the second erase command sent by the host; In response to the second erase command, a pre-erase operation is performed, wherein the pre-erase operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

2. The method according to claim 1, characterized in that, The pre-erasure operation is actively triggered by the host, and the memory executes the pre-erasure operation based on the second erase instruction sent by the host.

3. The method according to claim 1, characterized in that, The receiving of the second erase command sent by the host includes: Receive a target instruction sent by the host, wherein the target instruction is an instruction obtained by the host by adding the second erase instruction to a preset field of a specified instruction to be sent to the memory; The content of the preset field of the target instruction is parsed to obtain the second erase instruction.

4. The method according to claim 3, characterized in that, The specified instruction is a read or write instruction, and the preset field is an EHS field.

5. The method according to claim 1, characterized in that, The second erase instruction is a UPIU instruction that includes an erase command.

6. The method according to claim 1, characterized in that, The receiving of the second erase command sent by the host includes: The system receives a specified request sent by the host, the specified request containing the second erase instruction, wherein the specified request includes a query request or a task management request; the query request is used to query the attributes and status of the memory, and the task management request is used to manage and control the task execution of the memory.

7. The method according to claim 1, characterized in that, The second erase instruction specifies the capacity of the pre-erased space and the usage mode of the virtual block corresponding to the pre-erased operation, including SLC mode, TLC mode and QLC mode.

8. The method according to claim 7, characterized in that, The pre-erasure operation performed in response to the second erase command includes: When the virtual block corresponding to the pre-erase operation is used in SLC mode, if the write enhancement buffer of the memory is available, the pre-erase operation is performed in response to the second erase instruction, wherein the write enhancement buffer is available if the write enhancement buffer is not empty; or... When the usage mode of the virtual block corresponding to the pre-erase operation is TLC or QLC mode, if the current number of free physical blocks in the memory is greater than the first number, the pre-erase operation is executed in response to the second erase instruction.

9. The method according to claim 7, characterized in that, Also includes: If the write enhancement buffer of the memory is unavailable, a failure message is returned to the host; or, If the current number of free physical blocks is less than or equal to the first number, return a failure message to the host.

10. The method according to claim 1, characterized in that, Also includes: The system returns a response message to the host in response to the second erase instruction. The response message includes a failure message, a success message, a first message, and a second message. The failure message indicates that the memory cannot perform the current pre-erase operation. The success message indicates that the memory has successfully performed the current pre-erase operation. The first message indicates that the current remaining capacity of the pre-erase space obtained after the previous pre-erase operation is less than a second specified threshold. The previous pre-erase operation refers to the pre-erase operation performed before the second erase instruction was received. The second message indicates that the current remaining capacity of the pre-erase space obtained after the previous pre-erase operation is greater than or equal to the second specified threshold.

11. The method according to claim 1, characterized in that, The receiving of the second erase command sent by the host includes: If the current write rate of the memory is greater than the current first specified threshold, a second erase command sent by the host is received.

12. The method according to claim 11, characterized in that, Before performing the pre-erasure operation in response to the second erase command, the method further includes: If the current remaining capacity of the pre-erase space obtained from the previous pre-erase operation is lower than the second specified threshold, then the first information is returned to the host, and the first information is used to trigger the host to reduce the first specified threshold. If the current remaining capacity of the pre-erase space obtained from the previous pre-erase operation is greater than or equal to the second specified threshold, then the second information is returned to the host, which is used to trigger the host to increase the first specified threshold.

13. The method according to any one of claims 1-12, characterized in that, The memory is a general-purpose flash memory.

14. A memory management method, characterized in that, A host computer used in a storage system, the storage system further including the memory, the host computer being connected to the memory, the method comprising: A second erase command is sent to the memory, triggering the memory to respond to the second erase command and perform a pre-erasure operation. The pre-erasure operation refers to the operation of erasing the block containing the data to be written before performing a memory write operation.

15. The method according to claim 14, characterized in that, The host sends the second erase command to the memory in one of three ways: The first method: The second erase instruction is added to a preset field of the specified instruction to be sent to the memory to obtain the target instruction; Send the target instruction to the memory; The second method: send the UPIU instruction containing the erase command to the memory; The third method: Add the second erase instruction to the specified request and send the specified request to the memory, wherein the specified request includes a query request or a task management request; the query request is used to query the attributes and status of the memory, and the task management request is used to manage and control the task execution of the memory.

16. The method according to claim 15, characterized in that, In the first method, the specified instruction is a read or write instruction, and the preset field is an EHS field.

17. The method according to claim 14, characterized in that, After sending the second erase command to the memory, the method further includes: Obtain the response information from the memory in response to the second erase instruction. The response information includes failure information, success information, first information, and second information. The failure information indicates that the memory cannot perform the current pre-erase operation. The success information indicates that the memory has successfully performed the current pre-erase operation. The first information indicates that the current remaining capacity of the pre-erase space obtained after the previous pre-erase operation is less than a second specified threshold. The previous pre-erase operation refers to the pre-erase operation performed before the second erase instruction was received. The second information indicates that the current remaining capacity of the pre-erase space obtained after the previous pre-erase operation is greater than or equal to the second specified threshold.

18. A pre-erasing device for a memory, characterized in that, A memory used in a storage system, the storage system further including a host, the device comprising: The receiving unit is used to receive the second erase command sent by the host. An execution unit is configured to respond to the second erase instruction and perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

19. A memory management device, characterized in that, A host device is used in a storage system, the storage system further including the memory, the host being connected to the memory, the device comprising: a sending unit, configured to send a second erase command to the memory, triggering the memory to respond to the second erase command and perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

20. A storage system, characterized in that, include: Host; Memory; The host is connected to the memory, and the host is used to send a second erase command to the memory; The memory is configured to receive the second erase command sent by the host, and in response to the second erase command, perform a pre-erasure operation, wherein the pre-erasure operation refers to the operation of erasing the block containing the data to be written in advance before performing a memory write operation.

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