High-capacity table item processing method and device based on FPGA (Field Programmable Gate Array) platform

Abstract

The invention provides a high-capacity table item processing method and device based on an FPGA platform, and relates to the technical field of data processing.The method comprises the steps that after a newly-added table item is received, a control module conducts real-time operation type judgment on the newly-added table item; if the real-time operation type is an increasing operation, progressively traversing a three-level table item storage device by adopting a hash value of a newly-added table item to carry out DDR conflict pre-judgment so as to locate an idle storage position to carry out newly-added table item storage; and if the real-time operation type is a deletion operation, executing four-channel concurrent retrieval in the three-level table item storage device based on the newly added table item, and converging and outputting a retrieval result. According to the method and the device, the technical problem of relatively low reliability of high-capacity table item processing based on the FPGA platform in the prior art can be solved, and the technical effect of improving the reliability of the high-capacity table item processing based on the FPGA platform is achieved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method and apparatus for processing large-capacity entries based on an FPGA platform. Background Technology

[0002] With the widespread application of high-speed network equipment, intelligent data processing systems, and programmable hardware platforms, FPGA-based table entry storage and retrieval technology has gradually become one of the important foundational technologies supporting core functions such as routing, rule matching, state management, and data scheduling. Especially in application scenarios that require simultaneous high-concurrency access, large-capacity table entry storage, and low-latency processing, how to achieve efficient management of a large number of table entries under limited on-chip resources has become a key issue restricting system performance and scalability.

[0003] Currently, most existing FPGA-based table entry processing solutions employ a single storage medium or a simple multi-level storage structure, using a fixed hash algorithm or linear traversal to store and retrieve entries. While these solutions can meet basic requirements when the number of entries is small, they often reveal numerous shortcomings when the number of entries continues to grow, access operation types become more complex, and concurrent requests become more frequent. On one hand, existing technologies generally lack hierarchical scheduling and collaborative management mechanisms tailored to the characteristics of different storage media. They fail to effectively differentiate the differences in capacity, access latency, and parallelism between on-chip BlockRAM, off-chip DDR, and register-level storage resources, leading to insufficient utilization of high-speed storage resources and a significant increase in access latency for large-capacity storage. On the other hand, existing solutions primarily handle storage conflicts through post-event detection or simple retries, lacking conflict prediction and buffering mechanisms oriented towards time windows. When multiple increment operations occur simultaneously within a short period, address conflicts or access congestion can easily form in large-capacity storage such as DDR, resulting in write failures, retrieval uncertainty, or a sharp decline in performance.

[0004] In summary, existing technologies suffer from several problems. Firstly, the lack of a unified table management architecture for FPGA-based multi-layered heterogeneous storage resources, the absence of a hierarchical storage and concurrent retrieval mechanism combining different hash strategies, and the lack of effective means for time window prediction and buffering of DDR storage conflicts lead to frequent storage conflicts, low retrieval efficiency, and uneven resource utilization in high-concurrency CRUD scenarios for large-capacity tables. These issues further impact the throughput performance, real-time response capability, and overall operational reliability of FPGA-based table processing systems. Summary of the Invention

[0005] The purpose of this application is to provide a method and apparatus for processing large-capacity table entries based on an FPGA platform, in order to solve the technical problems in the prior art that are caused by the lack of a unified table entry management architecture for FPGA multi-layer heterogeneous storage resources, the lack of a hierarchical storage and concurrent retrieval mechanism that combines different HASH strategies, and the lack of effective means to predict DDR storage conflicts by time window and buffer traffic. These problems lead to frequent storage conflicts, low retrieval efficiency, and uneven resource utilization in high-concurrency CRUD scenarios for large-capacity table entries, which further affect the throughput performance, real-time response capability, and overall operational reliability of FPGA-based table entry processing systems.

[0006] In view of the above problems, this application provides a method and apparatus for processing large-capacity entries based on an FPGA platform.

[0007] Firstly, this application provides a method for processing large-capacity table entries based on an FPGA platform, implemented through an FPGA-based large-capacity table entry processing device. The method includes: upon receiving a new table entry, a control module performs real-time operation type determination on the new table entry; if the real-time operation type is an add operation, the hash value of the new table entry is used to progressively traverse a three-level table entry storage device to perform DDR conflict pre-determination, thereby locating a free storage location for storing the new table entry. The three-level table entry storage device includes BlockRAM, DDR, and LUT register array storage devices, and the LUT register array storage device includes a first LUT register array and a second LUT register array; if the real-time operation type is a delete operation, a four-channel concurrent retrieval is performed on the three-level table entry storage device based on the new table entry, and the retrieval results are aggregated and output.

[0008] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: after receiving the newly added entry, concurrently allocating it to a parallel retrieval channel, wherein the parallel retrieval channel includes a first processing channel, a second processing channel, a third processing channel, and a fourth processing channel: A1: performing an entry retrieval operation of the BlockRAM using a short-number HASH algorithm in the first processing channel; A2: performing an entry retrieval operation of the DDR using a high-bit-width HASH algorithm in the second processing channel; A3: performing an entry retrieval operation of the first LUT register array using a hierarchical traversal search in the third processing channel; A4: performing an entry retrieval operation of the second LUT register array using a hierarchical traversal search in the fourth processing channel; wherein steps A1 to A4 are executed in parallel, and when any processing channel retrieves a target entry, the operation of the remaining channels is stopped and the retrieval result is output.

[0009] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: calculating the hash value of the newly added entry using a short-number HASH algorithm to obtain a first hash value; detecting whether there is a storage conflict at the position corresponding to the first hash value in the BlockRAM; if there is no storage conflict, storing the newly added entry into the BlockRAM.

[0010] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: if there is a storage conflict at the position corresponding to the first hash value in the BlockRAM, then detecting whether there is free space in the first LUT register array; if there is free space in the first LUT register array, then storing the new entry into the first LUT register array in the order of storage address.

[0011] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: if the first LUT register array has no free space, calculating the hash value of the newly added entry using a high-bit-width HASH algorithm to obtain a second hash value; using a hierarchical traversal search algorithm to query whether there is a hash value in the third LUT register array that is the same as the second hash value, wherein the third LUT register array is used to cache the hash value of increment operations within a time window to predict DDR conflicts; if there is no hash value in the third LUT register array that is the same as the second hash value, detecting whether there is a conflict at the position corresponding to the second hash value in the DDR; if there is no conflict, storing the newly added entry in the DDR.

[0012] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: if there is a hash value in the third LUT register array that is the same as the second hash value, then a DDR conflict is determined, and the second LUT register array is checked for free space; if there is free space in the second LUT register array, then the newly added entry is sequentially stored in the second LUT register array; if there is no free space in the second LUT register array, then an entry expansion request is submitted.

[0013] Preferably, the method for processing large-capacity entries based on an FPGA platform further includes: if there is no hash value in the third LUT register array that is the same as the second hash value, and there is a conflict at the corresponding position of the second hash value in the DDR, then an expansion request is reported or a new entry is added for storage based on the free space status of the second LUT register array.

[0014] Secondly, this application also provides a large-capacity table entry processing device based on an FPGA platform, used to execute a large-capacity table entry processing method based on an FPGA platform as described in the first aspect, comprising: an operation type discrimination unit, used to perform real-time operation type discrimination on the new table entry after receiving it; a DDR conflict pre-discrimination unit, used to perform DDR conflict pre-discrimination by progressively traversing the three-level table entry storage device using the hash value of the new table entry if the real-time operation type is an add operation, in order to locate a free storage location for storing the new table entry, wherein the three-level table entry storage device includes a BlockRAM, DDR and LUT register array storage device, and the LUT register array storage device includes a first LUT register array and a second LUT register array; and a concurrent retrieval unit, used to perform a four-channel concurrent retrieval on the three-level table entry storage device based on the new table entry if the real-time operation type is a delete operation, and aggregate and output the retrieval results.

[0015] The technical solution provided in this application has at least the following technical effects or advantages: by implementing a multi-layer storage collaborative management and parallel retrieval table entry processing technology based on operation type discrimination, it achieves low-conflict, high-concurrency, and high-efficiency storage and retrieval of large-capacity table entries under limited FPGA hardware resources, and significantly improves the overall system processing performance, operational stability, and scalability through conflict pre-judgment and multi-level buffer diversion mechanism.

[0016] The above description is merely an overview of the technical solution of this application. To enable a clearer understanding of the technical means of this application and to facilitate its implementation according to the description, and to make the above and other objects, features, and advantages of this application more apparent, specific embodiments of this application are described below. It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent through the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a large-capacity table entry processing method based on an FPGA platform according to this application.

[0019] Figure 2This is a schematic diagram of the structure of a large-capacity table entry processing device based on an FPGA platform according to this application.

[0020] Figure labeling: Operation type discrimination unit 1, DDR conflict pre-discrimination unit 2, concurrent retrieval unit 3. Detailed Implementation

[0021] This application provides a method and apparatus for processing large-capacity table entries based on an FPGA platform. It addresses existing technologies that suffer from frequent storage conflicts, low retrieval efficiency, and uneven resource utilization in high-concurrency CRUD scenarios for large-capacity table entries. These issues stem from the lack of a unified table entry management architecture for multi-layer heterogeneous storage resources on FPGAs, the lack of a hierarchical storage and concurrent retrieval mechanism combining different hash strategies, and the lack of effective means for time window prediction and buffering of DDR storage conflicts. These shortcomings further impact the throughput, real-time response capability, and overall reliability of FPGA-based table entry processing systems. The application achieves a table entry processing technology based on operation type discrimination for multi-layer storage collaborative management and parallel retrieval. This results in low-conflict, high-concurrency, and high-efficiency storage and retrieval of large-capacity table entries under limited FPGA hardware resources. Furthermore, it significantly improves the overall system processing performance, operational stability, and scalability through conflict pre-judgment and multi-level buffering mechanisms.

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. It should be understood that this application is not limited to the exemplary embodiments described herein. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. It should also be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all of them.

[0023] Example 1, please refer to the appendix. Figure 1 This application provides a method for processing large-capacity entries based on an FPGA platform, which is applied to a device for processing large-capacity entries based on an FPGA platform, and specifically includes the following steps: After receiving a new entry, the control module performs real-time operation type determination on the new entry.

[0024] Specifically, receiving new entries refers to the input of new entry data from external business systems, data interfaces, or upper-level processing logic into the FPGA-based entry processing system. New entries represent target data units that need to be stored, updated, deleted, or queried, and include key fields, index fields, or encoded identification information for entry location. The process of receiving new entries is completed through a preset data bus, interface protocol, or input buffer to ensure that new entries can stably enter the control logic for subsequent processing according to a predetermined timing sequence.

[0025] The control module refers to the core scheduling and decision-making logic unit deployed within the FPGA platform. The control module is used to uniformly manage and coordinate the processing flow of new entries. It parses the operation identifier, request type field, or control signal carried by the input entry, and combines this with preset operation discrimination rules or state machine logic to determine the operation type of the new entry. This determines whether the new entry corresponds to an add, delete, or query operation, providing a basis for selecting different processing paths subsequently.

[0026] Furthermore, real-time operation type discrimination refers to the process by which the control module identifies the operation type within the current processing cycle or adjacent clock cycles after a new entry enters the system. This discrimination process does not rely on offline analysis or batch processing; instead, it provides the discrimination result instantly based on a parallel hardware logic mechanism. This ensures that in high-concurrency, high-throughput scenarios, the corresponding storage, retrieval, or deletion processing flow can be quickly switched according to different operation types, avoiding the accumulation of processing delays.

[0027] If the real-time operation type is an increment operation, the hash value of the newly added entry is used to traverse the three-level entry storage device in a progressive manner to perform DDR conflict pre-judgment in order to locate the free storage location for storing the newly added entry. The three-level entry storage device includes BlockRAM, DDR and LUT register array storage devices. The LUT register array storage device includes a first LUT register array and a second LUT register array.

[0028] Specifically, the real-time operation type is an add operation, which means that after the control module completes the operation type judgment for the newly added table entry, it determines that the table entry corresponding to the newly added table entry is table entry data that needs to be written or appended to the storage. The add operation is used to introduce the new table entry into the existing table entry set to expand or update the table entry content maintained by the system. Its judgment result serves as a prerequisite for triggering the subsequent storage allocation and conflict handling process.

[0029] Using the hash value of a new table entry refers to performing a preset hash operation rule on the key fields used for indexing or locating in the new table entry to generate a hash result used for storage addressing and conflict judgment. The hash value is used to map the new table entry to the corresponding storage location space, thereby reducing the resource consumption caused by direct sequential lookup and providing a unified basis for consistent addressing between hierarchical storage devices.

[0030] Furthermore, the progressive traversal of the three-level table entry storage device refers to detecting and evaluating the storage location corresponding to the hash value in different storage devices in turn according to the pre-set storage priority and access level. The progressive process follows the principle of expanding step by step from high-speed, low-latency storage to large-capacity storage, so as to meet storage needs while taking into account access efficiency and hardware resource utilization.

[0031] Meanwhile, DDR conflict prediction refers to the process of predicting potential memory address conflicts in advance based on hash values ​​and historical storage status before actually writing new entries to the DDR storage device. The prediction process is used to identify the risk of multiple entries mapping to the same DDR address or the same address range, so that avoidance or diversion measures can be taken before writing to avoid write failure or performance degradation.

[0032] Therefore, storing the new table entry by locating a free storage location means that after completing the progressive traversal and conflict prediction, at least one unoccupied or write-condition storage unit is determined, and the new table entry is written to the free location, thereby realizing the orderly allocation and stable storage of the new table entry in the multi-layer storage system.

[0033] Among them, the three-level table entry storage device refers to the multi-layer heterogeneous storage system built inside the FPGA platform, including BlockRAM, DDR and LUT register array storage devices, which are used to form a synergistic cooperation among different capacities, speeds and resource characteristics to support the high-speed processing requirements of large-capacity entries.

[0034] Furthermore, BlockRAM refers to the block-shaped random access memory resources integrated inside the FPGA chip, which has the characteristics of low access latency and high parallelism, and is suitable for storing high-frequency access or critical index entries; DDR refers to external or off-chip large-capacity dynamic random access memory devices, used to carry large-capacity entry data; and LUT register array storage devices refer to configurable storage structures built based on FPGA lookup tables and register resources, used for temporary caching or fallback storage of entries in scenarios with storage conflicts or limited capacity.

[0035] In addition, the LUT register array storage device includes a first LUT register array and a second LUT register array. The first LUT register array is used to carry new entries when conflicts occur or space is insufficient in the preceding storage, while the second LUT register array is used to provide further buffering and fault tolerance when conflicts occur or expansion is limited in the subsequent storage, thereby forming a multi-level conflict mitigation and storage compensation mechanism.

[0036] If the real-time operation type is a delete / search operation, then based on the newly added table entry, a four-channel concurrent retrieval is performed on the third-level table entry storage device, and the retrieval results are aggregated and output.

[0037] Furthermore, this application also includes: after receiving the newly added table entry, concurrently allocating it to a parallel retrieval channel, wherein the parallel retrieval channel includes a first processing channel, a second processing channel, a third processing channel, and a fourth processing channel: A1: performing the table entry retrieval operation of the BlockRAM using a short number HASH algorithm in the first processing channel; A2: performing the table entry retrieval operation of the DDR using a high bit width HASH algorithm in the second processing channel; A3: performing the table entry retrieval operation of the first LUT register array using a hierarchical traversal search in the third processing channel; A4: performing the table entry retrieval operation of the second LUT register array using a hierarchical traversal search in the fourth processing channel; wherein steps A1 to A4 are executed in parallel, and when any processing channel retrieves the target table entry, the operation of the remaining channels is stopped and the retrieval result is output.

[0038] Specifically, receiving new entries means that, under the premise that the current operation type is determined to be a delete or query operation, the system interface or upper-level control logic inputs the target entry to be retrieved into the entry processing module inside the FPGA platform. In this scenario, the new entry is used as a search condition or matching object. It contains index fields, hash fields or key identification information for entry location so that matching judgment can be performed in different storage levels.

[0039] Concurrent allocation to parallel retrieval channels means that after receiving a new entry, the control module uses parallel scheduling logic to simultaneously copy or broadcast the new entry to multiple independent retrieval processing channels. This allows each processing channel to independently execute retrieval operations within the same time window, thereby avoiding the accumulation of latency caused by serial retrieval and fully leveraging the parallel processing capabilities of the FPGA platform.

[0040] The parallel retrieval channels include a first processing channel, a second processing channel, a third processing channel, and a fourth processing channel. These refer to multiple independent retrieval execution paths constructed at the hardware logic level. Each processing channel corresponds to a storage medium and a retrieval strategy. The processing channels are independent of each other in terms of timing and control to support simultaneous access to different storage devices.

[0041] In step A1, the first processing channel uses a short-number hash algorithm to perform the entry retrieval operation of the BlockRAM. This means that when searching the BlockRAM storage area, a hash algorithm with a small bit width and low computational complexity is used to map the key fields of the new entry to a compact index number, and the corresponding storage address in the BlockRAM is directly located based on the index, thereby achieving high-speed and low-latency entry retrieval.

[0042] Subsequently, in step A2, the second processing channel uses a high-bit-width HASH algorithm to perform DDR table entry retrieval operations. This means that, given the large storage capacity and wide address space of DDR, a hash algorithm with a higher bit width and lower collision probability is used to map the newly added table entries, so as to improve the accuracy and stability of retrieving target table entries in a large-capacity storage space and reduce the impact of address collisions on retrieval efficiency.

[0043] Furthermore, in step A3, the third processing channel uses hierarchical traversal search to perform the entry retrieval operation of the first LUT register array. This means that in the first LUT register array, multiple register units are traversed and compared layer by layer according to a preset hierarchical structure or address order to identify whether there is a target entry that matches the newly added entry. The hierarchical traversal method is used to improve the retrieval coverage under the condition of limited register resources.

[0044] Meanwhile, in step A4, the fourth processing channel uses hierarchical traversal search to perform the entry retrieval operation of the second LUT register array. This means that the same or similar traversal retrieval mechanism as the first LUT register array is used to compare the entries in the second LUT register array level by level, so as to further expand the retrieval range and increase the probability of the target entry being retrieved if the first LUT is not hit.

[0045] The parallel execution of steps A1 to A4 means that the four processing channels run simultaneously within the same clock cycle or overlapping timing windows, each independently completing the retrieval task on the corresponding storage medium, thereby significantly shortening the overall retrieval latency and improving the system response capability in high-concurrency scenarios.

[0046] When any processing channel retrieves a target entry, the operation of the remaining channels is stopped and the retrieval result is output. This means that after receiving a hit signal from any processing channel, the control module immediately sends a termination control command to the remaining processing channels to stop the incomplete retrieval process and outputs the hit entry information as the final retrieval result, in order to avoid invalid calculations and redundant resource consumption.

[0047] Furthermore, this application also includes: calculating the hash value of the newly added entry using a short number HASH algorithm to obtain a first hash value; detecting whether there is a storage conflict at the position corresponding to the first hash value in the BlockRAM; if there is no storage conflict, storing the newly added entry into the BlockRAM.

[0048] Specifically, using the short-number HASH algorithm to calculate the hash value of a new table entry refers to performing a hash mapping operation with a smaller output bit width and a shorter calculation path on the key field used for indexing and locating in the new table entry. This converts the key field into a compact number form, thereby generating a hash result for high-speed addressing. The short-number HASH algorithm is adapted to the characteristics of FPGA hardware implementation and can complete the hash value calculation under conditions of less logic resources and lower clock latency.

[0049] The first hash value refers to the mapping result obtained through the short number HASH algorithm. The first hash value is used to directly correspond to the address space or address index range of the BlockRAM, serving as the initial storage location basis for new entries in the BlockRAM, and is used for subsequent conflict judgment and storage decisions.

[0050] Furthermore, detecting whether there is a storage conflict at the position corresponding to the first hash value in the BlockRAM means that the control module locates the target storage unit in the BlockRAM based on the first hash value and judges the occupancy status of the storage unit to determine whether other entries have already occupied the position or whether there is an address mapping overlap, thereby identifying the data overwriting or consistency problems that may occur when a new entry is directly written to the position.

[0051] Storage conflicts refer to situations where different entries, after being hashed, point to the same BlockRAM storage address or the same logical storage unit. Conflicts may cause existing entries to be overwritten, retrieval ambiguity, or data errors. Therefore, effective detection and avoidance are required before write operations.

[0052] When it is determined that there is no storage conflict, storing the new entry into BlockRAM means that after confirming that the target storage unit is in an idle or available state, the control module triggers the write control signal to write the data content of the new entry into the BlockRAM storage address corresponding to the first hash value, so as to complete the storage of the new entry in the high-speed storage level, thereby ensuring fast access to the entry in the future.

[0053] Furthermore, this application also includes: if there is a storage conflict at the position corresponding to the first hash value in the BlockRAM, then detect whether there is free space in the first LUT register array; if there is free space in the first LUT register array, then store the newly added table entry into the first LUT register array in the order of storage address.

[0054] Specifically, a storage conflict at the location corresponding to the first hash value in BlockRAM means that after the control module locates the target storage unit of BlockRAM based on the first hash value, it determines that the storage unit has been occupied by other entries or that multiple entries are mapped to the same address. Therefore, it cannot directly write the new entry to the location. The occurrence of a storage conflict indicates that the high-speed storage level does not have available write space under the current hash mapping conditions.

[0055] Detecting whether there is free space in the first LUT register array means that when a memory conflict occurs in BlockRAM, the control module further judges the resource status of the first LUT register array, which serves as an auxiliary storage level. By detecting the occupancy flag or valid bit information of each register unit, it confirms whether there are still free register positions that can be used to store new entries, thereby providing a basis for subsequent memory allocation.

[0056] Furthermore, the existence of free space in the first LUT register array means that there is at least one register storage unit in the first LUT register array that has not yet been allocated or marked as invalid. This free space is used to carry new entries that cannot be directly written due to BlockRAM conflicts, thereby playing the role of buffering and transitional storage.

[0057] When it is confirmed that there is free space in the first LUT register array, the new entries are stored in the first LUT register array in the order of their storage addresses. This means that the control module writes the new entries into the free register units in the first LUT register array according to the pre-set address arrangement rules or sequential allocation strategy. This sequential storage method is used to maintain the orderliness of the internal storage structure of the register array, which facilitates subsequent traversal retrieval, management and maintenance and status update operations.

[0058] Furthermore, this application also includes: if the first LUT register array has no free space, then the hash value of the newly added entry is calculated using a high-bit-width HASH algorithm to obtain a second hash value; a hierarchical traversal search algorithm is used to query whether there is a hash value in the third LUT register array that is the same as the second hash value, wherein the third LUT register array is used to cache the hash value of the increment operation within the time window to predict DDR conflicts; if there is no hash value in the third LUT register array that is the same as the second hash value, then a conflict is detected at the position corresponding to the second hash value in the DDR; if there is no conflict, then the newly added entry is stored in the DDR.

[0059] Specifically, the absence of free space in the first LUT register array means that after resource status detection of the first LUT register array, it is determined that all its internal register units are occupied or have reached the preset capacity limit, making it unable to continue to carry new entries that are diverted due to the previous level storage conflict, thus requiring the introduction of the next level of storage processing strategy.

[0060] Calculating the hash value of the newly added table entry using a high-bit-width HASH algorithm means using hash operation rules with a larger output bit width and a wider mapping space for the key fields of the newly added table entry to generate a more distinguishable hash result, thereby reducing the probability of address collisions in large-capacity storage space. The hash operation process is implemented in FPGA hardware logic to adapt to the addressing characteristics of DDR storage.

[0061] Furthermore, the second hash value refers to the hash result obtained through the high-bit-width HASH algorithm. This second hash value serves as the basis for locating the new entry in the DDR storage space and is used for subsequent conflict judgment, storage decisions, and access indexes.

[0062] Subsequently, a hierarchical traversal search algorithm is used to query whether there is a hash value in the third LUT register array that is the same as the second hash value. This means that the control module compares the cached hash values ​​in the third LUT register array layer by layer according to the preset hierarchical structure or address order to determine whether other increment operation entries have used the same second hash value in the current time window, thereby identifying potential DDR memory address conflicts in advance.

[0063] The third LUT register array is used to cache the hash values ​​of increment operations within a time window to predict DDR conflicts. This means that the third LUT register array does not directly store complete table entry data, but is used to temporarily store the hash values ​​corresponding to increment operations that have occurred or are being processed within a certain time range. Through centralized management of hash values, the early detection and avoidance of DDR conflicts can be achieved.

[0064] When there is no hash value in the third LUT register array that is the same as the second hash value, checking whether there is a conflict at the position corresponding to the second hash value in DDR means that after confirming that there is no known conflict risk within the time window, further checking the actual occupancy status of the target address in DDR is performed to determine whether there are other entries or address mapping overlap at that position.

[0065] If no conflict is confirmed, the new entry will be stored in DDR. This means that the control module initiates a write operation to DDR to write the data content of the new entry into the DDR storage address mapped by the second hash value, thereby completing the formal storage of the new entry in the high-capacity storage level.

[0066] Furthermore, this application also includes: if there is a hash value in the third LUT register array that is the same as the second hash value, then a DDR conflict is determined, and it is detected whether there is free space in the second LUT register array; if there is free space in the second LUT register array, then the newly added entries are sequentially stored in the second LUT register array; if there is no free space in the second LUT register array, then an entry expansion request is submitted.

[0067] Specifically, the existence of a hash value in the third LUT register array that is the same as the second hash value means that when performing a hierarchical traversal search on the third LUT register array, at least one cached hash value is detected that is consistent with the second hash value calculated by the high-bit-width HASH algorithm for the currently added entry. This consistency indicates that other added entries have been mapped to the same DDR address or address range within the preset time window, thus reflecting the potential risk of memory address overlap.

[0068] Determining DDR conflicts means that the control module directly determines, based on the hash value hit result in the third LUT register array, that writing the newly added entry into DDR will cause an address conflict or data overwrite risk. Therefore, there is no need to perform access detection on the actual storage location of DDR, and conflict determination can be made in advance to avoid invalid storage access and resource waste.

[0069] Furthermore, detecting whether there is free space in the second LUT register array means that after confirming that a DDR conflict has occurred, the control module turns to check the resource status of the second LUT register array, which serves as the subsequent buffer storage layer, and determines whether there is still available space that can be used to temporarily store new entries by judging the occupancy of its internal register units.

[0070] When there is free space in the second LUT register array, the newly added entries are stored sequentially in the second LUT register array. This means that the control module writes the newly added entries into the free register cells in the second LUT register array according to the preset sequential allocation or address increment rules. The sequential storage method is conducive to maintaining the continuity of the internal structure of the register array and facilitates subsequent unified retrieval, management and cleanup operations.

[0071] Conversely, if there is no free space in the second LUT register array, the above entry expansion request refers to the control module sending an expansion instruction signal to the upper-level management unit or system control module when all local buffer storage resources are occupied. This is used to request the addition of entry storage resources, adjust storage configuration, or trigger an external expansion mechanism to avoid the loss of newly added entries and ensure the continuous operation of the system.

[0072] Furthermore, this application also includes: if there is no hash value in the third LUT register array that is the same as the second hash value, and there is a conflict at the corresponding position of the second hash value in the DDR, then an expansion request is reported or a new entry is added for storage based on the free space status of the second LUT register array.

[0073] Specifically, the absence of a hash value identical to the second hash value in the third LUT register array means that after performing a hierarchical traversal search on the third LUT register array, no cached record consistent with the second hash value calculated by the high-bit-width HASH algorithm for the currently added entry was detected. This indicates that no other add operation entry has used the same hash mapping within the preset time window, and there is no known conflict warning information from a time perspective.

[0074] A conflict at the location corresponding to the second hash value in DDR refers to a scenario where, without triggering the third LUT register array to predict a conflict, further detection of the actual DDR storage space reveals that the target DDR storage address mapped by the second hash value has been occupied by other entries or has address overlap, thus forming an actual storage conflict scenario that was not identified in advance by the time window cache.

[0075] Furthermore, the process of reporting expansion requests or adding new entries based on the free space status of the second LUT register array means that after confirming the actual DDR conflict, the control module switches to using the second LUT register array as the final buffer and fallback storage resource. By detecting whether there are still available register units in the second LUT register array, the subsequent processing strategy is dynamically determined.

[0076] When there is free space in the second LUT register array, storing a new entry means writing the data content of the new entry into a free register cell in the second LUT register array to temporarily carry the DDR conflict entry, thereby ensuring that the new entry is not discarded and maintaining the continuity of system processing.

[0077] Conversely, when there is no free space in the second LUT register array, the expansion request report means that the control module sends an expansion indication signal to the upper-level resource management unit or system control module, requesting to increase the storage capacity of the table entries, adjust the storage structure, or enable the external expansion mechanism to cope with the current insufficient storage resources.

[0078] In summary, the large-capacity table entry processing method based on the FPGA platform provided in this application has the following technical effects: by realizing a table entry processing technology goal of multi-layer storage collaborative management and parallel retrieval based on operation type discrimination, it achieves low-conflict, high-concurrency, and high-efficiency storage and retrieval of large-capacity table entries under limited FPGA hardware resources, and significantly improves the overall system processing performance, operational stability, and scalability through conflict pre-judgment and multi-level buffer diversion mechanism.

[0079] Example 2: Based on the same inventive concept as the FPGA-based large-capacity table entry processing method described in the foregoing examples, this application also provides an FPGA-based large-capacity table entry processing apparatus. Please refer to the appendix. Figure 2 The system includes: an operation type determination unit 1, used by the control module to perform real-time operation type determination on the newly added entry after receiving it; a DDR conflict pre-determination unit 2, used to perform DDR conflict pre-determination by progressively traversing the three-level entry storage device using the hash value of the newly added entry if the real-time operation type is an add operation, in order to locate a free storage location for storing the newly added entry, wherein the three-level entry storage device includes a BlockRAM, DDR and LUT register array storage device, and the LUT register array storage device includes a first LUT register array and a second LUT register array; and a concurrent retrieval unit 3, used to perform a four-channel concurrent retrieval on the three-level entry storage device based on the newly added entry if the real-time operation type is a delete operation, and aggregate and output the retrieval results.

[0080] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used for: receiving the newly added table entry and concurrently allocating it to a parallel retrieval channel, wherein the parallel retrieval channel includes a first processing channel, a second processing channel, a third processing channel, and a fourth processing channel: A1: performing the table entry retrieval operation of the BlockRAM using a short number HASH algorithm in the first processing channel; A2: performing the table entry retrieval operation of the DDR using a high bit-width HASH algorithm in the second processing channel; A3: performing the table entry retrieval operation of the first LUT register array using a hierarchical traversal search in the third processing channel; A4: performing the table entry retrieval operation of the second LUT register array using a hierarchical traversal search in the fourth processing channel; wherein steps A1 to A4 are executed in parallel, and when any processing channel retrieves the target table entry, the operation of the remaining channels is stopped and the retrieval result is output.

[0081] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used to: calculate the hash value of the newly added table entry using a short number HASH algorithm to obtain a first hash value; detect whether there is a storage conflict at the position corresponding to the first hash value in the BlockRAM; if there is no storage conflict, store the newly added table entry into the BlockRAM.

[0082] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used to: if there is a storage conflict at the position corresponding to the first hash value in the BlockRAM, detect whether there is free space in the first LUT register array; if there is free space in the first LUT register array, store the newly added table entry into the first LUT register array in the order of storage address.

[0083] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used for: if there is no free space in the first LUT register array, calculating the hash value of the newly added table entry using a high-bit-width HASH algorithm to obtain a second hash value; using a hierarchical traversal search algorithm to query whether there is a hash value in the third LUT register array that is the same as the second hash value, wherein the third LUT register array is used to cache the hash value of the increment operation within the time window to predict DDR conflicts; if there is no hash value in the third LUT register array that is the same as the second hash value, detecting whether there is a conflict at the position corresponding to the second hash value in the DDR; if there is no conflict, storing the newly added table entry into the DDR.

[0084] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used to: if there is a hash value in the third LUT register array that is the same as the second hash value, then determine a DDR conflict and detect whether there is free space in the second LUT register array; if there is free space in the second LUT register array, then sequentially store the new table entry into the second LUT register array; if there is no free space in the second LUT register array, then submit a table entry expansion request.

[0085] Furthermore, the large-capacity table entry processing device based on the FPGA platform is also used to: if there is no hash value in the third LUT register array that is the same as the second hash value, and there is a conflict at the corresponding position of the second hash value in the DDR, then perform an expansion request report or add a new table entry storage according to the free space status of the second LUT register array.

[0086] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The large-capacity table entry processing method and specific examples based on the FPGA platform in the foregoing embodiment one are also applicable to the large-capacity table entry processing device based on the FPGA platform in this embodiment. Through the foregoing detailed description of the large-capacity table entry processing method based on the FPGA platform, those skilled in the art can clearly understand the large-capacity table entry processing device based on the FPGA platform in this embodiment. Therefore, for the sake of brevity, it will not be described in detail here.

[0087] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0088] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for processing large-capacity entries based on an FPGA platform, characterized in that, The method includes: After receiving a new entry, the control module performs real-time operation type determination on the new entry; If the real-time operation type is an add operation, the hash value of the newly added entry is used to traverse the three-level entry storage device in a progressive manner to perform DDR conflict pre-judgment in order to locate the free storage location for storing the newly added entry. The three-level entry storage device includes BlockRAM, DDR and LUT register array storage device, and the LUT register array storage device includes a first LUT register array and a second LUT register array. If the real-time operation type is a delete / search operation, then based on the newly added table entry, a four-channel concurrent retrieval is performed on the third-level table entry storage device, and the retrieval results are aggregated and output.

2. The method for processing large-capacity entries based on an FPGA platform as described in claim 1, characterized in that, If the real-time operation type is a delete / search operation, then based on the newly added table entry, a four-channel concurrent retrieval is performed on the third-level table entry storage device, and the retrieval results are aggregated and output. The method includes: Upon receiving the newly added table entry, it is concurrently allocated to a parallel retrieval channel, wherein the parallel retrieval channel includes a first processing channel, a second processing channel, a third processing channel, and a fourth processing channel: A1: The BlockRAM entry retrieval operation is performed in the first processing channel using a short number HASH algorithm; A2: The DDR entry retrieval operation is performed in the second processing channel using a high-bit-width HASH algorithm; A3: The table entry retrieval operation of the first LUT register array is performed using hierarchical traversal search in the third processing channel; A4: The table entry retrieval operation of the second LUT register array is performed using hierarchical traversal search in the fourth processing channel; Steps A1 to A4 are executed in parallel. Once any processing channel retrieves the target entry, the operation of the other channels is stopped and the retrieval result is output.

3. The method for processing large-capacity entries based on an FPGA platform as described in claim 1, characterized in that, The method further includes: The hash value of the newly added table entry is calculated using the short number HASH algorithm to obtain the first hash value; If there is a storage conflict at the position corresponding to the first hash value in the BlockRAM, and if there is no storage conflict, the new entry is stored in the BlockRAM.

4. The method for processing large-capacity entries based on an FPGA platform as described in claim 3, characterized in that, The method further includes: If there is a storage conflict at the position corresponding to the first hash value in the BlockRAM, then check whether there is free space in the first LUT register array; If there is free space in the first LUT register array, the newly added entries are stored in the first LUT register array in order of their storage addresses.

5. The method for processing large-capacity entries based on an FPGA platform as described in claim 4, characterized in that, The method further includes: If there is no free space in the first LUT register array, the hash value of the newly added entry is calculated using a high-bit-width HASH algorithm to obtain the second hash value; A hierarchical traversal search algorithm is used to query whether there is a hash value in the third LUT register array that is the same as the second hash value. The third LUT register array is used to cache the hash value of the increment operation within the time window to predict DDR conflicts. If there is no hash value in the third LUT register array that is the same as the second hash value, then check whether there is a conflict at the position corresponding to the second hash value in the DDR; If there is no conflict, the newly added entry will be stored in the DDR.

6. The method for processing large-capacity entries based on an FPGA platform as described in claim 5, characterized in that, The method further includes: If the third LUT register array contains a hash value that is the same as the second hash value, a DDR conflict is determined, and it is checked whether the second LUT register array has free space. If there is free space in the second LUT register array, the newly added entries are sequentially stored in the second LUT register array; If there is no free space in the second LUT register array, then the above report item will request an expansion.

7. The method for processing large-capacity entries based on an FPGA platform as described in claim 5, characterized in that, If there is no hash value in the third LUT register array that is the same as the second hash value, and there is a conflict at the corresponding position of the second hash value in the DDR, then an expansion request report or a new entry storage is performed according to the free space status of the second LUT register array.

8. A large-capacity table entry processing device based on an FPGA platform, characterized in that, The steps for implementing the large-capacity table entry processing method based on an FPGA platform according to any one of claims 1 to 7 include: An operation type determination unit is used to determine the operation type of a newly added table entry in real time after the control module receives the new table entry. The DDR conflict pre-judgment unit is used to perform DDR conflict pre-judgment by progressively traversing the three-level table entry storage device using the hash value of the newly added table entry if the real-time operation type is an increment operation, so as to locate the free storage location for storing the newly added table entry. The three-level table entry storage device includes a BlockRAM, DDR and LUT register array storage device, and the LUT register array storage device includes a first LUT register array and a second LUT register array. The concurrent retrieval unit is used to perform a four-channel concurrent retrieval on the third-level table entry storage device based on the newly added table entry if the real-time operation type is a delete or query operation, and then aggregate and output the retrieval results.

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