PLC task scheduling method and device, electronic equipment and storage medium

Abstract

The invention discloses a PLC task scheduling method and device, electronic equipment and a storage medium. According to the specific implementation scheme, when the semaphore of a clock reference task is detected, a plurality of first-type tasks are triggered; and when it is detected that the first type of tasks meeting the half-cycle offset scheduling condition exist, performing half-cycle offset scheduling on the first type of tasks. According to the technical scheme, the first type of tasks meeting the half-cycle offset scheduling conditions are subjected to half-cycle offset scheduling, resource competition and scheduling conflicts caused by multi-task concurrence can be effectively avoided, and therefore the efficiency and reliability of PLC task scheduling can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial automation, in particular to a PLC task scheduling method and device, an electronic device and a storage medium. BACKGROUND

[0002] As a core control device, Programmable Logic Controller (PLC) is widely used in various industrial control scenarios. The PLC includes periodic tasks and interrupt tasks. The above tasks need to be uniformly managed by a task scheduler during operation to ensure the real-time and accuracy of the control logic. The existing scheduling method usually adopts a fixed cycle triggering mechanism, that is, the task execution is triggered periodically by a system clock interrupt. However, when multiple tasks are triggered at the same time at a specific time point, it is easy to cause task scheduling intersection or accumulation, resulting in high instantaneous Central Processing Unit (CPU) load, which affects the system stability. Therefore, a new type of PLC task scheduling design is needed, which can effectively avoid resource competition and scheduling conflicts caused by multi-task concurrency on the premise of ensuring real-time preemption of high-priority tasks, and realize uniform distribution of PLC tasks in the time dimension, thereby improving the efficiency and reliability of PLC task scheduling. SUMMARY

[0003] The present application provides a PLC task scheduling method, device, electronic device and storage medium, aiming to solve the problem of low efficiency and reliability of PLC task scheduling caused by multi-task concurrency.

[0004] In a first aspect, a PLC task scheduling method is provided, comprising: triggering a plurality of first type tasks when detecting a semaphore of a clock reference task; performing half-cycle offset scheduling on the first type tasks when detecting that there is a first type task that meets the half-cycle offset scheduling condition.

[0005] In a second aspect, a PLC task scheduling device is also provided, comprising: a first triggering module, configured to trigger a plurality of first type tasks when detecting a semaphore of a clock reference task; a scheduling module, configured to perform half-cycle offset scheduling on the first type tasks when detecting that there is a first type task that meets the half-cycle offset scheduling condition.

[0006] In a third aspect, the present application also provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor invokes the computer program in the memory to execute the PLC task scheduling method provided in the first aspect.

[0007] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program. The computer program is loaded by a processor to execute the PLC task scheduling method provided in the first aspect.

[0008] According to the technical solution of the present disclosure, when the semaphore of the clock reference task is detected, the plurality of first type tasks are triggered; when it is detected that there is a first type task satisfying the half-cycle offset scheduling condition, the first type task is subjected to half-cycle offset scheduling. In this way, resource competition and scheduling conflicts caused by multi-task concurrency can be effectively avoided, thereby helping to improve the efficiency and reliability of PLC task scheduling. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1 is a flowchart of the PLC task scheduling provided by some embodiments of the present application; Figure 2 is a comparison diagram of fixed cycle task scheduling and half-cycle offset scheduling provided by some embodiments of the present application; Figure 3 is a flowchart of the half-cycle offset scheduling provided by some embodiments of the present application; Figure 4 is a flowchart of the execution of the first type task provided by some embodiments of the present application; Figure 5 is a flowchart of the execution of the second type task provided by some embodiments of the present application; Figure 6 is a scheduling diagram of low-density scheduling after half-cycle offset scheduling provided by some embodiments of the present application; Figure 7 is a structural diagram of an embodiment of the PLC task scheduling device provided by some embodiments of the present application; Figure 8 is a structural diagram of an embodiment of the electronic device provided in the embodiments of the present application. DETAILED DESCRIPTION

[0011] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0012] In the description of the embodiments of the present application, it should be understood that the terms "first", "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0013] The use of "applicable to" or "configured to" in the present application means open and inclusive language, which does not exclude devices applicable to or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0014] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other implementations. The following description is presented to enable any person skilled in the art to make and use the present application. In the following description, for the purposes of explanation, details are set forth in order to provide a thorough understanding of the present application. It should be apparent to one skilled in the art that the present application can be practiced without the specific details presented below. In other instances, well-known structures and processes are not described in detail in order to avoid obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features presented herein.

[0015] In the related art, with the rapid development of industrial automation and intelligent manufacturing, PLC as a core control device is widely used in various industrial automation scenarios. According to the International Electrotechnical Commission (IEC) 61131-3 international standard, the program in the PLC is usually composed of multiple task types, mainly including periodic tasks (such as timer tasks, loop tasks), interrupt tasks and event-driven tasks. The above tasks need to be uniformly managed by the task scheduler of the PLC system during the running process to ensure the real-time and accuracy of the control logic.

[0016] In the prior art, in a PLC system, PLC task scheduling is usually implemented by means of a real-time operating system, such as a Real-Time Operating System (RTOS), a Real-Time Linux (RT-Linux) operating system, and the like. Specifically, the existing PLC task scheduling mode usually adopts a fixed period trigger mechanism, that is, task execution is triggered periodically by means of a clock interrupt of the PLC system. Specifically, the prior art has the following disadvantages: First, when the execution periods of multiple periodic tasks have an integer multiple relationship (for example, the periods are 1 ms, 2 ms, 4 ms, and 8 ms), the simultaneous triggering of multiple tasks at a specific time point is prone to occur, which causes task scheduling to be "crossed" or "stacked", resulting in excessively high instantaneous CPU load, affecting system stability, and even possibly causing a control period to be timed out due to insufficient task execution time; Second, the existing PLC task scheduling mode lacks active regulation of task execution density, and the distribution of tasks on the time axis is uneven, making it difficult to achieve balanced utilization of resources, resulting in large fluctuations in CPU utilization, with resources being idle in some time periods and being severely overloaded in other time periods; Third, the existing PLC task scheduling mode lacks flexibility, and lacks fine control means for the execution time of PLC tasks, making it difficult to balance scheduling uniformity and real-time response.

[0017] To at least partially solve one or more of the above problems and other potential problems, the present disclosure proposes a PLC task scheduling scheme, which includes: when a semaphore of a clock reference task is detected, triggering a plurality of first type tasks; when it is detected that there is a first type task that meets a half-period offset scheduling condition, performing half-period offset scheduling on the first type task. In this way, by performing half-period offset scheduling on the first type task that meets the half-period offset scheduling condition, resource competition and scheduling conflicts caused by multiple task concurrency can be effectively avoided, thereby helping to improve the efficiency and reliability of PLC task scheduling.

[0018] Figure 1 is a flowchart of PLC task scheduling according to an embodiment of the present disclosure, as shown in Figure 1 the method at least includes the following steps: S101: when a semaphore of a clock reference task is detected, triggering a plurality of first type tasks; S102: when it is detected that there is a first type task that meets a half-period offset scheduling condition, performing half-period offset scheduling on the first type task.

[0019] In some embodiments, the clock reference task is a time anchor point for triggering the first type of task, providing a stable and unique time reference for the first type of task by releasing a semaphore, and is the basis for implementing PLC task scheduling. The clock reference task releases the semaphore periodically according to a preset running interval. When the PLC system detects the semaphore of the clock reference task, it determines whether the first type of task meets the first scheduling condition or the half-cycle offset scheduling condition, and schedules the first type of task that meets the first scheduling condition or the half-cycle offset scheduling condition to control the first program organization unit in the first type of task to execute the first target instruction or the second program organization unit to execute the second target instruction.

[0020] In some embodiments, the first type of task refers to a periodic task in the PLC that complies with the IEC 61131-3 international standard. The first type of task is mainly used for periodically executing fixed logic in industrial control (such as cycle monitoring, timing control, etc.), and is the basis for implementing regular control of industrial automation. The first type of task is repeatedly run according to a preset running interval, such as collecting temperature every 100 ms, performing PID (Proportional-Integral-Derivative Control) operation every 200 ms, etc.

[0021] In some embodiments, according to the PLC task scheduling requirements, five first type of tasks are set. When developing IEC program design and writing, according to the PLC system design and development requirements, the multiple first program organization units (POU) or first program organization units written are placed in the first type of task to complete the program function implementation. In order to complete the scheduling of the first type of task, a clock reference task (denoted as T0) and five first type of tasks (denoted as T0, T1, T2, T3, T4, T5 respectively) need to be set when running the PLC system. The first type of task is triggered when it detects the semaphore released by the clock reference task. The preset running interval of the first type of task is determined by the reference time of the clock reference task (T0), which is as follows: T0: As a time reference, T0 has no first type of task; T1: The cycle interval is 2 n1 *T0 (the minimum is 1 * T0); T2: The cycle interval is 2 n2 *T0; where n2 > n1; T3: The cycle interval is 2 n3 *T0; where n3 > n2; T4: The cycle interval is 2 n4 *T0; where n4 > n3; T5: the cycle interval is 2 n5 T0; wherein, n5>n4.

[0022] The running priority of the first type of task is T1>T2>T3>T4>T5. In addition, multiple first program organization units or second program organization units can also be placed in one first type of task.

[0023] Figure 2 The comparison diagram of fixed cycle task scheduling and half cycle offset scheduling is shown as follows. Figure 2 As shown in the figure, the blank square represents the first type of task (T1), the diagonal line square represents the first type of task (T2), the vertical line square represents the first type of task (T3), the cross line square represents the first type of task (T4), and the horizontal line square represents the first type of task (T5); as shown in Figure 2 (a) When n1=0, n2=1, n3=2, n4=3, n5=4, it is fixed cycle task scheduling; specifically, T1 is executed at time “0”, T1 and T2 are executed at time “1”, T1 is executed at time “2”, T1, T2 and T3 are executed at time “3”, T1 is executed at time “4”, T1 and T2 are executed at time “5”, T1 is executed at time “6”, T1, T2, T3 and T4 are executed at time “7”, T1 is executed at time “8”, T1 and T2 are executed at time “8”, T1 is executed at time “10”, T1, T2 and T3 are executed at time “11”, T1 is executed at time “12”, T1 and T2 are executed at time “13”, T1 is executed at time “14”, T1, T2, T3, T4 and T5 are executed at time “15”; when it is detected that there is a first type of task that meets the half cycle offset scheduling condition, the first type of task is half cycle offset scheduled, as shown in Figure 2 (b). Half cycle offset scheduling: T1 is executed at time “0”, T1 and T2 are executed at time “1”, T1 and T3 are executed at time “2”, T1 and T2 are executed at time “3”, T1 and T4 are executed at time “4”, T1 and T2 are executed at time “5”, T1 and T3 are executed at time “6”, T1 and T2 are executed at time “7”, T1 and T5 are executed at time “8”, T1 and T2 are executed at time “9”, T1 and T5 are executed at time “10”, T1 and T2 are executed at time “11”, T1 and T4 are executed at time “12”, T1 and T2 are executed at time “13”, T1 and T3 are executed at time “11”, and T1 and T2 are executed at time “15”.

[0024] The scheme of the embodiments of the present disclosure triggers a plurality of first type tasks when detecting the semaphore of the clock reference task; and performs half-cycle offset scheduling on the first type task when detecting that the first type task meets the half-cycle offset scheduling condition. In this way, by performing half-cycle offset scheduling on the first type task meeting the half-cycle offset scheduling condition, resource competition and scheduling conflicts caused by multi-task concurrency can be effectively avoided, thereby helping to improve the efficiency and reliability of PLC task scheduling.

[0025] In the embodiments of the present disclosure, a plurality of second type tasks are triggered when detecting the semaphore of the interrupt state.

[0026] In some embodiments, the second type task refers to an interrupt type task in the PLC that complies with the IEC 61131-3 international standard. The second type task is triggered after receiving the semaphore of the external interrupt state, and the priority of the second type task is higher than the priority of the first type task.

[0027] In some embodiments, the semaphore of the interrupt state is a mechanism for coordinating synchronization or resource mutual exclusion between the second type task and other tasks (such as the first type task), which is essentially a flag variable or a counter. The execution order or resource access permission of the task is controlled by releasing the semaphore.

[0028] In this way, by triggering a plurality of second type tasks when detecting the semaphore of the interrupt state, it can be ensured that the second type task is triggered in time, thereby helping to improve the real-time performance of PLC task scheduling.

[0029] In the embodiments of the present disclosure, the priority of the second type task is higher than the priority of the first type task, and when the semaphore of the interrupt state is detected while running the first type task, the first type task is interrupted and the second type task is run.

[0030] In some embodiments, according to the PLC task scheduling requirements, 5 first type tasks and 8 second type tasks are set. In order to complete the scheduling of the first type tasks and the second type tasks, a clock reference task (denoted as T0), 5 first type tasks (denoted as T0, T1, T2, T3, T4, T5, respectively) and 8 second type tasks (l1, l2, l3, l4, l5, l6, l7, l8) need to be set when running the PLC system. Among them, a plurality of first type tasks are triggered when the semaphore of the clock reference task is detected; and a plurality of second type tasks are triggered when the semaphore of the interrupt state is detected, and different interrupt sources can be configured for the interrupt state. The priority of the first type task decreases from T1 to T5 in turn, and is specifically as follows: T0: As a time reference, there is no first type task in T0; T1: The cycle interval is 2n1 T0 (minimum 1*T0); T2: cycle interval is 2 n2 T0; wherein n2>n1; T3: cycle interval is 2 n3 T0; wherein n3>n2; T4: cycle interval is 2 n4 T0; wherein n4>n3; T5: cycle interval is 2 n5 T0; wherein n5>n4.

[0031] The priority of the second type of task is sequentially decreased from I1 to I8, and is specifically as follows: I1: second type of task 1; I2: second type of task 2; I3: second type of task 3; I4: second type of task 4; I5: second type of task 5; I6: second type of task 6; I7: second type of task 7; I8: second type of task 8.

[0032] It should be noted that the running priority order of the first type of task and the second type of task is: T0>I1>I2>I3>I4>I5>I6>I7>I8>T1>T2>T3>T4>T5, and the above tasks are completed by the real-time operating system for task scheduling.

[0033] Exemplarily, it is assumed that the PLC system is executing the first type of task T2, T2 is to dynamically correct the frequency of the conveying belt motor according to the current material flow (cycle interval is 2 n2 T0, n2>n1); when T2 is executed to the third step of the adjustment logic (such as calculating the target frequency parameter), the PLC system detects the signal quantity of the interrupt state of the second type of task I3, which is triggered by the material stack overrun sensor at the end of the production line (the interrupt source of I3 is configured as the high-level signal of the sensor); the PLC system interrupts the execution of T2, and automatically saves the current execution progress of T2 (including the calculated intermediate parameters, program counter position, etc.); the PLC system runs I3, and executes the preset interrupt processing logic: quickly cuts off the output of the end conveying belt motor; after the execution of I3 is completed, T2 is continued to be run, and the remaining frequency adjustment logic is executed from the third step which is interrupted.

[0034] Thus, by interrupting the first type of task and running the second type of task when detecting the semaphore of the interrupt state while running the first type of task, the high-priority task can be preempted in real time, which helps to improve the real-time performance of the PLC task scheduling.

[0035] In the embodiments of the present disclosure, it is assumed that the clock reference task of the PLC system is T0, and the running periods of the plurality of first type of tasks are Tn=2 n T0(wherein n is an incremental integer, ensuring that the priority order of the plurality of first type of tasks is T1<T2<T3<T4<T5). Meanwhile, a global counter is used to count the running period of the first type of task, and the running period is maintained by the clock reference task T0, which is incremented by 1 every T0 time and is reset to zero when reaching the maximum running period T5. The rule for the global counter to count the running period of the first type of task is: TickCount=TickCount+1; TickCount=(TickCount+1)%T5.

[0036] wherein TickCount represents the global counter, and the global counter is used to count the running period of the first type of task.

[0037] In the embodiments of the present disclosure, the half-cycle offset scheduling condition is calculated according to the following formula: tn_res=(TickCount+Tn / 2)%Tn; wherein tn_res represents the half-cycle offset scheduling condition, TickCount represents the global counter, and Tn represents the running period in which the first type of task is located. When tn_res=0, the half-cycle offset scheduling of the first type of task is triggered. When tn_res=0, the PLC system determines whether the current first type of task is at a safe execution point that can be interrupted; if yes, the first type of task is offset and scheduled for half a cycle; if not, the offset scheduling is delayed until the next safe point that meets the condition.

[0038] In some embodiments, the half-cycle offset scheduling condition is a condition for whether the first type of task is subjected to half-cycle offset scheduling. When it is detected that there is a first type of task that meets the half-cycle offset scheduling condition, the first type of task is subjected to half-cycle offset scheduling.

[0039] Thus, by detecting that there is a first type of task that meets the half-cycle offset scheduling condition, the first type of task is subjected to half-cycle offset scheduling, which can avoid the CPU resource contention caused by the concentrated execution of the plurality of first type of tasks at the same time point, reduce the execution delay caused by resource conflicts, and help to improve the efficiency and reliability of the PLC task scheduling.

[0040] In the embodiments of the present disclosure, when it is detected that there is a first type task satisfying the half-cycle offset scheduling condition, the first type task is subjected to half-cycle offset scheduling, which includes: after the first type task is bound to the first program organization unit, a first application program is generated when it is detected that the first type task satisfies the half-cycle offset scheduling condition; when it is detected that the first application program is running, the first type task is scheduled to control the first program organization unit in the first type task to execute a first target instruction.

[0041] In some embodiments, the program organization unit is a basic program module unit defined by the IEC 61131-3 international standard for PLC programming, and the core role is to split the complex PLC control program into independent and reusable structured modules, facilitating program development, maintenance and transplantation. The first program organization unit is one of the basic execution units for task scheduling, carries the core control logic of the first type task, and realizes half-cycle offset scheduling through cooperation with the global counter. The first program organization unit is used to bind the first type task respectively to generate a first application program, and when it is detected that the first application program is running, the first type task is scheduled to control the first program organization unit in the first type task to execute a first target instruction. The first application program refers to an executable logic unit composed of the first type task and the first program organization unit bound thereto, and its running state is directly managed by the task scheduler, ensuring that when the half-cycle offset condition is met, multiple first type tasks are scheduled in turn according to the priority of the first type task, and the program organization unit in the first type task is controlled to execute the first target instruction. The first target instruction refers to a specific operation instruction or logic code contained in the first program organization unit bound by the first type task for implementing a specific control function. Exemplarily, the first target instruction can be a logic instruction for controlling the start and stop of a motor, an analog output instruction for adjusting the opening degree of a valve, or an input acquisition instruction for reading sensor data. It should be noted that the above is only an exemplary description and does not limit the entire possible content of the first target instruction, but here we do not make an exhaustive enumeration.

[0042] Figure 3 A flowchart of the half-cycle offset scheduling is shown, as shown in Figure 3 The flowchart can include: S301: PLC system starts; S302: initialize clock reference task; S303: hardware interrupt enable; here, the hardware interrupt enable is a response mechanism that allows a specific external event to trigger the interruption of the PLC system; S304: main loop; S305: whether to detect the semaphore of the interruption state; if yes, execute S306; if no, execute S307; S306: Triggering a plurality of second type tasks; S307: Updating a global counter; S308: Calculating a half-cycle offset scheduling condition tn_res of the plurality of first type tasks; S309: Whether there is a first type task satisfying tn_res=0; if yes, performing S310; if no, returning to S304; S310: Scheduling the first type task to control a first program organization unit in the first type task to execute a first target instruction; S311: Completing the first type task and releasing a semaphore; here, after completing the first type task and releasing the semaphore, returning to S304.

[0043] In this way, by detecting that there is a first type task satisfying the half-cycle offset scheduling condition, the first type task is scheduled with a half-cycle offset, so that the execution time of the first type task is staggered by a half cycle on the time axis from other tasks of the same running cycle, avoiding that multiple tasks of the same priority or the same running cycle occupy core resources such as CPU at the same time, reducing resource conflicts and waiting delays in the task execution process, and helping to improve the timing accuracy of the execution of the first target instruction, thereby helping to improve the efficiency and reliability of PLC task scheduling.

[0044] In the embodiments of the present disclosure, when the semaphore of the clock reference task is detected, the plurality of first type tasks are triggered, including: when the semaphore of the clock reference task is detected, configuring a plurality of first type tasks according to a preset running interval; after binding the plurality of first type tasks with a plurality of second program organization units respectively, generating a second application program; when the second application program is detected to run, calculating a first scheduling condition corresponding to each of the plurality of first type tasks respectively; when it is detected that there is a first type task satisfying the first scheduling condition, scheduling the first type task to control a second program organization unit in the first type task to execute a second target instruction.

[0045] In some embodiments, the second program organization unit is one of the basic execution units of task scheduling, carries the core control logic of the first type of task, and realizes periodic task scheduling through cooperation with the global counter. The second program organization unit is used to bind with a plurality of first type of tasks respectively, generate a second application program, and calculate the first scheduling condition corresponding to each of the plurality of first type of tasks respectively when detecting that the second application program is running. When detecting that there is a first type of task satisfying the first scheduling condition, the first type of task is scheduled to control the second program organization unit in the first type of task to execute the second target instruction. The second application program refers to an executable logic unit composed of the first type of task and the second program organization unit bound thereto, and its running state is directly managed by the task scheduler, ensuring that the plurality of first type of tasks are scheduled in turn according to the priority of the first type of task when the first scheduling condition is satisfied, and the second program organization unit in the first type of task is controlled to execute the second target instruction. The second target instruction refers to a specific operation instruction or logic code for realizing a specific control function contained in the second program organization unit bound to the first type of task. Exemplarily, the second target instruction can be a logic instruction for controlling the start and stop of a motor, an analog output instruction for adjusting the opening degree of a valve, or an input acquisition instruction for reading sensor data. It should be noted that the above is only an exemplary description and does not limit the entire possible content of the second target instruction. Here, an exhaustive enumeration is not made.

[0046] Figure Four A flowchart for executing the first type of task is shown, as shown in Figure 4 The flowchart can include: S401: Start; S402: Initialize the clock reference task; S403: When detecting the semaphore of the clock reference task, configure a plurality of first type of tasks according to a preset running interval; Exemplarily, the running period of the first type of task T1 is set to T1=2, the running period of the first type of task T2 is set to T2=4, the running period of the first type of task T3 is set to T3=8, the running period of the first type of task T4 is set to T4=16, and the running period of the first type of task T5 is set to T5=32; S404: After binding the plurality of first type of tasks with the plurality of second program organization units respectively, generate a second application program; Exemplarily, after binding T1-T5 with the plurality of second program organization units respectively, generate a second application program; S405: Update the global counter; Exemplarily, the global counter TickCount is incremented, and a remainder operation is performed with T25. The global counter is updated to TickCount=(TickCount+1)%T5 every time it is triggered. S406: When the second application program is detected to run, the first scheduling condition corresponding to each of the plurality of first type tasks is respectively calculated; for example, when the second application program is detected to run, the first scheduling condition corresponding to each of the plurality of first type tasks is respectively calculated; specifically, for T1, the first scheduling condition of T1 is calculated by (TickCount+T1 / 2)%T1, for T2, the first scheduling condition of T2 is calculated by (TickCount+T2 / 2)%T2, for T3, the first scheduling condition of T3 is calculated by (TickCount+T3 / 2)%T3, for T4, the first scheduling condition of T4 is calculated by (TickCount+T4 / 2)%T4, for T5, the first scheduling condition of T5 is calculated by (TickCount+T5 / 2)%T5; the task scheduler of the PLC system is specifically run as follows: TickCount=(TickCount+1)%T5; If((TickCount+T1 / 2)%T1==0)execute_task1(); If((TickCount+T2 / 2)%T2==0)execute_task2(); If((TickCount+T3 / 2)%T3==0)execute_task3(); If((TickCount+T4 / 2)%T4==0)execute_task4(); If((TickCount+T5 / 2)%T5==0)execute_task5().

[0047] S407: Whether there is a first type task meeting the first scheduling condition; if yes, S408 is executed; if no, S405 is executed; S408: Scheduling the first type task to control the second program organization unit in the first type task to execute the second target instruction.

[0048] In this way, by triggering the plurality of first type tasks when the semaphore of the clock reference task is detected, time overlap or logical conflict caused by random start time can be avoided, and each second program organization unit can execute the second target instruction according to the cooperative sequence, and system response lag or logical error caused by chaotic triggering can be reduced.

[0049] In the embodiments of the present disclosure, when the signal quantity of the interrupt state is detected, the plurality of second type tasks are triggered, including: after the second scheduling conditions of the plurality of second type tasks are initialized, and after the plurality of second type tasks are bound with the plurality of third program organization units, a third application program is generated; the interrupt state of the plurality of second type tasks is monitored in real time, and when the signal quantity of the interrupt state is detected, the second type task meeting the second scheduling condition is scheduled to control the third program organization unit in the second type task to execute a third target instruction.

[0050] In some embodiments, the third program organization unit is one of the basic execution units of task scheduling, carries the core control logic of the second type task, and is used to be bound with the plurality of second type tasks respectively to generate a third application program. After the third application program is generated, the interrupt state of the plurality of second type tasks is monitored in real time, and when the signal quantity of the interrupt state is detected, the second type task meeting the second scheduling condition is scheduled to control the third program organization unit in the second type task to execute a third target instruction. The third application program refers to an executable logic unit composed of the second type task and the third program organization unit bound therewith, and the running state thereof is directly managed by the task scheduler, so as to ensure that the plurality of second type tasks are sequentially scheduled according to the priority of the second type task when the second scheduling condition is met, and the third program organization unit in the second type task is controlled to execute a third target instruction. The third target instruction refers to a specific operation instruction or logic code for realizing a specific control function contained in the third program organization unit bound with the second type task. Exemplarily, the third target instruction can be a logic instruction for controlling the start and stop of a motor, can be an analog output instruction for adjusting the opening degree of a valve, or can be an input collection instruction for reading sensor data. It should be noted that the above is only an exemplary description, and is not a limitation on all possible contents of the third target instruction, but here no exhaustive enumeration is made.

[0051] Figure 5 A flowchart for executing the second type task is shown, as shown in Figure 5 The flowchart can include: S501: start; S502: initialize the second scheduling conditions of the plurality of second type tasks; S503: after the plurality of second type tasks are bound with the plurality of third program organization units, a third application program is generated; S504: the third application program is downloaded to the PLC system; S505: the interrupt state of the plurality of second type tasks is monitored in real time; S506: whether the signal quantity of the interrupt state is detected; if yes, S507 is executed; if no, S505 is executed; S507: scheduling a second type task meeting a second scheduling condition to control a third program organization unit in the second type task to execute a third target instruction.

[0052] In this way, when the semaphore of the interrupt state is detected, the plurality of second type tasks are triggered, the interrupt response logic of the plurality of third program organization units can be triggered with the interrupt state semaphore as a precise trigger point, and the second type tasks that are suitable are quickly screened and started in combination with the pre-initialized second scheduling condition, so that the third target instructions are executed in order by the plurality of third program organization units according to the interrupt response logic, and irrelevant tasks are prevented from being mistakenly started or responding with lag, and redundant operations and logic conflicts in interrupt processing are reduced.

[0053] In the embodiment of the present disclosure, the PLC task scheduling method further includes: after the semi-cycle offset scheduling of the first type tasks, a preset running interval is set according to a target requirement, so that one first type task is executed in one running cycle.

[0054] In some embodiments, the target requirement can be a PLC system design requirement or a development requirement. It should be noted that the above is only an example and is not intended to limit all possible target requirements.

[0055] In some embodiments, after the semi-cycle offset scheduling of the first type tasks, the first program organization units in each first type task are executed at different time periods, and the running cycle of each first type task is Tn=2 n T0 (wherein n is an incremental integer, and T0 is a clock reference task). However, when n1=0, n2=1, n3=2, n4=3, and n5=4, there are two first type tasks in each running cycle. In order to further reduce the frequency and quantity of task cross accumulation, after the semi-cycle offset scheduling of the first type tasks, a preset running interval is set according to a target requirement, so that one first type task is executed in one running cycle. Figure 6 A scheduling diagram of low-density scheduling after semi-cycle offset scheduling is shown as follows: Figure 6 As shown in the figure, the blank square represents a first type task (T1), the diagonal line square represents a first type task (T2), the vertical line square represents a first type task (T3), the cross line square represents a first type task (T4), and the horizontal line square represents a first type task (T5). When the preset running interval is set according to the target requirement, when n1=1, n2=2, n3=4, n4=8, and n5=16, only one first type task is executed in each running cycle.

[0056] Thus, by performing the half-cycle offset scheduling on the first type of task, and setting the preset running interval according to the target requirement, one running cycle can execute one first type of task, so that an independent execution window can be reserved for each first type of task in the running cycle, avoiding multiple tasks of the same priority or the same running cycle from occupying core resources such as CPU at the same time, reducing resource conflicts and waiting delays in the task execution process, and thus helping to improve the efficiency and reliability of PLC task scheduling.

[0057] The embodiment of the present disclosure provides a PLC task scheduling device, as shown in the figure, the PLC task scheduling device comprises: Figure 7 The PLC task scheduling device comprises: The first trigger module 701 is configured to trigger a plurality of first type of tasks when detecting the semaphore of the clock reference task. The scheduling module 702 is configured to perform half-cycle offset scheduling on the first type of task when detecting that there is a first type of task meeting the half-cycle offset scheduling condition.

[0058] In some embodiments, the PLC task scheduling device further comprises a second scheduling module (not shown in the figure) configured to trigger a plurality of second type of tasks when detecting the semaphore of the interrupt state. Figure 7 The second type of task has a priority higher than that of the first type of task.

[0059] In some embodiments, when the semaphore of the interrupt state is detected while the first type of task is running, the first type of task is interrupted, and the second type of task is run.

[0060] In some embodiments, the half-cycle offset scheduling condition is calculated according to the following formula: tn_res=(TickCount+Tn / 2)%Tn; Wherein, tn_res represents the half-cycle offset scheduling condition, TickCount represents the global counter, and Tn represents the running cycle in which the first type of task is located.

[0061] In some embodiments, the global counter is used to count the running cycle of the first type of task, and the rule for the global counter to count the running cycle of the first type of task is: TickCount=TickCount+1; TickCount=(TickCount+1)%T5.

[0062] In some embodiments, the scheduling unit comprises: a first generating submodule configured to generate a first application after binding the first type of task to the first program organization unit when it is detected that there is a first type of task satisfying the half-cycle offset scheduling condition; and a first scheduling submodule configured to schedule the first type of task to control the first program organization unit in the first type of task to execute the first target instruction when it is detected that the first application is running.

[0063] In some embodiments, the first triggering module comprises: a configuration submodule configured to configure a plurality of first type of tasks according to a preset running interval when it is detected that the semaphore of the clock reference task; a second generating submodule configured to generate a second application after binding the plurality of first type of tasks to a plurality of second program organization units respectively; a calculation submodule configured to calculate a first scheduling condition corresponding to each of the plurality of first type of tasks respectively when it is detected that the second application is running; and a second scheduling submodule configured to schedule the first type of task to control the second program organization unit in the first type of task to execute the second target instruction when it is detected that there is a first type of task satisfying the first scheduling condition.

[0064] In some embodiments, the second triggering module comprises: a third generating submodule configured to generate a third application after initializing a second scheduling condition of a plurality of second type of tasks and binding the plurality of second type of tasks to a plurality of third program organization units; and a third scheduling submodule configured to monitor an interrupt state of the plurality of second type of tasks in real time, and schedule the second type of task satisfying the second scheduling condition to control the third program organization unit in the second type of task to execute the third target instruction when it is detected that the semaphore of the interrupt state.

[0065] In some embodiments, the PLC task scheduling device further comprises: setting the preset running interval according to the target requirement after the half-cycle offset scheduling of the first type of task, so that one first type of task is executed in one running cycle.

[0066] The PLC task scheduling device according to the embodiments of the present disclosure can effectively avoid resource competition and scheduling conflicts caused by multi-task concurrency by performing half-cycle offset scheduling on the first type of task satisfying the half-cycle offset scheduling condition, thereby helping to improve the efficiency and reliability of PLC task scheduling.

[0067] In the technical solutions of the present disclosure, the acquisition, storage and application of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0068] Figure 8 FIG. 1 is a structural block diagram of a computer device according to an embodiment of the present disclosure. As shown in FIG. 1, the computer device comprises a processor 10, a memory 20, a storage 30, a power supply 40, an input device 50, an output device 60 and a communication interface 70. Figure 8As shown, the computer device includes a memory 810 and a processor 820, and the memory 810 stores a computer program capable of running on the processor 820. The number of the memory 810 and the processor 820 can be one or more. The memory 810 can store one or more computer programs, which, when executed by the computer device, enable the computer device to perform the method provided by the above-mentioned method embodiments. The computer device can further include a communication interface 830 for communicating with external devices and performing data interaction transmission.

[0069] If the memory 810, the processor 820 and the communication interface 830 are independently implemented, the memory 810, the processor 820 and the communication interface 830 can be connected with each other through a bus and complete communication therebetween. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the figure to represent the memory 810, the processor 820 and the communication interface 830, but it does not mean that there is only one bus or only one type of bus.

[0070] Optionally, if the memory 810, the processor 820 and the communication interface 830 are integrated on a chip, the memory 810, the processor 820 and the communication interface 830 can complete communication therebetween through an internal interface.

[0071] It should be understood that the above-mentioned processor can be a Central Processing Unit (CPU), and can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It should be noted that the processor can be a processor supporting Advanced RISC Machines (ARM) architecture.

[0072] Further, the aforementioned memory can include a read-only memory, and a random access memory, and can further include a non-volatile random access memory. The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memory. Among them, the non-volatile memory can include a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can include a random access memory (RAM) used as an external cache. By way of example, and not limitation, a number of forms of RAM can be used. For example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced SDRAM (ESDRAM), a Synchlink DRAM (SLDRAM), and a direct RAMBUS RAM (DR RAM) can be employed.

[0073] In the above embodiments, all or part of the steps can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the steps can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present disclosure are generated. The computer can be a general purpose computer, a special purpose computer, a computer network or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (for example: coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example: infrared, Bluetooth, microwave, etc.) mode. The computer readable storage medium can be any available medium accessible by a computer, or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example: floppy disk, hard disk, magnetic tape), an optical medium (for example: digital versatile disc (DVD)) or a semiconductor medium (for example: solid state disk (SSD)) and the like. It is worth noting that the computer readable storage medium mentioned in the present disclosure can be a non-volatile storage medium, in other words, it can be a non-transitory storage medium.

[0074] A person of ordinary skill in the art can understand that all or part of the steps of the above embodiments can be completed by hardware, or the program can instruct the related hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0075] In the description of the embodiments of the present disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0076] The above merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Accordingly, any modification, equivalent replacement or improvement made without departing from the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.

Claims

1. A method for scheduling PLC tasks, characterized in that, The method comprises: triggering a plurality of first type tasks when detecting a semaphore of a clock reference task; performing half-cycle offset scheduling on the first type task when detecting that the first type task meets a half-cycle offset scheduling condition.

2. The method of claim 1, wherein, The method further comprises triggering a plurality of second type tasks when detecting a semaphore of an interrupt state.

3. The method of claim 2, wherein, The priority of the second type task is higher than that of the first type task, and when detecting the semaphore of the interrupt state while running the first type task, interrupting the first type task and running the second type task.

4. The method of claim 1, wherein, The half-cycle offset scheduling condition is calculated according to the following formula: tn_res=(TickCount+Tn / 2)%Tn; Wherein, tn_res represents a half-cycle offset scheduling condition, TickCount represents a global counter, and Tn represents a running cycle of the first type task.

5. The method of claim 4, wherein, The global counter is used to count the running cycle of the first type task, and the rule for the global counter to count the running cycle of the first type task is: TickCount=TickCount+1; TickCount=(TickCount+1)%T5.

6. The method of claim 5, wherein, The half-cycle offset scheduling on the first type task when detecting that the first type task meets a half-cycle offset scheduling condition comprises: When detecting that the first type task meets a half-cycle offset scheduling condition, binding the first type task with a first program organization unit to generate a first application program; When detecting that the first application program runs, scheduling the first type task to control the first program organization unit in the first type task to execute a first target instruction.

7. The method of claim 1, wherein, The triggering of a plurality of first type tasks when detecting a semaphore of a clock reference task comprises: When detecting a semaphore of a clock reference task, configuring a plurality of first type tasks according to a preset running interval; Binding a plurality of the first type tasks with a plurality of second program organization units to generate a second application program; When detecting that the second application program runs, calculating a first scheduling condition corresponding to each of a plurality of the first type tasks respectively; When detecting that the first type task meets the first scheduling condition, scheduling the first type task to control the second program organization unit in the first type task to execute a second target instruction.

8. The method of claim 2, wherein, The triggering of a plurality of second type tasks when detecting a semaphore of an interrupt state comprises: Initializing a second scheduling condition of a plurality of the second type tasks, binding a plurality of the second type tasks with a plurality of third program organization units to generate a third application program; Real-time monitoring of an interrupt state of a plurality of the second type tasks, when detecting a semaphore of the interrupt state, scheduling the second type task meeting the second scheduling condition to control the third program organization unit in the second type task to execute a third target instruction.

9. The method of claim 7, wherein, The method further comprises: after the first type of task is subjected to the half-cycle offset scheduling, setting the preset running interval according to a target requirement, so that one running cycle executes one first type of task.

10. A PLC task scheduling apparatus characterized by comprising: The device comprises: A first triggering module is configured to trigger a plurality of first type of tasks when detecting a semaphore of a clock reference task; A scheduling module is configured to subject the first type of task to half-cycle offset scheduling when detecting that the first type of task meets a half-cycle offset scheduling condition. 11.An electronic device comprising a processor and a memory, wherein the memory stores a computer program, and the processor invokes the computer program in the memory to execute the PLC task scheduling method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the memory, and the computer program is loaded by a processor to execute the PLC task scheduling method according to any one of claims 1 to 9.

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