Verification method and system of register in different PCIe reset modes

Abstract

The invention provides a method and a system for verifying registers in different PCIe reset modes, and belongs to the technical field of PCIe chip verification. The method comprises the following steps: on the basis of a UVM expansion register field class, adding a viscous attribute for identifying a viscous register and a reset attribute for identifying a reset influence to the UVM expansion register field class; defining a mapping relationship between a reset type and a register attribute, and configuring a corresponding reset expected value; rewriting the reset function to selectively update the register value according to the reset type and attribute; a reset event is automatically recognized through intelligent monitoring, reset is triggered, and a verification sequence is called for automatic inspection. The system correspondingly comprises an expansion register model, a mapping configuration module, an intelligent monitoring module and an automatic checking control module. According to the invention, automatic and efficient verification of the register state in the PCIe multi-reset mode is realized.

Description

TECHNICAL FIELD

[0001] The application relates to a PCIe register verification method and system under different reset modes, and belongs to the technical field of PCIe chip verification. BACKGROUND

[0002] PCIe registers are various, including HwInit (Hardware Initialized), RO (Read-only), RW (Read-Write), RW1C (Write-1-to-clear status), ROS (Sticky-Read-only), RWS (Sticky-Read-Write) and RW1CS (Sticky-Write-1-to-clear status). The state logic of registers of different types after reset is complex.

[0003] PCIe protocol defines multiple reset mechanisms, including COLD Reset, WARM Reset, HOT Reset and FLR (Function Level Reset). The influence range of different reset modes on registers is significantly different. COLD Reset resets all registers except sticky registers to the initial value, HOT Reset resets link-related registers and configuration-related registers, but does not reset LTSSM (Link Training State Status Machine) registers and sticky registers, and FLR only resets the registers of the target function, and does not affect HwInit type registers, link control registers and sticky registers.

[0004] The traditional verification method has the following pain points: The reset () function of the existing RAL model only supports HARD and SOFT reset types by default, and cannot be extended to multiple reset scenarios of PCIe. After PCIe is reset, the register needs to be manually scanned and the correctness of the reset value of the register needs to be verified, which is low in efficiency. The register types in the RAL model in the existing UVM do not include ROS, RWS and RW1CS type registers, and the sticky registers cannot be effectively verified. SUMMARY

[0005] The application provides a PCIe register verification method and system under different reset modes, and solves the problems of low verification efficiency and poor adaptability of register state under different reset modes of PCIe, and realizes automatic and rapid checking of the register state after reset.

[0006] The application achieves the above-mentioned purpose through the following technical solutions. A verification method of a register in different reset modes of PCIe, comprising the following steps: The uvm_reg_field class of the UVM register field is extended to be pcie_reg_field; In the configuration function of the pcie_reg_field class, sticky attributes and reset attributes are added to the register field, and corresponding reset expected values are set for different reset attributes; The reset function of the pcie_reg_field class is rewritten, so that whether to perform a reset operation on the register field and update the value to the corresponding reset expected value can be dynamically determined according to the input reset type parameter and the sticky attribute and reset attribute of the register field; The register model set constructed based on the pcie_reg_field class is integrated into the verification environment and an intelligent monitoring and prediction model; When the intelligent monitoring and prediction model detects a specific reset event, the reset function of the register model is automatically called to automatically reset and check the register value.

[0007] Preferably, the reset attribute includes cold reset, warm reset, hot reset and function-level reset.

[0008] Preferably, the logic of the reset function includes: If a PERST signal or a main power-on signal is detected, the reset type is cold reset, and the state machine register, hardware logic register, configuration register and sticky register field are reset; If the PERST signal is detected and the main power supply is not turned off, the reset type is warm reset, and the state machine register, hardware logic register, configuration register and sticky register field are reset; If the TS1 sequence HOT Reset bit or the Secondary Bus Reset bit is detected, the reset type is hot reset, and the link-related register, configuration register, sticky register and link training state register field are reset; If the Device Control register FLR bit is detected, the reset type is function-level reset, and the internal state register, sticky register, HwInit register and extended Capability register field of the target Function are reset.

[0009] Preferably, the intelligent monitoring and prediction model identifies reset events by monitoring specific bits of the PCIe link's signals or configuration registers, including cold reset triggered by the PERST signal or main power up, warm reset triggered by the PERST signal, hot reset triggered by the TS1 sequence or Secondary Bus Reset, and function level reset triggered by the DeviceControl register FLR bit.

[0010] Preferably, the register value is reset and checked by a hardware reset sequence built into the register value.

[0011] Preferably, the sticky attribute is 1 for a sticky register and 0 for a non-sticky register.

[0012] A verification system for PCIe registers in different reset modes, comprising: An extension module for providing a PCIe register field class pcie_reg_field extended from a UVM register field class, the class containing a rewritten configuration function and a reset function; A register model generation module for generating a corresponding register model based on the pcie_reg_field class and according to a user-defined register sticky attribute and reset attribute; A monitoring module for constructing the intelligent monitoring and prediction model to monitor reset events in the PCIe link; An integration and execution environment for integrating the register model and the monitoring module into a verification platform and automatically invoking a reset verification process when a reset event is monitored.

[0013] The present application has the advantages of supporting all PCIe reset modes, being compatible with the state logic of special registers such as sticky registers and HwInit, dynamically predicting and checking in parallel without manual intervention, reducing human errors, and significantly improving verification efficiency. The problems of low verification efficiency and poor adaptability of PCIe registers in different reset modes are solved, and the present application can be widely applied in functional verification of PCIe controllers, endpoint devices and other chips. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, illustrate the application, and are used to explain the application together with the embodiments of the application, and do not constitute a limitation on the application.

[0015] Figure 1 The present application is a method flowchart. DETAILED DESCRIPTION

[0016] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0017] Embodiment 1 As shown in the figure, a verification method of a PCIe different reset mode register comprises the following steps: Figure 1 S1: extending the UVM register field class uvm_reg_field to pcie_reg_field; S2: in the configuration function of the pcie_reg_field class, adding sticky attributes and reset attributes to the register field, and setting corresponding reset expected values for different reset attributes; S3: rewriting the reset function of the pcie_reg_field class, so that it can dynamically determine whether to perform a reset operation on the register field and update its value to the corresponding reset expected value according to the input reset type parameter and the sticky attributes and reset attributes of the register field; S4: integrating the register model constructed based on the pcie_reg_field class and the intelligent monitoring and prediction model into the verification environment; S5: when the intelligent monitoring and prediction model detects a specific reset event, automatically calling the reset function of the register model to automatically reset and check the register value.

[0018] As a refinement of the above embodiment, the reset attribute includes cold reset, warm reset, hot reset, and function level reset.

[0019] As a refinement of the above embodiment, the logic of the reset function includes: If the PERST signal or the main power-on signal is detected, the reset type is cold reset, and the state machine register, hardware logic register, configuration register and sticky register field are reset; If the PERST signal is detected and the main power supply is not turned off, the reset type is warm reset, and the state machine register, hardware logic register, configuration register and sticky register field are reset; If the TS1 sequence HOT Reset bit or Secondary Bus Reset bit is detected, the reset type is hot reset, and the link related register, configuration register, sticky register, and link training state register field are reset; ​If the FLR bit in the Device Control register is detected, the reset type is a function-level reset, which resets the internal status register, sticky register, HwInit register, and extended Capability register fields of the target function.

[0020] As a refinement of the above embodiments, the intelligent monitoring and prediction model identifies reset events by monitoring signals of the PCIe link or specific bits of the configuration register. The reset events include cold resets triggered by the PERST signal or mains power-on, warm resets triggered by the PERST signal, thermal resets triggered by the TS1 sequence or Secondary Bus Reset, and function-level resets triggered by the FLR bit of the Device Control register.

[0021] As a refinement of the above embodiments, the register value is reset and checked through a hardware reset sequence built into the register value.

[0022] As a refinement of the above embodiments, a viscosity property of 1 indicates a viscous register, and a viscosity property of 0 indicates a non-viscous register.

[0023] The code examples for steps S2-S3 are as follows: class pcie_reg_field extends uvm_reg_field; / / pcie_reg_field inherits from uvm_reg_field string m_reg_rst_arrtribute; / / Newly added register reset attribute bit m_sticky; / / Newly added sticky attribute function void configure(uvm_reg parent, int unsigned size, int unsigned lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible, bit sticky, / / Newly added sticky property string reg_rst_arrtribute / / Newly added register reset attribute); ... / / The original built-in code of UVM is omitted here. m_reg_rst_arrtribute=reg_rst_arrtribute; m_sticky=sticky; if(has_reset) begin / / Set expected values ​​for different reset types set_reset(reset, "HARD"); set_reset(reset, "COLD"); / / Cold reset value set_reset(reset, "WARM"); / / Warm reset value set_reset(reset, "HOT"); / / Hot reset value set_reset(reset, "FLR0"); / / function 0 resets the value / / Reset value of function1-(N-1) omitted here set_reset(reset, "FLRN"); / / function N resets the value end function void reset(kind = “HARD”); Case(kind): “HARD”: value = m_reset[kind]; / / Reset all registers. “COLD”: if(reg_rst_arrtribute== (“COLD” || “WARM” || “HOT” || “FLR0-N”)&&(!sticky)) value = m_reset[kind]; / / Resets all registers except sticky = 1 during a cold reset. end “WARM”: if(reg_rst_arrtribute== ("WARM"||"HOT"||"FLR0-N")&&(!sticky) ) value = m_reset[kind]; / / Resets all registers except sticky = 1 during a warm reset. end “HOT”: if(reg_rst_arrtribute== ("HOT"||"FLR0-N")&&(!sticky) ) value = m_reset[kind]; / / Resets all registers except sticky=1 during a hot reset. end “FLR0”: if(reg_rst_arrtribute== ("FLR0")&&(!sticky) ) value = m_reset[kind]; / / When FLR0 is reset, all registers in function 0 except sticky = 1 are reset. end ... / / Reset of FLR1-(N-1) omitted “FLRN”: if(reg_rst_arrtribute== ("FLRN")&&(!sticky) ) value = m_reset[kind]; / / When FLRN is reset, it resets all registers in N except sticky = 1. end endcase Endclass The code example for step S5 is as follows: virtual task monitor_reset_events(); fork forever begin @(cold reset event); reg_model.reset("COLD"); Start the built-in UVM sequence uvm_reg_hw_reset_seq and check the default value. end forever begin @(Hot reset event); reg_model.reset("WARM"); Start the built-in UVM sequence uvm_reg_hw_reset_seq and check the default value. end ... forever begin @(Function 0 Reset Event); reg_model.reset("FLR0"); Start the built-in UVM sequence uvm_reg_hw_reset_seq and check the default value. end / / reset of function 0 Function 1-(N-1) reset mechanism omitted here. forever begin @(Function N Reset Event); reg_model.reset("FLRN"); Start the built-in UVM sequence uvm_reg_hw_reset_seq and check the default value. end join_none endtask Example 2 In this embodiment, the scenario is that PCIe is used as the endpoint, there are a total of 8 functions, and a COLD reset is performed.

[0024] Step 1: Expand uvm_reg_field to pcie_reg_field.

[0025] Step 2: Rewrite the configure() function in pcie_reg_field, and add the sticky attribute and reset attribute (reg_rst_arrtribute) to the register. reg_rst_arrtribute has the following values: "COLD", "WARM", "HOT", "FLR0", "FLR1", "FLR2", "FLR3", "FLR4", "FLR5", "FLR6", and "FLR7".

[0026] Step 3: In the configure() function, set the reset values ​​of the 11 reg_rst_arrtributes mentioned in Step 2.

[0027] Step 4: Rewrite the reset() function in pcie_reg_field to reset the 11 reg_rst_arrtributes mentioned in Step 2 according to the reset type and sticky attribute.

[0028] Step 5: When the user generates registers using the uvm register model, the register fields use the uvm_reg_field mentioned in step 1, and the sticky attribute and register reset attribute are passed in as required.

[0029] Step 6: Create an intelligent monitoring and prediction model.

[0030] Step 7: Integrate the register model into the verification environment.

[0031] Step 8: Integrate the intelligent monitoring and prediction model into the validation environment.

[0032] Step 9: When a PCIe cold reset occurs, the intelligent monitoring and prediction model detects the cold reset event and sets the values ​​of the registers with reset types "COLD", "WARM", "HOT", "FLR0", "FLR1", "FLR2", "FLR3", "FLR4", "FLR5", "FLR6", and "FLR7" and sticky=0 to the reset values. Then, it calls the built-in uvm sequence uvm_reg_hw_reset_seq to check all registers.

[0033] Example 3 In this embodiment, the scenario is that PCIe is used as the endpoint, there are two functions, and an FLR0 reset is performed.

[0034] Step 1: Expand uvm_reg_field to pcie_reg_field.

[0035] Step 2: Rewrite the configure() function in pcie_reg_field, and add the sticky and reset attributes (reg_rst_arrtribute) to the register. reg_rst_arrtribute has "COLD", "WARM", "HOT", "FLR0", "FLR1" and "WARM".

[0036] Step 3: In the configure() function, set the reset values ​​of the 11 reg_rst_arrtributes mentioned in Step 2.

[0037] Step 4: Rewrite the reset() function in pcie_reg_field to reset the five reg_rst_arrtributes mentioned in Step 2 according to the reset type and sticky attribute.

[0038] Step 5: When the user generates registers using the uvm register model, the register fields use the uvm_reg_field mentioned in step 1, and the sticky attribute and register reset attribute are passed in as required.

[0039] Step 6: Create an intelligent monitoring and prediction model.

[0040] Step 7: Integrate the register model into the verification environment.

[0041] Step 8: Integrate the intelligent monitoring and prediction model into the validation environment.

[0042] Step 9: When a PCIe FLR0 reset occurs, the intelligent monitoring and prediction model detects the FLR0 reset event and sets the value of the "FLR0" type register with sticky=0 to the reset value, while leaving the values ​​of other types of registers unchanged. Then, it calls the built-in uvm sequence uvm_reg_hw_reset_seq to check all registers.

[0043] Example 4 A verification system for registers under different PCIe reset modes includes: The extension module provides a PCIe register field class (pcie_reg_field) that extends the UVM register field class. This class contains overridden configuration and reset functions. The register model generation module is used to generate a corresponding register model based on the pcie_reg_field class and according to the user-defined register stickiness and reset attributes. The monitoring module is used to build the intelligent monitoring and prediction model to monitor reset events in the PCIe link; An integration and execution environment is provided to integrate the register model and the monitoring module into the verification platform, and to automatically invoke the reset verification process when a reset event is detected.

[0044] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for verifying registers under different PCIe reset modes, characterized in that, Includes the following steps: The UVM register field class uvm_reg_field is extended to pcie_reg_field; In the configuration function of the pcie_reg_field class, add sticky and reset attributes to the register fields, and set corresponding expected reset values ​​for different reset attributes; The reset function of the pcie_reg_field class is rewritten so that it can dynamically determine whether to perform a reset operation on the register field and update its value to the corresponding expected reset value based on the input reset type parameter and the stickiness and reset attributes of the register field. Integrate the register model built based on the pcie_reg_field class and the intelligent monitoring and prediction model into the verification environment; When the intelligent monitoring and prediction model detects a specific reset event, it automatically invokes the reset function of the register model to automatically reset and check the register values.

2. The verification method for registers under different PCIe reset modes according to claim 1, characterized in that, The reset attributes include cold reset, warm reset, hot reset, and functional level reset.

3. The verification method for registers under different PCIe reset modes according to claim 1 or 2, characterized in that, The logic for the reset function includes: If the PERST signal or the main power-on signal is detected, the reset type is cold reset, which resets the state machine register, hardware logic register, configuration register and sticky register fields; If the PERST signal is detected and the main power is not turned off, the reset type is a warm reset, which resets the state machine register, hardware logic register, configuration register and sticky register fields. If the TS1 sequence HOT Reset bit or Secondary Bus Reset bit is detected, the reset type is hot reset, and the fields of the link-related registers, configuration registers, sticky registers, and link training status registers are reset; If the FLR bit in the Device Control register is detected, the reset type is a function-level reset, which resets the internal status register, sticky register, HwInit register, and extended Capability register fields of the target function.

4. The verification method for registers under different PCIe reset modes according to claim 1, characterized in that, The intelligent monitoring and prediction model identifies reset events by monitoring signals of the PCIe link or specific bits of the configuration register. These reset events include cold resets triggered by the PERST signal or mains power-on, warm resets triggered by the PERST signal, thermal resets triggered by the TS1 sequence or Secondary Bus Reset, and function-level resets triggered by the FLR bit of the Device Control register.

5. The verification method for registers under different PCIe reset modes according to claim 1, characterized in that, The register value is reset and checked using the hardware reset sequence built into the register value.

6. The verification method for registers under different PCIe reset modes according to claim 1, characterized in that, A viscosity property of 1 indicates a viscous register, while a viscosity property of 0 indicates a non-viscous register.

7. A system for verifying registers under different PCIe reset modes, used to implement the verification method for registers under different PCIe reset modes as described in any one of claims 1-6, characterized in that, include: An extension module is provided to provide a PCIe register field class pcie_reg_field that extends the UVM register field class. This class contains overridden configuration and reset functions. The register model generation module is used to generate a corresponding register model based on the pcie_reg_field class and according to the user-defined register stickiness and reset attributes. The monitoring module is used to build the intelligent monitoring and prediction model to monitor reset events in the PCIe link; An integration and execution environment is provided to integrate the register model and the monitoring module into the verification platform, and to automatically invoke the reset verification process when a reset event is detected.

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