System and method for realizing content addressable memory in FPGA (Field Programmable Gate Array), electronic equipment and medium

Abstract

The invention discloses a system and a method for realizing a content addressable memory (CAM) in a field programmable gate array (FPGA), electronic equipment and a medium, and belongs to the technical field of semiconductor memorizers, the system comprises a storage table item updating module for recoding data and addresses which need to be stored in a current content addressable memory (CAM), generating new write-in signals, addresses and data, and storing the new write-in signals, addresses and data in the FPGA; preparing to write data into the BlockRAM module; the Block RAM module is used for storing the encoded table items; and the matching result output module is used for inputting to-be-matched contents, reading the storage data from the BlockRAM module, decoding the storage data and generating matching address information. The method has the advantages of low complexity, low power consumption, high performance and easiness in implementation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor memory, and more particularly, to a system, method, electronic device and medium for implementing a content-addressable memory in an FPGA. BACKGROUND

[0002] Content-Addressable Memory (CAM) is a special computer memory. Unlike the working mechanism of traditional address-based Random Access Memory (RAM) (input an address, return the data stored at the address), the working mechanism of CAM is: input a search data (or called "key value"), CAM will compare it with all the entries stored in the internal, and return one or more addresses of the entries that match the data. The "parallel search" feature makes CAM irreplaceable in the fields that require ultra-fast search function, such as network packet routing, cache controller, database acceleration, pattern recognition, etc.

[0003] Traditional CAM is usually implemented as an Application-Specific Integrated Circuit (ASIC), which has extremely high performance but lacks flexibility. Since FPGA has the advantages of reprogrammability and short development cycle, more and more systems tend to implement the entire design in FPGA, including the fast search function originally handled by dedicated CAM chips.

[0004] Currently, the mainstream method for implementing CAM in FPGA mainly relies on its core programmable logic resources, i.e. Look-Up Tables (LUTs) and Flip-Flops. By configuring each storage bit as multiple comparators, LUT can effectively implement the parallel comparison function of CAM. However, this so-called "Distributed RAM or LUT-based CAM implementation" has several significant inherent defects: 1) High resource consumption: Each storage bit requires an independent comparator circuit. For a CAM table with a width of W bits and a depth of D, the number of comparators required is WxD. This will cause the consumption of LUT and register resources to grow quadratically with the expansion of CAM capacity, quickly depleting the logic resources of FPGA, greatly increasing the implementation cost and limiting the available capacity of CAM.

[0005] 2) High power consumption: Each search operation will activate the comparator circuits of all D entries for parallel comparison. This large-scale simultaneous switching activity will result in very high dynamic power consumption, especially in large-capacity CAM applications, becoming a serious burden on system heat dissipation and power budget.

[0006] 3) Poor scalability: due to the limitation of logic resources, the capacity and bit-width of LUT-based CAM is strictly constrained by the total amount of resources available in a single FPGA device. Designers often need to make a difficult compromise among functionality, capacity and cost.

[0007] On the other hand, modern FPGA devices are usually equipped with a large number of Block RAMs (BRAMs) built-in. BRAM is a special, large-capacity embedded memory unit in FPGA, whose density is much higher than that of distributed RAM composed of LUTs. The traditional usage of BRAM is consistent with that of standard RAM, i.e. for sequential storage and reading of data. Since its original design intention is to store rather than compare, BRAM itself does not have any built-in parallel content comparison function. SUMMARY

[0008] The present application aims to overcome the deficiencies of the prior art, and provide a system, method, electronic device and medium for implementing a content addressable memory in an FPGA, which has the advantages of low complexity, low power consumption, high performance and easy implementation.

[0009] The present application is achieved by the following scheme: A system for implementing a content addressable memory in an FPGA, comprising a storage entry update module, a BlockRAM module and a matching result output module; The storage entry update module is configured to re-encode data and address to be stored in the current content addressable memory CAM, to generate new write signals, addresses and data, and to prepare to write the data into the BlockRAM module; The BlockRAM module is configured to store the encoded entries; The matching result output module is configured to input a content to be matched, to read out the stored data from the BlockRAM module and to decode the data, to generate matching address information.

[0010] Further, the storage entry update module has each port bit-width adjusted according to input parameters, to change the input entry bit-width and the number of entry items.

[0011] Further, the BlockRAM module uses a matrix arrangement to increase the storage capacity according to the number of entry items to be stored.

[0012] Further, the BlockRAM module comprises a 16K-bit BRAM module in the FPGA.

[0013] Further, the matching result output module adjusts the bit-width of the output address according to the entire CAM capacity.

[0014] Further, the matching result output module adjusts the bit width of the output address according to the whole CAM capacity.

[0015] A method for implementing a content addressable memory in an FPGA, based on the system for implementing a content addressable memory in an FPGA as described above, performs the following steps: S1, re-encoding the data and address to be stored in the current content addressable memory CAM to generate new write signals, address, data, and preparing to write the data into the BlockRAM module; S2, the BlockRAM module stores the encoded table entries; S3, inputting the content to be matched, reading out the stored data from the BlockRAM module and decoding to generate matching address information.

[0016] An electronic device comprising a processor and a memory, the memory storing a computer program, when the computer program is loaded by the processor and executes the method according to any one of the above.

[0017] A computer readable storage medium, in which a computer program is stored, the computer program is loaded by a processor and executes the method according to any one of the above.

[0018] The beneficial effects of the present application include: The present application can overcome the fundamental shortcomings of the existing LUT-based CAM implementation method, fully utilize the existing hardware resources of the FPGA chip, significantly reduce the resource occupation and power consumption of the CAM function, and provide excellent scalability, so that it is possible to implement a low-power and high-performance CAM in an FPGA.

[0019] The present application provides a method for implementing a CAM in an FPGA, which balances the target table entry query rate and the logic unit usage amount, obtains a very high query rate while using fewer logic units, and provides a technical solution for high-bandwidth network communication. In actual application, the capacity of the CAM can be increased by increasing the number of BlockRAMs to form a RAM matrix, so that the number of internal storage table entries is multiplied. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1The overall block diagram of the content addressable memory of the embodiment system of the present application; Figure 2 The schematic diagram of address conversion in the BlockRAM in the embodiment system of the present application. DETAILED DESCRIPTION

[0022] All features disclosed in this specification, and / or the steps of any method or process specified in this specification, can be combined in any combination, and / or substituted for one another, except insofar as specifically stated otherwise.

[0023] As a first aspect of the present application, a system for implementing a content addressable memory (CAM) in an FPGA is provided, comprising: a storage entry update module, a BlockRAM module, and a matching result output module; The storage entry update module re-encodes data and an address to be stored in the current CAM, generates new write signals, addresses, and data, and prepares to write the data into the BlockRAM module. The BlockRAM module is used for storing the encoded entries, and the BlockRAM uses a 16K bit BRAM module in the FPGA. The matching result output module inputs content to be matched, reads out the stored data from the BlockRAM module and decodes the data, and generates matching address information.

[0024] In a further embodiment, the storage entry update module can adjust the bit width of each port according to input parameters, and change the bit width of the input entries and the number of entry items.

[0025] In a further embodiment, the BlockRAM module can use a matrix arrangement to increase the storage capacity according to the number of entry items to be stored.

[0026] In a further embodiment, the matching result output module can adjust the bit width of the output address according to the capacity of the entire CAM.

[0027] In a further embodiment, the matching result output module can adjust the bit width of the output address according to the capacity of the entire CAM.

[0028] As a second aspect of the present application, based on the above system embodiment, a method for implementing a content addressable memory (CAM) in an FPGA is provided, based on the above system for implementing a content addressable memory in an FPGA, the following steps are performed: S1, re-encode data and an address to be stored in the current content addressable memory CAM, generate new write signals, addresses, and data, and prepare to write the data into the BlockRAM module; S2, the BlockRAM module stores the encoded table entry; S3, input the content to be matched, read out the stored data from the BlockRAM module and decode to generate the matching address information.

[0029] In other embodiments, based on the above-mentioned embodiment method, a method for implementing a content addressable memory in an FPGA is further provided, which is described in detail as follows: Figure 1 The figure is a whole block diagram of the present application, Figure 2 is a schematic diagram of address conversion in the BlockRAM. In combination with Figure 1 and Figure 2 The specific steps are described in detail as follows by taking a 16K bit BRAM as an example: Step (1), first, 32 pieces of 9-bit data are planned to be stored in a 16K bit BRAM, i.e. 5-bit address bit width and 9-bit data bit width; Step (2), when a table entry needs to be entered into the CAM, such as write address 01001 and write data 010110111; Step (3), the address data encoding logic combines the 9-bit data and the 5-bit data into 14-bit data, {010110111, 01001}; Step (4), the 14-bit data {010110111, 01001}, i.e. decimal 5865, is taken as an address, and the BlockRAM write control logic writes 1 into the address as an identifier, indicating that the current table entry has been stored in the CAM; Step (5), when it is needed to query whether the current CAM stores data 010110111, only 010110111 needs to be input into the "to-be-queried data" port; Step (6), the BlockRAM read control logic takes 010110111 (decimal 183) input from the "to-be-queried data" port as an address and reads the 32-bit content in the address 183; Step (7), the 32-bit content read from the address 183 is 00000000010000000000000000000000, and the leftmost bit of the binary data indicates whether a table entry is stored in the decimal address 5856, and the bits from left to right represent the addresses 5857... to 5887 in increasing order; Step (8), it is found that there is an identifier in the decimal address 5865, indicating that a table entry is stored in the current position; Step (9), the binary data is sent into the matching result decoding logic, the decoding logic takes the leftmost bit in the binary data as the identification of whether the entry is stored in the 0 address, searches from left to right in sequence, until the first bit stored is 1, converts the position of the bit to an address output, and from the binary data, data 1 corresponds to address 9, i.e. binary 01001, and the address is output as the query result.

[0030] In conclusion, the technical scheme of the present application designs a method for implementing CAM in FPGA, which can achieve high-speed query rate with very small hardware usage area, and the writing of the stored entry only needs one clock, and the writing of the query data to the address output of the query result also only needs one clock, thereby reducing the design complexity, and without additional hardware or algorithm IP for implementing high-speed addressing operation. The method is easy to implement on FPGA and ASIC.

[0031] In other embodiments, an electronic device is provided, which includes a processor and a memory, and the memory stores a computer program, when the computer program is loaded by the processor and executed, the method according to any one of the above embodiments is performed.

[0032] The units described in the embodiments of the present application can be implemented in the form of software, or can be implemented in the form of hardware, and the described units can also be arranged in a processor. In some cases, the names of the units do not constitute a limitation on the units themselves.

[0033] According to other aspects of the embodiments of the present application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method provided in the various optional implementation manners.

[0034] The embodiments of the present application also provide a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist separately without being assembled into the electronic device. The computer readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device implements the method described in the above embodiments.

Claims

1. A system for implementing content-addressable memory in an FPGA, characterized in that, It includes a storage table entry update module, a BlockRAM module, and a matching result output module; The storage entry update module is used to re-encode the data and address that need to be stored in the current content-addressable memory (CAM), generate new write signals, addresses, and data, and prepare to write the data into the BlockRAM module. The BlockRAM module is used to store the encoded table entries; The matching result output module takes the content to be matched as input, reads the stored data from the BlockRAM module and decodes it to generate matching address information.

2. The system for implementing content-addressable memory in an FPGA according to claim 1, characterized in that, The storage entry update module adjusts the bit width of each port according to the input parameters, thereby changing the bit width of the input entry and the number of entries.

3. The system for implementing content-addressable memory in an FPGA according to claim 1, characterized in that, The BlockRAM module increases its storage capacity by arranging entries in a matrix manner according to the required number of table entries.

4. The system for implementing content-addressable memory in an FPGA according to claim 1, characterized in that, The BlockRAM module includes a 16K-bit BRAM module in the FPGA.

5. The system for implementing content-addressable memory in an FPGA according to claim 1, characterized in that, The matching result output module adjusts the bit width of the output address according to the total CAM capacity.

6. The system for implementing content-addressable memory in an FPGA according to claim 1, characterized in that, The matching result output module adjusts the bit width of the output address according to the total CAM capacity.

7. A method for implementing content-addressable memory in an FPGA, characterized in that, Based on the system for implementing content-addressable memory in an FPGA as described in claims 1-4, the following steps are performed: S1 re-encodes the data and address that need to be stored in the current content-addressable memory CAM, generating new write signals, addresses, and data, and prepares to write the data into the BlockRAM module; S2, the BlockRAM module stores the encoded table entries; S3, input the content to be matched, read the stored data from the BlockRAM module and decode it to generate matching address information.

8. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when loaded by the processor, executes the method as described in claim 7.

9. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium, the computer program being loaded by a processor and executing the method as described in claim 7.

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