Hardware large page aggregation method, processor and chip

Abstract

The embodiment of the invention relates to a hardware large page aggregation method, a processor and a chip, and relates to the technical field of computers, the hardware large page aggregation method comprises the steps that a page table is traversed to obtain a plurality of page table entries, and the page table entries comprise a target page table entry and a plurality of adjacent page table entries; if the target page table item is a leaf page table item, obtaining an effective leaf page table item from the plurality of adjacent page table items; according to comparison fields in the target page table item and the effective leaf page table item, aggregating the target page table item and the effective leaf page table item; wherein the comparison field is a field influencing the execution of the memory access instruction in a page table item field; and storing the aggregated large page into a translation lookaside buffer.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, specifically to a method for aggregating hardware large pages, a processor, and a chip. Background Technology

[0002] In today's high-performance computing, cloud computing, and big data applications, the operating system's ability to efficiently allocate large pages has become a key performance bottleneck, and proactive software-level optimization of physical memory fragmentation is the core technological support for ensuring this capability. With the exponential growth of application data scale (such as AI model training, in-memory databases, and virtualization clusters), the high-frequency Translation Lookaside Buffer Miss (TLB Miss) and page table traversal overhead caused by the traditional 4KB paging mechanism have resulted in performance losses of up to a thousand times. 2MB / 1GB large pages can significantly reduce the number of page table entries, increasing TLB coverage by hundreds of times and significantly reducing address translation latency. However, severe fragmentation of physical memory directly hinders the contiguous allocation of large pages, forcing the operating system to revert to small-page mode, causing a precipitous drop in performance. Modern operating systems proactively migrate fragmented physical pages and reserve contiguous memory areas through software-level optimization techniques such as memory consolidation and contiguous memory allocators, ensuring the on-demand allocation of hundreds of MB or even GB-level large pages. This optimization supports the fundamental premise of key technologies such as RDMA high-speed networks, GPU Direct Memory Access (GPUDirect), and persistent memory pools. However, without contiguous physical memory, hardware acceleration capabilities cannot be fully realized.

[0003] Based on software optimizations for contiguous physical memory, operating systems have more opportunities to allocate large pages such as 2MB / 1GB. However, in the RISC-V architecture's NAPOT (Naturally Aligned Power-Of-Two) large page mode, the current design has a clear granularity limitation: it only supports aggregating 16 4KB base pages into a 64KB large page using consecutive bits (N bits), lacking the ability to aggregate higher-order large pages (such as 2MB / 1GB). This limitation causes significant performance bottlenecks in server-level applications. Summary of the Invention

[0004] The purpose of the embodiments in this specification is to provide a method, processor, and chip for aggregating hardware big pages, so as to overcome the problem that existing methods lack the ability to aggregate high-order big pages.

[0005] To solve the above-mentioned technical problems, the specific technical solutions of the embodiments in this specification are as follows:

[0006] On the one hand, embodiments of this specification provide a method for aggregating hardware large pages, including:

[0007] The page table is traversed to obtain multiple page table entries, which include the target page table entry and multiple adjacent page table entries.

[0008] If the target page table entry is a leaf page table entry, obtain a valid leaf page table entry from the plurality of adjacent page table entries;

[0009] Aggregate the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry; wherein, the comparison fields are the fields in the page table entry that affect the execution of memory access instructions;

[0010] Store the aggregated large pages to the translation back buffer.

[0011] Furthermore, the page table entry fields also include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field;

[0012] The aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes:

[0013] If the target page table entry and the valid leaf page table entry satisfy the full aggregation condition, the independent state fields in the target page table entry and the valid leaf page table entry are cached in the translation back buffer;

[0014] The full aggregation conditions include: the number of valid leaf page entries is equal to the number of adjacent page entries, each valid leaf page entry is consistent with the target page entry in the comparison field, and the low-order bits of the hardware address in the target page entry and the valid leaf page entries are consecutive.

[0015] Furthermore, the page table entry fields also include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field;

[0016] The aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes:

[0017] If the target page table entry and the valid leaf page table entry satisfy the partial aggregation condition, then the independent status field and the low-order hardware address field in the target page table entry and the valid leaf page table entry are cached in the translation backup buffer;

[0018] The aggregation conditions include: the number of valid leaf page entries is greater than zero and less than the number of adjacent page entries, and each valid leaf page entry is consistent with the target page entry in the comparison field.

[0019] Furthermore, the independent status field does not include the read field and / or the execute field.

[0020] Further, the aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes:

[0021] If each valid leaf page table entry and the target page table entry have at least one inconsistency in the comparison fields, the hardware big page mapping corresponding to the target page table entry is cached in the translation back buffer.

[0022] Furthermore, storing the aggregated large pages to the translation back buffer includes:

[0023] Aggregate multiple hardware big page mappings corresponding to the target page table entry and the valid leaf page table entry into a single hardware big page mapping;

[0024] Store the aggregated hardware big page map to the translation back buffer.

[0025] Furthermore, the memory access instructions include at least read instructions and write instructions.

[0026] Furthermore, if the target page table entry is not a leaf page table entry, the next level page table traversal continues according to the next level page table indicated by the target page table entry.

[0027] Furthermore, embodiments of this specification provide a hardware large-page aggregation device, comprising:

[0028] The traversal module is used to traverse the page table to obtain multiple page table entries, which include the target page table entry and multiple adjacent page table entries;

[0029] The first acquisition module is used to acquire a valid leaf page table entry from the plurality of adjacent page table entries if the target page table entry is a leaf page table entry.

[0030] The aggregation module is used to aggregate the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry; wherein, the comparison fields are the fields in the page table entry that affect the execution of memory access instructions;

[0031] The storage module is used to store the aggregated large pages to the translation backup buffer.

[0032] Furthermore, embodiments of this specification provide an instruction processing method, including:

[0033] Get memory access instructions;

[0034] Retrieve the aggregated big page hit by the memory access instruction from the translation back buffer;

[0035] If the memory access instruction is a write instruction, perform a page table traversal to obtain the leaf page table entry corresponding to the write instruction.

[0036] Further, if the memory access instruction is a write instruction, performing a page table traversal to obtain the leaf page table entry corresponding to the write instruction includes:

[0037] If a write instruction hits a hardware big page corresponding to an aggregate big page mapping that is at risk of being written in the translation back buffer, a page table traversal is performed to retrieve the leaf page table entry corresponding to the write instruction from memory or cache.

[0038] The operation data corresponding to the write instruction is written into the hardware big page mapped by the leaf page table entry.

[0039] Furthermore, the hardware large page corresponding to the aggregated hardware large page mapping with write risk includes the hardware large page corresponding to the aggregated hardware large page mapping with a dirty field of 0, or the hardware large page corresponding to the aggregated hardware large page mapping with a write field of 0.

[0040] Furthermore, the method also includes:

[0041] If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the dirty field is 0, the hit is ignored.

[0042] Furthermore, the method also includes:

[0043] If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the write field is 0, a page fault occurs.

[0044] Furthermore, embodiments of this specification provide an instruction processing apparatus, including:

[0045] The first acquisition module is used to acquire memory access instructions;

[0046] The second acquisition module is used to acquire the aggregated big page hit by the memory access instruction from the translation back buffer;

[0047] The third acquisition module is used to perform page table traversal to obtain the leaf page table entry corresponding to the write instruction if the memory access instruction is a write instruction.

[0048] Furthermore, embodiments of this specification provide a processor for performing any of the methods described above.

[0049] Furthermore, embodiments of this specification provide a chip including the processor described above for performing any of the methods described above.

[0050] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification can traverse the page table to obtain multiple page table entries, including a target page table entry and multiple adjacent page table entries; if the target page table entry is a leaf page table entry, a valid leaf page table entry is obtained from the multiple adjacent page table entries; the target page table entry and the valid leaf page table entry are aggregated according to the comparison field in the target page table entry and the valid leaf page table entry; wherein, the comparison field is a field in the page table entry field that affects the execution of memory access instructions; the aggregated big page is stored in the translation lookup buffer. Compared with the existing methods, the embodiments of this specification significantly expand the range of hardware address space that a single TLB entry can cover by aggregating and storing the page table entries of multiple consecutive hardware big pages in the TLB, reducing the frequency of TLB failures, reducing the probability of triggering high-overhead page table traversal in subsequent accesses, thereby effectively shortening the average address translation latency and improving the overall execution efficiency of the processor. Meanwhile, by prefetching multiple consecutive page table entries in a single operation, the inherent spatial locality characteristic of program memory access behavior is effectively utilized. This pre-integrates the mapping of adjacent hardware megapages that may be accessed consecutively, making the TLB structure more aligned with actual memory access patterns and improving resource utilization efficiency. Furthermore, a conditional aggregation strategy is employed, where the comparison fields only include fields that affect memory access instructions. Aggregation is then performed only when the comparison field attributes are consistent, ensuring consistency of permissions and states and significantly improving the success rate of aggregation operations.

[0051] This specification embodiment can also obtain memory access instructions; retrieve the aggregated big page hit by the memory access instruction from the translation back buffer; if the memory access instruction is a write instruction, perform page table traversal to obtain the leaf page table entry corresponding to the write instruction. For read instructions, aggregated big page mapping is directly used to achieve performance improvement, while a strict verification process is enabled for write instructions. This approach benefits from the TLB coverage gain brought by aggregated mapping while ensuring the security of storage operations through permission checks down to the subpage level, achieving a balance between efficiency and reliability. Specifically, by strictly limiting time-consuming page table traversal operations to necessary write instruction scenarios, the average system access latency is significantly reduced. This conditional rollback strategy ensures functional integrity while minimizing performance overhead, significantly improving the collaboration efficiency between the processor core and the memory subsystem. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below.

[0053] Figure 1This is a flowchart of a hardware big page aggregation method provided in the embodiments of this specification;

[0054] Figure 2 This is a schematic diagram of the overall process of a method for aggregating 2MB hardware big pages provided in the embodiments of this specification;

[0055] Figure 3 This is a flowchart illustrating the different levels of page table traversal provided in the embodiments of this specification;

[0056] Figure 4 This is a schematic diagram of the structural composition of a hardware large-page aggregation device provided in the embodiments of this specification;

[0057] Figure 5 This is a flowchart of an instruction processing method provided in an embodiment of this specification;

[0058] Figure 6 This is a schematic diagram of the structural composition of an instruction processing device provided in an embodiment of this specification. Detailed Implementation

[0059] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0060] It should be noted that the terms "first," "second," etc., used in this specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0061] In mainstream RISC-CV CPU designs, software-aggregated big pages are primarily used, with clear granularity limitations. It only supports aggregating 16 4KB base pages into a 64KB big page using consecutive bits (N bits). With the development of high-performance computing, cloud computing, and big data applications, and the increasing memory capacity of server CPUs, operating systems are increasingly allocating big pages such as 2MB / 1GB. Aggregating 16 4KB base pages into a 64KB big page is no longer sufficient. However, existing architectures and software ecosystems do not support hardware big page aggregation, thus increasing the number of page table traversals, memory accesses, and TLB utilization efficiency, ultimately impacting system performance.

[0062] In related technologies, when the CPU executes an instruction that requires memory access, it generates a virtual address and sends it to the Memory Management Unit (MMU). The MMU uses the virtual page number at this address as a tag and performs a parallel lookup in the Translation Lookaside Buffer (TLB). If a valid match is found in the TLB, the MMU can obtain the physical page number within 1-2 clock cycles, combine it with the page offset in the virtual address to form a complete physical address, and then the CPU can access the cache or main memory through this address. If no corresponding mapping is found in the TLB, a TLB Miss event is triggered. In this case, the MMU needs to obtain the address translation result through a slower page table traversal mechanism.

[0063] A TLB miss will activate the page table traversal mechanism. The MMU first obtains the physical base address of the current process's root page table from the privilege register. Then, based on the indexes of each segment of the virtual address, it queries the page table hierarchy from top to bottom until it locates a leaf page table entry with a non-zero XWR permission bit at a certain level. Once a leaf page table entry is found, the traversal process terminates immediately, and the physical page number in that entry is the required translation result. While obtaining the final leaf page table entry, the MMU checks its permission bits. If a conflict with the current access mode is detected (such as an attempt to perform a write operation to a read-only page), a page fault exception is triggered.

[0064] After verification, the system caches the mapping relationship between virtual page numbers and physical page numbers obtained during this traversal, along with related permission bits, in the TLB. If the TLB is full, old entries are evicted according to a predetermined replacement policy. Finally, the MMU uses the newly acquired physical page number to generate a physical address, which the CPU uses to continue executing the previously blocked load or store operations.

[0065] Figure 1 This is a flowchart of a hardware big page aggregation method provided in the embodiments of this specification. Figure 2 This is a schematic diagram of the overall logic flow of a 2MB hardware big page aggregation method provided in the embodiments of this specification.

[0066] Small pages can be 4KB in size. Their advantages include high flexibility, high memory utilization, and low fragmentation. The disadvantage is that if a program needs to use a large amount of memory, it requires a large number of page table entries, resulting in a heavy burden on the page tables and TLB.

[0067] Large pages can be memory pages with a larger capacity than small pages, such as 2MB, 1GB, and 512GB memory pages. Their advantages include: a single TLB entry can cover a larger address range, significantly improving TLB hit rate; and during page table traversal, mappings may be found earlier at higher levels, reducing the number of memory accesses.

[0068] Software-based big page aggregation and hardware-based big page aggregation are two different technologies for achieving the big page effect.

[0069] The operating system is the primary entity responsible for executing software big page aggregation. Specifically, when allocating memory, the operating system directly allocates a contiguous, large block of physical memory (e.g., 2MB) and creates a page table entry at a higher level of the page table, marking this entry as a leaf node, thus completing the mapping of the entire big page in one go. Essentially, it allocates first, then maps; that is, the big page is created at the source.

[0070] The execution entity for hardware big page aggregation is the MMU (Memory Management Unit). Specifically, the operating system may still allocate multiple consecutive small big pages (e.g., four consecutive 2MB pages). However, when the MMU traverses the page table, if it finds that these consecutive page table entries have consistent attributes and contiguous physical addresses, it automatically merges them into a larger mapping entry in the TLB (e.g., merging four 2MB pages into one 8MB TLB entry). Essentially, it maps first, then caches; that is, it merges small mappings at the TLB cache level, which is transparent to the operating system. Hardware big page aggregation is a performance optimization that optimizes the caching method of address translation results.

[0071] The hardware big page aggregation method provided in the embodiments of this specification includes the following steps in its specific implementation:

[0072] S101: Traverse the page table to obtain multiple page table entries, including the target page table entry and multiple adjacent page table entries.

[0073] In some embodiments, a page table is a data structure maintained by the operating system for each process, which records the mapping relationship between virtual addresses and physical addresses. Virtual memory is a large, contiguous address space, while physical memory is scattered and finite. The page table allows the CPU to know the actual physical address corresponding to the virtual address it accesses. A page table entry (PTE) is an entry in the page table and is the smallest unit of the mapping relationship. A PTE consists of multiple bytes and contains not only the physical address but also rich control information, such as: the physical page number pointing to the actual physical memory block, read, write, and execute permission bits, status bits such as whether it has been accessed or modified, and other flag bits such as whether it is a global page and whether it can be accessed in user mode.

[0074] In some embodiments, the mapping relationship between virtual addresses and physical addresses can be stored using a multi-level page table structure. The multi-level page table structure includes multiple page tables. These page tables correspond to multiple levels. Each level includes one or more page tables. Each page table contains multiple Page Table Entry (PTE). The multiple page tables include leaf page tables and non-leaf page tables. In non-leaf page tables, page table entries include the physical base address of the next-level page table, used to guide the page table to the next level. In leaf page tables, page table entries include a Physical Page Number (PPN) and a flag. Thus, address translation can be achieved through page table entries between levels.

[0075] In some embodiments, when the CPU executes an instruction that requires memory access, it generates a target virtual address and sends it to the Memory Management Unit (MMU). The MMU can perform a page table traversal based on this target virtual address. The MMU can split the target virtual address to obtain multiple page table indices (VPNs) and a page offset. The number of page table indices can be equal to the number of levels in the multi-level page table structure. Each page table index can correspond to one level. The MMU can determine the number of bits based on the size of the base page to be aggregated; based on the determined number of bits, it can select the page offset within the virtual address. For example, the MMU can select the lowest number of bits in the virtual address as the page offset. The base page can be a small page. For example, the size of a small page can be 4KB. The number of bits for the page offset is 12 bits. Alternatively, the base page can also be a large page larger than a small page. For example, the size of the base page can be 2MB, 1GB, 512GB, etc. Taking a base page size of 2MB as an example, the number of bits for the page offset is 21 bits. After determining the number of bits for the page offset, the MMU can determine multiple page table indexes based on the remaining bits of the virtual address and the number of levels in the multi-level page table structure.

[0076] For example, the virtual address can be 48 bits. The size of the base page to be aggregated is 2M. The number of levels in the multi-level page table structure is 4. Then the MMU can split the virtual address into VPN[3], VPN[2], VPN[1], VPN[0], and Page offset. By concatenating VPN[3], VPN[2], VPN[1], VPN[0], and Page offset in sequence, the virtual address can be obtained. The Page offset is 21 bits. VPN[3], VPN[2], VPN[1], and VPN[0] are all 9 bits.

[0077] In some embodiments, the MMU can perform multiple page table traversals in a multi-level page table structure based on multiple page table indexes. The number of page table traversals can be equal to the number of page table indexes. The MMU can perform traversals in a top-down manner. During each page table traversal, the MMU can obtain the page table index; it can obtain the physical base address; and based on the page table index and the physical base address, it can traverse the page table corresponding to the physical base address to obtain multiple Page Table Elements (PTEs).

[0078] Reference Figure 3 For hardware memory pages of different sizes, the MMU can initiate page table traversal at the corresponding level when performing address translation. For example, for a 1GB hardware big page, the MMU performs a second-level (L2) page table traversal; while for a 4KB basic page, it needs to perform a last-level (L0) page table traversal.

[0079] In some embodiments, the page table is traversed to obtain multiple page table entries, the multiple page table entries including a target page table entry and multiple adjacent page table entries.

[0080] In some embodiments, when performing page table traversal, the MMU can not only obtain the target page table entry corresponding to the target virtual address, but also read multiple adjacent page table entries stored consecutively, including the target page table entry, at once, based on the prefetch strategy and the principle of locality of memory access.

[0081] The target virtual address, serving as the starting point and core of page table traversal, is the specific memory address that the CPU instruction attempts to access. The MMU uses the virtual page number portion of this address to calculate the physical address of each page table entry, starting from the root page table, with the ultimate goal of finding a unique target page table entry to complete the address translation.

[0082] Reading multiple contiguous page table entries, including the target page table entry, in a single operation is a hardware optimization strategy based on the principle of locality of reference in memory access. Since operating systems typically store page table structures in contiguous physical page frames, page table entries adjacent to the virtual address of the target page table entry also have a high probability of maintaining contiguous physical addresses, creating favorable conditions for batch reading. Therefore, this mechanism can fully utilize the principle of spatial locality—that is, regions adjacent to accessed memory locations have a high probability of being accessed sequentially. By prefetching page table entries adjacent to the current target virtual address, the hardware can prepare for address translation in advance for subsequent possible contiguous address accesses, thereby avoiding triggering a complete page table traversal process again from the source. Furthermore, the prefetch strategy is a proactive optimization mechanism implemented by the hardware based on the principle of locality. When the MMU accesses the target page table entry, it uses a wide-bit memory bus to read a larger data block at once. This strategy has significant advantages: the latency of a single memory access depends primarily on the transfer setup time, rather than the data size, so batch transfers can reduce the average latency of a single access; at the same time, it provides a data foundation for hardware big page aggregation, enabling the MMU to evaluate the merging conditions of adjacent page table entries in real time; in addition, prefetched data is kept in the cache, providing an acceleration effect of unsolicited delivery for subsequent accesses.

[0083] In some embodiments, the target page table entry can be the target PTE uniquely specified by the index bit of the target virtual address during the current page table traversal step. It is the initial reason and direct target for the MMU to initiate memory access. Adjacent page table entries can be other page table entries stored contiguously with the target page table entry in the page table to which the target page table entry belongs. Specifically, when the MMU reads the target page table entry, it loads the entire cache line containing it at once, thereby automatically obtaining the target page table entry and multiple adjacent page table entries. This mechanism provides an immediately available data foundation for subsequent hardware big page aggregations that may occur.

[0084] In its implementation, the MMU calculates and retrieves page table entries using the following steps: For the highest-level page table traversal, the MMU reads the PPN field from the Supervisor Address Translation and Protection Register (SATP) and determines the base address of the root page table based on the read PPN field. The MMU can use the most significant bit of the virtual address as an index, combined with the determined base address, to calculate the physical address of the first page table entry to be searched. For non-highest-level page table traversals, the MMU can use the Physical Page Number (PPN) provided by the previous-level page table entry as the base address of the current-level page table, combined with a specific multi-bit index in the target virtual address, to obtain the physical address of the target page table entry through address concatenation.

[0085] In some embodiments, the number of multiple page table entries is determined based on the processor's bus width.

[0086] The MMU can determine the number of page table entries that can be retrieved in a single page table traversal based on the processor's system bus width; that is, this number can be directly determined by the ratio of the bus width to the size of a single page table entry. For example, when the system bus width is 256 bits (32 bytes) and each page table entry occupies 64 bits (8 bytes), a single memory access can retrieve four consecutive page table entries simultaneously. This hardware design allows the MMU to fully utilize the physical characteristics of the bus bandwidth when reading the target page table entry, prefetching a group of page table entries with physically adjacent addresses into the cache together. Through this mechanism, not only is the data retrieval efficiency of page table traversal significantly improved and the overall memory access latency reduced, but it also provides the necessary data foundation for subsequent hardware big page aggregation judgments, thereby effectively improving the overall performance of the address translation system.

[0087] S102: If the target page table entry is a leaf page table entry, obtain a valid leaf page table entry from the plurality of adjacent page table entries.

[0088] In some embodiments, a leaf page table entry, or PTE, can be the final page table entry that, during address translation in a multi-level page table structure, no longer points to the next-level page table but directly maps to a physical memory page. When the MMU traverses the page tables from higher to lower levels, the traversal process terminates immediately once a leaf page table entry is found at a certain level. Whether a page table entry is a leaf page table entry can be determined by checking its permission bit field, such as the XWR bit in the RISC-V architecture, which represents the execute, write, and read permission bits. If XWR == 3'b000, it is determined to be a non-leaf page table entry; this PTE is simply a pointer to the next-level page table. If XWR != 3'b000, it is determined to be a leaf page table entry. This PTE may contain the final physical page mapping and its access permissions.

[0089] Leaf page table entries can appear at different page table levels, which directly determines the size of the memory page they map to. (See reference...) Figure 3 As shown, terminating at Level 0 of the page table maps a small 4KB page. Terminating at Level 1 maps a large 2MB page. Terminating at Level 2 maps a large 1GB page. Terminating at Level 3 maps a massive 512GB page. This design provides great flexibility, allowing the operating system to choose the most suitable page size for different memory regions based on demand.

[0090] In some embodiments, when the page table entry obtained by the MMU in a certain level of the page table does not directly map physical memory pages but points to the base address of the next level page table, the processing of this PTE and subsequent operations involve traversing the non-leaf page table. Specifically, the MMU can resolve the physical page number (PPN) in the PTE to the starting physical address of the next level page table, and combine it with the index corresponding to the next level in the virtual address to calculate the precise physical address of the next level target PTE, thereby initiating a new memory access and iteratively executing the next level page table traversal process.

[0091] In some embodiments, when the PTE obtained by the MMU in a certain level of the page table directly defines the final mapping from the virtual address to the physical memory page, the processing of this PTE involves traversing the leaf page table. This process marks the completion of address translation. Specifically, the MMU recognizes this PTE as a leaf PTE, immediately terminates the page table traversal process, and uses the PPN in this PTE as the page number of the target physical page. Then, it directly concatenates this PPN with the page offset in the original virtual address to generate the final physical address.

[0092] In some embodiments, if the target page table entry is not a leaf page table entry, a valid leaf page table entry with a valid status bit field of 1 is obtained from multiple adjacent page table entries.

[0093] In some embodiments, the valid status bit field can be a flag field in a page table entry that indicates whether it is in an available state. When the field is 1, it indicates that the mapping contained in this page table entry is currently valid and can be used by the hardware; when it is 0, it indicates that the mapping is invalid, such as the corresponding physical page not being allocated or having been swapped out of memory, and any access attempt will trigger a page fault exception.

[0094] If the target page table entry is a leaf page table entry, the MMU can further filter from multiple pre-fetched adjacent page table entries to select all candidate page table entries with a valid state bit field of 1. These page table entries that pass the filter are valid leaf page table entries and will be included in the subsequent aggregation judgment process. Specifically, the MMU checks the valid state bit fields of each adjacent page table entry in parallel, retaining only those entries that both meet the validity conditions and have the characteristics of a leaf page table entry, thereby ensuring that the set of page table entries participating in the aggregation operation meets the requirements in terms of basic state and mapping type.

[0095] S103: Aggregate the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry; wherein, the comparison fields are the fields in the page table entry that affect the execution of memory access instructions.

[0096] In some embodiments, the comparison field is a field in the page table entry that affects the execution of memory access instructions.

[0097] In some embodiments, the comparison field may consist of multiple key fields in the page table entry that directly control the execution behavior of specific types of memory access instructions. Specifically, these fields define the basic permission conditions that the processor must meet when executing different categories of memory access instructions, and their values ​​directly determine whether the corresponding memory access operation can be executed successfully without triggering permission exceptions.

[0098] In some embodiments, the comparison fields may include at least an address space identifier field, a memory type field, a hardware address high-order bits field, and a status identifier field. The address space identifier field, such as user mode bits (U) and global bits (G), determines the effective scope and access privilege level of the mapping; the memory type field, such as page base memory type (PBMT), controls the caching strategy and memory order of access; the hardware address high-order bits field ensures the physical continuity of the mapping; and the status identifier field, such as a valid bit (V), ensures that the page table entries participating in the comparison are in an available state.

[0099] During hardware bigpage aggregation, all page table entries participating in the aggregation must maintain complete consistency in these comparison fields. This consistency ensures that the aggregated hardware bigpage has uniform memory access control characteristics. If page table entries participating in the aggregation have inconsistencies in the comparison fields, it will result in the corresponding hardware bigpages having different access permission characteristics. This difference in permission characteristics will violate the premise of memory access consistency, causing discontinuities in access control within what should be a unified address space region. For example, some pages may allow user-mode access while others are prohibited; such permission splitting will seriously affect the security and functional correctness of the system.

[0100] Therefore, consistency checks of comparison fields are a prerequisite for hardware big page aggregation. They ensure that the aggregated address space remains intact and consistent in terms of access permissions, memory attributes, and protection mechanisms, providing reliable security and a consistent execution environment for subsequent memory access operations.

[0101] By precisely defining fields that affect specific memory access instructions as comparison benchmarks, this design ensures that the aggregated bigpage mapping does not alter the underlying access semantics of the original pages. This guarantees that aggregation operations do not affect the execution results of any memory access instructions under individual page mappings. By selectively including some permission fields in the comparison scope, it avoids both overly strict comparison conditions that reduce aggregation opportunities and overly lenient aggregation strategies that lead to functional errors, achieving an optimal balance between security and performance improvement. The system can flexibly configure the composition of comparison fields according to the needs of different application scenarios. For environments requiring strict isolation, more permission fields can be included; for performance-priority scenarios, comparison fields can be appropriately simplified, thus providing differentiated aggregation strategies for memory regions with different security levels. This method of defining comparison fields based on instruction type influence essentially establishes a secure and efficient aggregation admission mechanism, enabling the system to enjoy the performance benefits of bigpage aggregation while maintaining strict memory access control rules.

[0102] In some embodiments, the page table entry fields further include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field.

[0103] Independent state fields can be a set of fields that do not participate in consistency comparisons during page table entry aggregation and whose values ​​do not have a decisive impact on the core execution logic of memory access instructions. This set of fields can include at least the write permission bit (W) and the dirty bit (D). From the perspective of memory access instructions, for LOAD type operations, these two fields do not constitute any execution constraints; while for STORE type instructions, although the write permission bit (W) needs to be verified in the final execution stage and the dirty bit (D) needs to be updated when data is written, in most application scenarios, the state of these fields also does not constitute any execution constraints for STORE type instructions. Therefore, the state of these fields should not be a prerequisite for hindering initial address translation and mapping aggregation.

[0104] Based on the above characteristics, independent state fields are essentially a set of fields with a low probability of affecting the execution result of memory access instructions. Therefore, during the decision-making phase of hardware big page aggregation, the specific values ​​of these fields can be excluded from the consistency comparison conditions, and instead, they can be stored completely in the aggregation entry of the TLB, with precise permission verification performed during actual execution. This separation architecture creates significant technical advantages: on the one hand, by relaxing the aggregation conditions, it greatly improves the space utilization of TLB entries, allowing more contiguous page table entries to be merged into a single big page mapping; on the other hand, through subsequent independent verification mechanisms, it ensures that the write permissions and dirty states of each subpage can be accurately checked, perfectly balancing the dual requirements of system performance and security. Especially in complex memory management scenarios such as copy-on-write, this design can bring significant performance improvements to the system without sacrificing functional correctness.

[0105] The low-order bits of the hardware address do not need to be directly compared in terms of field content. Instead, they can be used to verify whether multiple physical page frames constitute a contiguous address space. Specifically, if the comparison fields of the target page table entry and the valid leaf page table entry are completely identical, it means that the high-order bits of the hardware address of the target page table entry and the valid leaf page table entry are completely identical. In this case, the low-order bits of the hardware address can be used to determine whether the physical addresses of the multiple large hardware pages corresponding to the target page table entry and the valid leaf page table entry are contiguous.

[0106] In some embodiments, the low-order bits of the hardware address are determined based on the processor's bus width.

[0107] The bit width of the low-order field of the hardware address can be dynamically determined based on the processor's system bus bit width. Specifically, the number of bits in this field is determined by the correspondence between bus transfer capability and the size of a single page table entry, representing the address identifier requirement corresponding to the number of consecutive page table entries that can be retrieved in parallel during a single memory access.

[0108] When the system bus width is 256 bits (32 bytes) and each page table entry occupies 64 bits (8 bytes), a single memory access can simultaneously retrieve 4 consecutive page table entries. In this case, the low-order bits of the hardware address must contain the lowest 2 bit fields (such as PPN[1][1:0]), which are sufficient to uniquely identify the relative positions of the 4 consecutive page table entries in the physical address space.

[0109] When the system bus width is increased to 512 bits (64 bytes), a single memory access can simultaneously retrieve 8 consecutive page table entries. Accordingly, the low-order fields of the hardware address need to be extended to the lowest 3 bits (such as PPN[1][2:0]), through which the physical address distribution characteristics of the 8 consecutive page table entries can be fully described.

[0110] This dynamic matching mechanism ensures that the hardware can make full use of bus bandwidth resources, while providing an accurate address information basis for subsequent page table entry continuity verification and hardware big page aggregation.

[0111] In some embodiments, if the target page table entry and the valid leaf page table entry satisfy the full aggregation condition, the independent state fields in the target page table entry and the valid leaf page table entry are cached in the translation back buffer; wherein, the full aggregation condition includes: the number of valid leaf page table entries is equal to the number of adjacent page table entries, and each valid leaf page table entry is consistent with the target page table entry in the comparison field, and the low-order bits of the hardware address in the target page table entry and the valid leaf page table entry are consecutive.

[0112] Including a dirty (D) and write (W) field in the independent status field, that is, ignoring the dirty (D) and write (W) fields in the comparison of comparison fields, can accurately distinguish between the real-time requirements of access permission checks and the consistency requirements of mapping relationships, thereby significantly improving the success rate of hardware big page aggregation and the overall hit rate of TLB. Specifically, the D and W bits are dynamic status bits, and their values ​​may change at any time due to the program's access behavior. The D bit records whether the page has been written, and the W bit controls whether writing is allowed. However, the read (Load) instruction does not logically care about these two bits, because Load only needs read permission, does not trigger write operations, and does not care whether the page is dirty. Similarly, for the write (Store) instruction, in most access scenarios, especially for pages that have write permission and are in a clean state, its execution flow is also not directly affected by the D and W bits. Therefore, if the aggregation conditions require that the D and W bits of all candidate page table entries must be exactly the same, it will unnecessarily exclude a large number of PTEs that are completely consistent in other aspects but differ in D / W bits only due to different access histories. By ignoring these two bits, aggregation is determined solely by stable permission bits and physical address contiguity, which determine mapping relationships. This significantly relaxes the aggregation criteria, directly improving the aggregation success rate. Secondly, program memory accesses typically exhibit strong spatial locality. That is, the processor is likely to access a series of adjacent virtual pages within a short period. Although these adjacent pages are mapped to consecutive physical page frames, their modification history (D) and write permissions (W) may not be entirely identical (e.g., some pages are read-only code segments, while others are writable data segments). If aggregation is prohibited simply because of differences in the W bit, these contiguous pages, which could have been mapped as a single large memory block, would require multiple TLB entries. By ignoring the D and W bits during aggregation, the hardware can merge more spatially contiguous pages with slightly different permission states into a larger TLB entry. This allows a single TLB entry to cover a larger virtual address range, directly reducing the frequency of TLB misses and thus improving the TLB hit rate. Furthermore, improving the aggregation rate does not come at the expense of correctness. Although the D / W bits are not compared during aggregation, the hardware independently caches the D and W bits of each subpage in the aggregated TLB entry. When a write (Store) instruction is executed, the TLB checks the individual W bit of the target subpage after hitting the aggregation entry. If W=0, a Page Fault is triggered, strictly preventing illegal writes. Similarly, if a Store operation hits a subpage with D=0, the hardware can be configured to trigger a processing flow to update the D bit of the PTE in memory. This design separates aggregation judgment from permission checks; that is, aggregation aims to maximize merging to improve coverage, while checks provide precise permission and state control down to each subpage. Thus, performance is maximized without compromising security.

[0113] The independent state field includes at least a dirty (D) field and a write (W) field, meaning the comparison field can exclude the dirty (D) and write (W) fields. Based on this setting, if the target page table entry and the valid leaf page table entry satisfy the full aggregation condition, the write (W) field and the dirty (D) field in the aforementioned candidate page table entry and the target page table entry are cached in the TLB. The full aggregation condition may include: the number of candidate page table entries equals the total number of pre-acquired adjacent page table entries; each candidate page table entry and the target page table entry are consistent in the comparison field; and the low-order bits of the hardware address contained in the target page table entry and the valid leaf page table entry are arranged consecutively, i.e., the physical addresses are contiguous.

[0114] By ignoring the comparison of the D and W fields, hardware is essentially allowed to aggregate based on more stable and fundamental mapping attributes, namely physical continuity and basic permissions, avoiding invalid exclusions caused by transient state bit differences. This significantly increases the number of aggregateable PTE combinations, enabling the TLB to cache a larger address space range. Furthermore, by caching the write and dirty fields independently, large-page aggregation can be implemented to improve TLB space utilization while ensuring accurate permission and status checks for subsequent storage accesses, guaranteeing system access security and consistency.

[0115] In some embodiments, if the target page table entry and the valid leaf page table entry satisfy a partial aggregation condition, then the independent status field and the low-order hardware address field in the target page table entry and the valid leaf page table entry are cached in the translation backup buffer; wherein, the partial aggregation condition includes: the number of valid leaf page table entries is greater than zero and less than the number of adjacent page table entries, and each valid leaf page table entry is consistent with the target page table entry in the comparison field.

[0116] The comparison field can exclude low-order bits of the hardware address. Based on this, if the target page table entry and the valid leaf page table entry satisfy partial aggregation conditions, the write field (W) and dirty field (D) of the candidate page table entry and the target page table entry are independently cached in the TLB. The partial aggregation conditions include: the number of candidate page table entries is greater than zero and less than the total number of pre-acquired adjacent page table entries, and each candidate page table entry and the target page table entry are consistent in the comparison field. By retaining and caching the independent control and status fields and low-order address information of each page table entry, partial contiguous hardware big page aggregation can be achieved while ensuring access control, status consistency, and correct address mapping, thereby improving TLB utilization efficiency and overall system performance.

[0117] Compared to full aggregation, partial aggregation requires explicitly recording the low-order bits of the hardware address in the TLB, primarily due to the relaxed physical address continuity requirement and the resulting address mapping uncertainty. Specifically, full aggregation requires that the low-order bits of the physical page numbers of all candidate page table entries and target page table entries be strictly consecutive. This perfect continuity allows the hardware to implicitly deduce the actual physical page number of each subpage by storing a base address and combining it with the index bits in the access address. Therefore, the TLB entry does not need to store the low-order bits of each subpage's address. However, partial aggregation only requires that some PTEs meet the condition, and the low-order bits of the physical page numbers of these PTEs may no longer be consecutive. This discontinuity makes it impossible to deduce the physical addresses of all subpages using a common base address plus a simple offset. Secondly, because the physical addresses of subpages in partial aggregation may be non-consecutive, the TLB must record the complete physical page number information for each aggregated subpage individually. The low-order bits of the hardware address are a crucial component of the physical page number. If these low-order bits are not explicitly stored, the TLB will be unable to determine the exact physical address of each subpage during translation, leading to address translation errors. Explicitly caching these low-order fields ensures that the mapping relationship of each subpage remains accurate and independent, even in cases of non-contiguous addresses. Therefore, partial aggregation sacrifices some TLB storage space—that is, by using additional storage for non-contiguous address low-order fields—in exchange for the flexibility to perform aggregation even in scenarios with non-contiguous physical addresses. This improves the success rate of hardware bigpage aggregation and TLB hit rate in a wider range of real-world scenarios, achieving an effective balance between performance and resource overhead.

[0118] In some embodiments, if the target page table entry and the valid leaf page table entry satisfy a partial aggregation condition, then the valid fields in the target page table entry and the valid leaf page table entry are cached in the translation fallback buffer.

[0119] In a virtual memory system, if a virtual address is hit in the Translation Lookaside Buffer (TLB), but its corresponding page table entry is actually invalid (i.e., PTE V=0), the hardware must trigger a page fault exception instead of returning an incorrect physical address. This mechanism is the core guarantee of the memory protection system.

[0120] In some aggregation scenarios, if the system aggregates PTE0 and PTE1 (both with V=1), while PTE2 is not included in the aggregation because V=0, and instead of independently recording the V bit of each subpage in the aggregation item, the entire aggregation item is simply marked as V=1, then an incorrect TLB hit will occur when accessing the virtual address corresponding to PTE2. In this case, the hardware will misjudge the address as valid and perform memory access based on the incorrect mapping, ultimately leading to serious consequences such as data corruption and compromised system stability.

[0121] Therefore, in some aggregation scenarios, it is crucial to store the V bit independently for each subpage. This design ensures that the actual validity of the target subpage can be accurately verified after a TLB hit: when the V bit of the requested subpage is 0, the hardware will ignore the TLB hit and trigger a page fault, which will then be handled by the operating system. This mechanism effectively blocks the propagation path of error address translation.

[0122] Furthermore, page table entry validity is dynamically changing. The operating system may implement memory management operations such as page swapping by setting the V bit of the PTE to 0. In full aggregation mode, the failure of any subpage will cause the entire aggregation entry to be evicted; however, in partial aggregation architecture, since the state of each subpage is managed independently, the failure of a single subpage (V: 1→0) will not affect the TLB cache state of other valid subpages, nor will it destroy the overall validity of the aggregation entry. The hardware only needs to trigger a page fault when accessing the failed subpage, and the operating system can handle the exception accordingly, while retaining the remaining valid mappings within the aggregation entry to continue service. This fine-grained state management improves the system's fault tolerance and ensures the accuracy of memory management operations, providing an important guarantee for the continuous and stable operation of the system.

[0123] In some embodiments, if each valid leaf page table entry and the target page table entry have at least one inconsistency in the comparison fields, the hardware big page mapping corresponding to the target page table entry is cached in the translation backup buffer.

[0124] If each of the multiple valid page table entries is inconsistent with the target page table entry in the comparison fields, the overall aggregation operation is abandoned, and only the hardware big page mapping corresponding to the target page table entry is cached in the TLB. The comparison fields contain attributes that determine page access behavior (such as permission bits, global flags, etc.). If inconsistencies exist, it indicates that although these pages are physically adjacent, their access rules or states differ. Forced aggregation may lead to privilege escalation or confusion, resulting in unauthorized access or data inconsistency. Abandoning aggregation strictly adheres to the principle of least privilege, ensuring that each mapping is independent and secure. Even if aggregation is not possible, caching the target page table entry separately can still accelerate subsequent accesses to that address, avoiding complete reliance on slow page table traversal. At the same time, this strategy avoids the storage overhead of recording additional information required for partial aggregation, which is more conducive to the efficient use of limited TLB resources. By discarding some aggregations with high uncertainty, a balance can be achieved between hardware implementation complexity, timing performance, and resource utilization.

[0125] S104: Store the aggregated large page to the translation back buffer.

[0126] In some embodiments, the TLB is a small, high-speed cache integrated within the CPU chip's memory management unit. Its sole purpose is to cache the results of recently used virtual-to-physical address translations. Since page tables are stored in slower memory, looking up the page table for each translation is very slow; the TLB exists to address this performance bottleneck.

[0127] The content in the TLB is derived from the PTE. When a TLB miss occurs, the MMU finds the correct PTE by traversing the page table, then extracts the key information (virtual page number, physical page number, permission bits) from it, and creates an entry to cache in the TLB.

[0128] TLB and PTE work together to complete address translation. Specifically, TLB handles common cases, i.e., fast paths. The MMU first queries the TLB; if a hit occurs, the translation is completed within 1-2 cycles. PTE handles exceptional cases, i.e., slow paths. When the TLB misses, the PTE acts as a backup data source, providing the translation result through page table traversal. A TLB entry is a subset or simplified version of the PTE content. The TLB only caches the most critical information needed for address translation and does not cache all memory bits used for management in the PTE.

[0129] In some embodiments, multiple hardware big page maps corresponding to target page table entries and valid leaf page table entries can be aggregated into a single hardware big page map; the aggregated hardware big page map is then stored in a translation back buffer.

[0130] The MMU can aggregate multiple independent hardware big page mappings corresponding to these page table entries into a larger logical mapping unit and store this aggregated mapping relationship in a single TLB entry. By compressing multiple independent hardware big page mappings into a single TLB entry, structural optimization of TLB storage resources can be achieved. A single entry can cover an address space several times larger than the original size, effectively increasing the actual capacity of the TLB several times. This enables the system to more efficiently support application scenarios requiring large-scale address space mapping, effectively alleviating performance bottlenecks caused by TLB capacity limitations. The aggregated single TLB entry can meet the translation needs of contiguous large blocks of address space, significantly reducing the frequency of TLB misses. This directly reduces the number of time-consuming page table traversal operations, shortens the average address translation latency, and provides a more continuous and efficient data supply to the processor core. In addition, this mechanism fully utilizes the spatial locality of program access, organizing multiple pages that may be accessed consecutively into a unified address unit in the TLB. This not only improves the TLB hit probability but also creates a synergistic effect with the processor's prefetch mechanism, making the memory access pattern more compatible with the hardware cache structure.

[0131] In some embodiments, the aforementioned independent status field may further include a read field and / or an execute field. Based on this, step S102 may further include: caching the read field and / or execute field from the target page table entry and the valid leaf page table entry to the translation back buffer.

[0132] The MMU handles address translation requests from both the Load Memory Unit (LSU) and the Instruction Fetch Unit (IFU). However, in most application scenarios, execution permissions (X) do not constrain LSU memory access operations (except for special hlvx instructions that require X permission checks), and read / write permissions (R / W) do not affect IFU instruction fetch operations. Based on this characteristic, the XWR permission bit can be excluded from the comparison fields that must be consistent during page table entry aggregation, thereby significantly improving the success rate of hardware big page aggregation.

[0133] In this design, the XWR permission bits in all page table entries (PTEs) participating in the aggregation are fully cached in the aggregation entry of the Translation Lookaside Buffer (TLB), and the hardware performs precise permission verification based on the specific source of the access request. When the request originates from the IFU, the MMU only needs to check the X permission bit; when the request originates from the LSU, it selects to check either the R or W permission bit based on the operation type. This on-demand verification mechanism ensures that different functional units receive correct permission protection and significantly improves the space utilization of the TLB by relaxing the aggregation conditions.

[0134] Based on this, the independent status field can also include a read field and / or an execute field, meaning the comparison field can further exclude the read field (R) and / or the execute field (X). With this configuration, the read and / or execute fields from multiple candidate page table entries and the target page table entry can be cached in the TLB during the full or partial aggregation process described above. By ignoring the consistency requirements of read and / or execute permissions during the aggregation decision process, mergeable page table entries can be identified on a larger scale. Simultaneously, by independently recording the read and execute permission bits of each page table entry in the aggregated TLB entry, the MMU can perform fast permission verification in parallel during address translation, significantly improving the success rate of large page aggregation and the space utilization of the TLB, while also ensuring that Load and Store instructions receive secure and correct access control according to the original page table permissions.

[0135] Storing the dirty bit (D), write permission bit (W), execute permission bit (X), and read permission bit (R) of all page table entries in the TLB inevitably requires more hardware storage resources and may impose additional load on critical timing paths, thus impacting overall performance and area efficiency. Therefore, in actual hardware implementation, a more flexible trade-off strategy can be adopted based on design goals and performance trade-offs. In some embodiments, only some critical permission fields can be compared during the aggregation judgment phase (e.g., only comparing the X and R bits), while still storing all or part of the D, W, X, and R attributes in the TLB entry; in some embodiments, the comparison and storage strategy can also be dynamically selected based on the access mode, such as enabling a stricter W bit comparison for a subset of pages that may be written. Such solutions can effectively alleviate resource overhead and access timing pressure while maintaining system security and functional correctness, achieving a reasonable balance between aggregation benefits and hardware costs.

[0136] In some embodiments, the memory access instructions in step S103 above include at least read instructions and write instructions.

[0137] Memory access instructions include at least two basic types: read instructions (Load) and write instructions (Store). For read instructions, execution only requires verification of the read permission bit (R) and execute permission bit (X), while the states of the write permission bit (W) and dirty bit (D) do not impose any constraints on the completion of the operation. For write instructions, in most access scenarios, especially for pages that already have write permissions and are in a clean state, their execution flow is also not directly affected by the write permission bit and dirty bit, allowing them to fully utilize the acceleration provided by aggregation mapping.

[0138] By clearly distinguishing the degree of dependence of different instruction types on permission fields, the admission criteria for aggregation judgment are significantly relaxed. Especially for read instructions and regular write instructions, ignoring the consistency requirements of the W and D bits significantly increases the number of aggregateable page table entries, enabling the TLB to cache a larger range of contiguous address space and directly improving TLB hit rate. This design achieves intelligent adjustment of permission verification granularity: while ensuring absolute security for read instructions, complex permission checks are limited to necessary risk scenarios. This on-demand verification mechanism avoids overly conservative aggregation strategies while ensuring the integrity of critical security boundaries, achieving the best balance between performance optimization and system protection. Furthermore, by reducing unnecessary field comparison operations, the circuit complexity and timing latency of the aggregation judgment logic are reduced. Simultaneously, by concentrating limited hardware resources on the critical paths that truly affect instruction execution, precise allocation of computational overhead is achieved, improving overall energy efficiency.

[0139] In some embodiments, step S102 may further include: if the target page table entry is not a leaf page table entry, continuing to traverse the next level page table according to the next level page table indicated by the target page table entry.

[0140] If the target page table entry is a non-leaf page table entry, the physical base address of the next-level page table is obtained based on the physical page number field it contains. This, combined with the index bit of the corresponding level in the virtual address, is used to calculate the physical address of the next-level target page table entry, and then the next-level page table traversal process continues. Modern processor virtual memory systems commonly use multi-level page table structures to efficiently manage vast address spaces. Non-leaf page table entries do not directly map to physical pages but act as pointers to the next-level page table. Continuing to traverse the next level is a necessary step in resolving this tree structure until the leaf page table entry containing the actual physical page number is finally located, thus completing the virtual address to physical address translation. Multi-level page tables allow the operating system to avoid allocating intermediate page tables when large unmapped regions exist in the address space, saving physical memory.

[0141] The following is a specific embodiment of this specification:

[0142] Reference Figure 2 As shown, in the RV SV48 paging mode, the bit field description of each PTE corresponding to the 2M hardware big page is represented as: {N|PBMT|Reserved|PPN[3]|PPN[2]|PPN[1][8:2]|PPN[1][1:0]|PPN[0]|RSW|D|A|U|G|X|W|R|V}, where each field has a specific function and position.

[0143] N (No-execute) can be used to represent NAPOT mode. When it is 1, it indicates that the current PTE is a large page aggregated by software. That is, the current PTE represents a continuous virtual address to physical address mapping region, and the attribute values ​​of bits 5 to 0 of all page table entries in this region are exactly the same. Such address regions satisfy the natural alignment power of 2 (NAPOT) granularity requirement, and their size is larger than the base page size.

[0144] PBMT (Page-Based Memory Types) can control the memory type of a page, such as caching strategy (Cacheable, Non-cacheable) and memory order (Strong Order, Weak Order).

[0145] Reserved is a reserved bit and must be set to 0, otherwise an exception may occur.

[0146] PPN[3] is the third part of the Physical Page Number, corresponding to the physical page frame number of the Level 3 page table. When PTE is a non-leaf node, it points to the base address of the next level page table; when it is a leaf node, it is the high-order bit of the physical page number.

[0147] PPN[2] is the second part of the physical page number, corresponding to the physical page frame number of the Level 2 page table.

[0148] The PPN[1][8:2] position is bits 18-10, which are the high 7 bits of the first part of the physical page number, corresponding to the physical page frame number of the Level 1 page table.

[0149] PPN[1][1:0] is the lower 2 bits of the first part of the physical page number, which is the key field for 2MB big page aggregation: when the hardware reads 4 consecutive PTEs at once, it checks whether the PPN[1][1:0] of these PTEs are consecutive (the values ​​are 00, 01, 10, and 11 respectively) to determine whether full aggregation can be performed.

[0150] PPN[0] is the 0th part of the physical page number, corresponding to the physical page frame number of the Level 0 page table.

[0151] RSW (Reserved for Software) bits are reserved for the operating system. Hardware ignores these bits, and the operating system can use them to store custom information, such as page type or protection flags.

[0152] D (Dirty) is the dirty bit, which is automatically set by the hardware when a page is written.

[0153] A (Accessed) is the access bit, which is automatically set by the hardware when the page is read or written.

[0154] U (User) is the user mode bit. If set to 1, the user mode (U-mode) can access the page; otherwise, only the supervisor mode (S-mode) can access it.

[0155] G(Global) is the global bit. If set to 1, the mapping is global and the TLB will not refresh this entry during context switching.

[0156] X (Execute) is the executable bit. If set to 1, instructions can be executed from this page.

[0157] W (Write) is the writable bit. If set to 1, writing to this page is allowed.

[0158] R (Read) is the readable bit. If set to 1, data can be read from this page.

[0159] V(Valid) is the valid bit. If it is set to 1, the PTE is valid; otherwise, the access will trigger a page error.

[0160] Depending on the bus width, the number of PTEs retrieved from the cache or memory during each table walk varies. Taking a bus width of 256 as an example, each table walk retrieves 4 PTEs from the cache. These 4 PTEs must correspond to 4 consecutive virtual addresses. When a level 1 table walk returns, the MMU checks whether the XWR of the 4 PTEs is 0 to determine if the current return is a leaf PTE return. There are four possible scenarios:

[0161] 1. If the address pointed to by the current table walk request is a table PTE, then the other three PTEs are not checked to see if they are leaf PTEs. Large page aggregation is not performed in this case.

[0162] 2. If the PTE pointed to by the address PA[4:3] in the current table walk request is a leaf PTE, and the other three PTEs are also valid leaf PTEs, then according to... Figure 2 The comparison fields shown in bold are used for consistency comparison. The specific comparison fields include N, PBMT, Reserved, PPN[3], PPN[2], PPN[1][8:2], PPN[0], RSW, A, U, G, X, R, V, etc. If the comparison fields are completely consistent and PPN[1][1:0] is aligned and continuous, full aggregation can be performed. At this time, it is not necessary to record the PPN[1][1:0] of the four PTEs, but it is necessary to record the D and W attributes of the four PTEs. At this time, the V field of the four PTEs is 1.

[0163] 3. If the PTE pointed to by the address PA[4:3] in the current table walk request is a leaf PTE, and the other three PTEs are also valid leaf PTEs or partially valid leaf PTEs, then if some leaf PTEs match the leaf PTE pointed to by PA[4:3], then... Figure 2 The comparison fields shown in bold are used for consistency comparison. If the comparison fields are completely consistent, they can be partially aggregated in the TLB. The TLB records the PPN[1][1:0] of all aggregated leaf PTEs, as well as the D and W attributes and the valid signals of the corresponding PTEs.

[0164] 4. If the PTE pointed to by the address PA[4:3] of the current table walk request is a leaf PTE, and the other 3 PTEs are also valid leaf PTEs or partially valid leaf PTEs, then the other leaf PTEs are compared with the leaf PTE pointed to by PA[4:3] according to the comparison fields. If they are not completely the same, then aggregation is not performed.

[0165] As can be seen from the hardware big page aggregation method provided in the embodiments of this specification above, the embodiments of this specification can traverse the page table to obtain multiple page table entries, which include a target page table entry and multiple adjacent page table entries; if the target page table entry is a leaf page table entry, a valid leaf page table entry is obtained from the multiple adjacent page table entries; the target page table entry and the valid leaf page table entry are aggregated according to the comparison field in the target page table entry and the valid leaf page table entry; wherein, the comparison field is a field in the page table entry field that affects the execution of memory access instructions; the aggregated big page is stored in the translation lookup buffer. Compared with the existing methods, the embodiments of this specification significantly expand the range of hardware address space that a single TLB entry can cover by aggregating and storing the page table entries of multiple consecutive hardware big pages in the TLB, reducing the frequency of TLB failures, reducing the probability of triggering high-overhead page table traversal in subsequent accesses, thereby effectively shortening the average address translation latency and improving the overall execution efficiency of the processor. Meanwhile, by prefetching multiple consecutive page table entries in a single operation, the inherent spatial locality characteristic of program memory access behavior is effectively utilized. This pre-integrates the mapping of adjacent hardware megapages that may be accessed consecutively, making the TLB structure more aligned with actual memory access patterns and improving resource utilization efficiency. Furthermore, a conditional aggregation strategy is employed, where the comparison fields only include fields that affect memory access instructions. Aggregation is then performed only when the comparison field attributes are consistent, ensuring consistency of permissions and states and significantly improving the success rate of aggregation operations.

[0166] Based on the above-described hardware big page aggregation method, this specification also provides embodiments of a hardware big page aggregation apparatus. For example... Figure 4 As shown, the hardware large page aggregation device 400 may specifically include the following modules:

[0167] The traversal module 401 is used to traverse the page table to obtain multiple page table entries, including the target page table entry and multiple adjacent page table entries.

[0168] The first acquisition module 402 is used to acquire a valid leaf page table entry from the plurality of adjacent page table entries if the target page table entry is a leaf page table entry.

[0169] The aggregation module 403 is used to aggregate the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry; wherein, the comparison fields are the fields in the page table entry fields that affect the execution of memory access instructions.

[0170] Storage module 404 is used to store the aggregated large pages to the translation backup buffer.

[0171] In some embodiments, the page table entry fields further include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field.

[0172] Based on this, the aggregation module 403 described above can be specifically used for:

[0173] If the target page table entry and the valid leaf page table entry satisfy the full aggregation condition, the independent state fields in the target page table entry and the valid leaf page table entry are cached in the translation back buffer;

[0174] The full aggregation conditions include: the number of valid leaf page entries is equal to the number of adjacent page entries, each valid leaf page entry is consistent with the target page entry in the comparison field, and the low-order bits of the hardware address in the target page entry and the valid leaf page entries are consecutive.

[0175] In some embodiments, the page table entry fields further include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field.

[0176] Based on this, the aggregation module 403 mentioned above can also be used for:

[0177] If the target page table entry and the valid leaf page table entry satisfy the partial aggregation condition, then the independent status field and the low-order hardware address field in the target page table entry and the valid leaf page table entry are cached in the translation backup buffer;

[0178] The aggregation conditions include: the number of valid leaf page entries is greater than zero and less than the number of adjacent page entries, and each valid leaf page entry is consistent with the target page entry in the comparison field.

[0179] In some embodiments, the aforementioned independent status fields do not include read fields and / or execution fields.

[0180] In some embodiments, the aggregation module 403 described above can also be used for:

[0181] If each valid leaf page table entry and the target page table entry have at least one inconsistency in the comparison fields, the hardware big page mapping corresponding to the target page table entry is cached in the translation back buffer.

[0182] In some embodiments, the storage module 404 described above can be specifically used for:

[0183] Aggregate multiple hardware big page mappings corresponding to the target page table entry and the valid leaf page table entry into a single hardware big page mapping;

[0184] Store the aggregated hardware big page map to the translation back buffer.

[0185] In some embodiments, the memory access instructions described above include at least read instructions and write instructions.

[0186] In some embodiments, the above-described hardware large page aggregation device 400 can specifically be used for:

[0187] If the target page table entry is not a leaf page table entry, the next level page table traversal continues according to the next level page table indicated by the target page table entry.

[0188] As can be seen from the hardware big page aggregation device provided in the embodiments of this specification above, the embodiments of this specification can traverse the page table to obtain multiple page table entries, which include a target page table entry and multiple adjacent page table entries; if the target page table entry is a leaf page table entry, a valid leaf page table entry is obtained from the multiple adjacent page table entries; the target page table entry and the valid leaf page table entry are aggregated according to the comparison field in the target page table entry and the valid leaf page table entry; wherein, the comparison field is a field in the page table entry field that affects the execution of memory access instructions; the aggregated big page is stored in the translation lookup buffer. Compared with the existing methods, the embodiments of this specification significantly expand the range of hardware address space that a single TLB entry can cover by aggregating and storing the page table entries of multiple consecutive hardware big pages in the TLB, reducing the frequency of TLB failures, reducing the probability of triggering high-overhead page table traversal in subsequent accesses, thereby effectively shortening the average address translation latency and improving the overall execution efficiency of the processor. Meanwhile, by prefetching multiple consecutive page table entries in a single operation, the inherent spatial locality characteristic of program memory access behavior is effectively utilized. This pre-integrates the mapping of adjacent hardware megapages that may be accessed consecutively, making the TLB structure more aligned with actual memory access patterns and improving resource utilization efficiency. Furthermore, a conditional aggregation strategy is adopted, performing aggregation only when the comparison field attributes are consistent, ensuring the consistency of permissions and states. By excluding write fields and dirty fields from the comparison fields, the success rate of aggregation operations is significantly improved.

[0189] Corresponding to the above-described hardware big page aggregation method, this specification also provides an instruction processing method in its embodiments. Figure 5This is a flowchart of an instruction processing method provided in an embodiment of this specification. In specific implementation, it may include the following steps:

[0190] S501: Get memory access instructions.

[0191] In some embodiments, memory access instructions may be obtained, which may include at least write instructions and read instructions.

[0192] The MMU can receive and process memory access instructions from the processor's execution pipeline. Memory access instructions can include at least two basic types: write instructions and read instructions. Write instructions are responsible for writing data from the processor registers to the specified memory address space, while read instructions are used to read data from the memory address space into the processor registers.

[0193] S502: Retrieve the aggregated big page hit by the memory access instruction from the translation back buffer.

[0194] In some embodiments, the aggregated big page hit by the memory access instruction is retrieved from the translation back buffer.

[0195] When a memory access instruction requires a virtual address to physical address translation, the MMU can look up the corresponding address mapping in the translation lookup buffer. If the lookup matches a massive page mapping entry, it indicates that the virtual address is within a hardware-optimized, merged massive page address range. This massive page entry exists as a single entry in the TLB, but it actually covers the address space corresponding to multiple consecutive base pages.

[0196] During this process, the MMU can adopt different processing strategies based on the specific type of access instruction: for read instructions, address translation can be directly completed using aggregation mapping; for write instructions, the independent write permission bits and dirty bit status of the corresponding subpage in the aggregation entry can be further checked to ensure the legality of the access and the consistency of the data. This mechanism enables a single TLB entry to serve a wider range of address spaces while maintaining precise control over the independent permission status of each subpage.

[0197] S503: If the memory access instruction is a write instruction, perform page table traversal to obtain the leaf page table entry corresponding to the write instruction.

[0198] In some embodiments, if a write instruction hits a hardware big page corresponding to an aggregated hardware big page mapping that is at risk of being written to in the translation back buffer, a page table traversal is initiated to retrieve the leaf page table entry corresponding to the write instruction from memory or cache.

[0199] If a store instruction hits an aggregated hardware big page mapping in the translation back buffer that is at risk of being written to, the memory management unit will ignore the hit result and instead initiate a page table traversal operation to retrieve the original leaf page table entry corresponding to the store instruction from the memory or cache hierarchy.

[0200] In some embodiments, the hardware large page corresponding to the aggregated hardware large page mapping with write risk includes the hardware large page corresponding to the aggregated hardware large page mapping with a dirty field of 0, or the hardware large page corresponding to the aggregated hardware large page mapping with a write field of 0.

[0201] Aggregated hardware big page mappings with write risks include, but are not limited to, the following types: physical pages corresponding to aggregated hardware big page mappings with a dirty bit flagged as 0, or physical pages corresponding to aggregated hardware big page mappings with a write permission flagged as 0. These two cases represent different risk states: the former indicates that the target page may not be ready to accept writes (the dirty bit state is uncertain), while the latter indicates that it currently has no write permissions at all. By re-fetching page table entries, the potential problem of lagging state information in the aggregate cache is effectively avoided. For pages with a dirty bit of 0, it is ensured that the dirty bit state is correctly updated upon the first write; for pages with a write permission flag of 0, the final permission determination is made through authoritative page table entries, thus preventing illegal write operations from occurring. This design enjoys the performance advantages brought by big page aggregation while maintaining the precision of permission control. Even in big page aggregation mapping, the independent write permissions and dirty bit state of each subpage are still strictly respected, achieving a perfect balance between performance optimization and security control.

[0202] In some embodiments, a page table traversal is initiated to retrieve the leaf page table entry corresponding to the write instruction from memory or cache.

[0203] In its implementation, the process of initiating a page table traversal can include: querying the multi-level page table structure step by step based on the virtual address, ultimately locating the corresponding leaf page table entry, and loading it from main memory or cache into the temporary register of the memory management unit for subsequent permission verification and status update operations. This on-demand page table traversal mechanism avoids maintaining complex metadata information in the TLB to handle a few special cases. This lazy verification strategy ensures functional correctness while maximizing hardware storage savings and improving overall resource utilization efficiency.

[0204] In some embodiments, if a write instruction hits the aggregate page corresponding to an aggregate hardware big page mapping in the translation back buffer where the dirty field is 0, the hit is ignored.

[0205] If a write instruction hits an aggregated hardware big page mapping entry in the TLB where the dirty bit (D) is 0, the hardware will ignore the hit and instead initiate a page table traversal to retrieve the original leaf page table entry corresponding to the write instruction from memory or cache. After obtaining a valid PTE, the hardware will update its dirty bit to 1 to mark that the corresponding physical page has been written. The dirty bit indicates whether a page has been written and is a critical state for ensuring data consistency between memory and external storage. A dirty bit of 0 in the aggregated TLB entry only indicates that all subpages are in a clean state at the time of aggregation, but it does not represent the actual situation at the current moment. Ignoring the hit and re-acquiring the PTE ensures that the dirty bit is updated synchronously with the actual write operation, avoiding data synchronization errors caused by the lag in the aggregated cache state. The operating system relies on the dirty bit to determine whether a page needs to be written back to disk when swapped out. If the dirty bit in the TLB aggregated entry is not updated in time, dirty pages may be mistakenly judged as clean pages and discarded, resulting in data loss. By searching back for and updating the PTE dirty bit, a reliable state basis for memory management can be provided, ensuring the correctness of the storage system. In addition to updating the dirty bit, storage operations can also check the write permission bit (W bit). Although the W bit may be cached independently in the aggregate item, the re-initiated page table traversal can perform centralized and consistent native checks on permissions and state, avoiding security risks or state conflicts introduced by the scattered fields in the aggregate cache. Although repeated traversal increases the latency of a single storage operation, this ensures that the consistency of critical state is not sacrificed while significantly improving TLB coverage. In actual systems, the proportion of storage operations relative to load operations is relatively low, and the locality of access characteristic means that subsequent writes can benefit from TLB items with updated dirty bits, so the overall performance is still significantly better than the strategy of completely disabling aggregation. Overall, by falling back to the underlying page table traversal and update under certain conditions, the state consistency problem caused by TLB aggregation is properly solved, which helps to achieve a balance between efficient address translation and system reliability.

[0206] In some embodiments, a page fault occurs if a write instruction hits the aggregate page corresponding to an aggregated hardware big page mapping in the translation back buffer where the write field is 0.

[0207] If a write instruction hits the aggregated page corresponding to an aggregated hardware big page mapping where the write permission bit (W) is 0 in the TLB, the MMU can generate a page fault, thereby terminating the current storage operation and transferring control to the operating system's exception handler. A write permission bit (W) of 0 indicates that write operations are prohibited on that page under any circumstances, even if the page is cached in the TLB due to big page aggregation; its original permissions remain inviolable. Triggering a page fault can forcibly prevent illegal write operations, avoiding unauthorized data modification and thus ensuring system security and stability. A page fault can activate the operating system's exception handling process, allowing the operating system to intervene and adjudicate the illegal access. The operating system can adopt flexible response strategies based on the actual scenario, such as terminating the process initiating the illegal access, recording security audit events, or allocating a new physical page and resetting permissions in a copy-on-write scenario. Although the aggregation mechanism ignores the comparison of W bit consistency to improve performance, the hardware still strictly adheres to the original page table entry permissions in the final permission check. Generating a page fault is a necessary price to pay for maintaining this security and reliability; it ensures that hardware big page aggregation never comes at the cost of compromising memory protection. Overall, by resolutely triggering exceptions at the hardware level, the final decision-making power for write permissions is firmly placed under the operating system, thereby fully utilizing big page aggregation to improve performance while taking into account the system's security and reliability requirements.

[0208] In some embodiments, the operation data corresponding to the write instruction is written into the hardware big page mapped by the leaf table entry.

[0209] The MMU can directly write the operation data to the target storage location in the corresponding hardware big page based on the physical page frame address provided by the newly acquired leaf page table entry. This write operation is performed immediately after the physical address mapping is determined, ensuring that the data is accurately stored in the physical memory area directly mapped by the leaf page table entry. By performing the write operation based on the latest acquired leaf page table entry, the absolute accuracy of the physical address mapping is guaranteed. This mechanism effectively avoids erroneous writes caused by expired TLB cache or incomplete aggregate mapping information, ensuring the integrity and reliability of data storage at the hardware level.

[0210] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification can obtain memory access instructions; obtain the aggregated big page hit by the memory access instruction from the translation back buffer; if the memory access instruction is a write instruction, perform page table traversal to obtain the leaf page table entry corresponding to the write instruction. For read instructions, performance is improved by directly using aggregated big page mapping, while a strict verification process is enabled for write instructions. This approach benefits from the TLB coverage gain brought by aggregate mapping while ensuring the security of storage operations through permission checks down to the subpage level, achieving a balance between efficiency and reliability. Specifically, by strictly limiting the time-consuming page table traversal operation to necessary write instruction scenarios, the average system access latency is significantly reduced. This conditional rollback strategy minimizes performance overhead while ensuring functional integrity, significantly improving the collaboration efficiency between the processor core and the memory subsystem.

[0211] Based on the above instruction processing method, this specification also provides embodiments of an instruction processing apparatus. For example... Figure 6 As shown, the instruction processing device 600 may specifically include the following modules:

[0212] The first acquisition module 601 is used to acquire memory access instructions.

[0213] The second acquisition module 602 is used to acquire the aggregated big page hit by the memory access instruction from the translation back buffer.

[0214] The third acquisition module 603 is used to perform page table traversal to obtain the leaf page table entry corresponding to the write instruction if the memory access instruction is a write instruction.

[0215] In some embodiments, the third acquisition module 603 described above can be specifically used for:

[0216] If a write instruction hits a hardware big page corresponding to an aggregate big page mapping that is at risk of being written in the translation back buffer, a page table traversal is performed to retrieve the leaf page table entry corresponding to the write instruction from memory or cache.

[0217] The operation data corresponding to the write instruction is written into the hardware big page mapped by the leaf page table entry.

[0218] In some embodiments, the hardware large page corresponding to the above-mentioned aggregated hardware large page mapping with write risk includes the hardware large page corresponding to the aggregated hardware large page mapping with a dirty field of 0, or the hardware large page corresponding to the aggregated hardware large page mapping with a write field of 0.

[0219] Based on this, the third acquisition module 603 mentioned above can also be used for:

[0220] If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the dirty field is 0, the hit is ignored.

[0221] Based on this, the third acquisition module 603 mentioned above can also be used for:

[0222] If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the write field is 0, a page fault occurs.

[0223] This specification also provides a processor for executing the above-described hardware big page aggregation method and instruction processing method.

[0224] This specification also provides a chip, including the processor described above for executing the above-described hardware big page aggregation method and the above-described instruction processing method.

[0225] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0226] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0227] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0228] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0229] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0230] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational tasks to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The task is a function specified in one or more boxes.

[0231] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for aggregating hardware large pages, characterized in that, The method includes: The page table is traversed to obtain multiple page table entries, which include the target page table entry and multiple adjacent page table entries. If the target page table entry is a leaf page table entry, obtain a valid leaf page table entry from the plurality of adjacent page table entries; Aggregate the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry; wherein, the comparison fields are the fields in the page table entry that affect the execution of memory access instructions; Store the aggregated large pages to the translation back buffer.

2. The method according to claim 1, characterized in that, The page table entry fields also include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field; The aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes: If the target page table entry and the valid leaf page table entry satisfy the full aggregation condition, the independent state fields in the target page table entry and the valid leaf page table entry are cached in the translation back buffer; The full aggregation conditions include: the number of valid leaf page entries is equal to the number of adjacent page entries, each valid leaf page entry is consistent with the target page entry in the comparison field, and the low-order bits of the hardware address in the target page entry and the valid leaf page entries are consecutive.

3. The method according to claim 1, characterized in that, The page table entry fields also include an independent status field and a low-order hardware address field; the independent status field consists of multiple fields in the page table entry fields that do not affect the execution of memory access instructions; the independent status field includes at least a write field and a dirty field; The aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes: If the target page table entry and the valid leaf page table entry satisfy the partial aggregation condition, then the independent status field and the low-order hardware address field in the target page table entry and the valid leaf page table entry are cached in the translation backup buffer; The aggregation conditions include: the number of valid leaf page entries is greater than zero and less than the number of adjacent page entries, and each valid leaf page entry is consistent with the target page entry in the comparison field.

4. The method according to claim 2 or 3, characterized in that, The independent status fields do not yet include read fields and / or execution fields.

5. The method according to claim 1, characterized in that, The aggregation of the target page table entry and the valid leaf page table entry based on the comparison fields in the target page table entry and the valid leaf page table entry includes: If each valid leaf page table entry and the target page table entry have at least one inconsistency in the comparison fields, the hardware big page mapping corresponding to the target page table entry is cached in the translation back buffer.

6. The method according to claim 1, characterized in that, The step of storing the aggregated large pages to the translation backup buffer includes: Aggregate multiple hardware big page mappings corresponding to the target page table entry and the valid leaf page table entry into a single hardware big page mapping; Store the aggregated hardware big page map to the translation back buffer.

7. The method according to claim 1, characterized in that, The memory access instructions include at least read instructions and write instructions.

8. The method according to claim 1, characterized in that, The method further includes: If the target page table entry is not a leaf page table entry, the next level page table traversal continues according to the next level page table indicated by the target page table entry.

9. An instruction processing method, characterized in that, The method includes: Get memory access instructions; Retrieve the aggregated big page hit by the memory access instruction from the translation back buffer; If the memory access instruction is a write instruction, perform a page table traversal to obtain the leaf page table entry corresponding to the write instruction.

10. The method according to claim 9, characterized in that, If the memory access instruction is a write instruction, the process of performing a page table traversal to obtain the leaf page table entry corresponding to the write instruction includes: If a write instruction hits a hardware big page corresponding to an aggregate big page mapping that is at risk of being written in the translation back buffer, a page table traversal is performed to retrieve the leaf page table entry corresponding to the write instruction from memory or cache. The operation data corresponding to the write instruction is written into the hardware big page mapped by the leaf page table entry.

11. The method according to claim 10, characterized in that, The hardware large pages corresponding to the aggregated hardware large page mappings with write risks include hardware large pages corresponding to aggregated hardware large page mappings with a dirty field of 0, or hardware large pages corresponding to aggregated hardware large page mappings with a write field of 0.

12. The method according to claim 11, characterized in that, The method further includes: If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the dirty field is 0, the hit is ignored.

13. The method according to claim 10, characterized in that, The method further includes: If a write instruction hits the aggregate page corresponding to the aggregate hardware big page mapping in the translated backing buffer where the write field is 0, a page fault occurs.

14. A processor, characterized in that, The processor is used to execute the method according to any one of claims 1-13.

15. A chip, characterized in that, Includes the processor as described in claim 14.

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