Modularized synchronous triggering method and system with reconfigurable hardware logic engine

Abstract

The invention provides a modular synchronous triggering method and system with a reconfigurable hardware logic engine, which are applied to the field of data acquisition and equipment control, and the method comprises the following steps that: a management processor receives an event triggering logic to generate hardware configuration parameters, configures an event logic execution engine in a reconfigurable hardware executor, and executes the event logic execution engine in the reconfigurable hardware executor; the engine monitors the multi-mode input signals in real time in parallel, a result is generated through comparison and judgment on the hardware level, and multi-mode output signals are generated and sent when event trigger logic is met. According to the scheme, the synchronization precision and trigger flexibility of cooperative work of multiple devices can be improved, and compatibility and expansibility are improved.

Description

Technical Field

[0001] This invention relates to the field of data acquisition and equipment control technology, and in particular to a modular synchronous triggering method and system with a reconfigurable hardware logic engine. Background Technology

[0002] This invention relates to the field of data acquisition and equipment control technology, particularly in cutting-edge applications in clinical medical research, such as gait analysis, neurorehabilitation engineering, surgical navigation, and functional medical imaging. In these scenarios, it is often necessary to integrate various medical and research devices, such as motion capture systems, force tables, surface electromyography / electroencephalography (sEMG / EEG) acquisition devices, functional near-infrared spectroscopy (fNIRS) equipment, high-speed cameras, and ultrasound imaging equipment, to work collaboratively. These applications place extremely stringent demands on the precise time synchronization of multimodal data and the ability to respond in a coordinated manner to complex real-time physiological events.

[0003] However, existing technologies, while meeting the above requirements, suffer from the following insurmountable technical defects:

[0004] Poor synchronization accuracy and difficulties in data fusion: In traditional solutions, various devices typically operate independently, relying on their own internal clocks. Although software can perform time alignment of the data afterward, the drift of clocks across devices and the lack of a unified hardware triggering benchmark result in low alignment accuracy on the timeline, with errors typically ranging from tens to hundreds of milliseconds. For clinical research requiring precise capture of neuromuscular responses, transient brain activity, or rapid motor biomechanical events, such time errors can directly lead to data analysis errors, such as incorrect calculation of joint torques or misjudgment of the order of neural activation, thus severely impacting the validity and reliability of research conclusions.

[0005] Rigid triggering mechanisms are unable to respond to complex physiological events: Existing synchronous triggers or data acquisition cards are typically limited to manual buttons, fixed time intervals, or simple threshold triggering based on a single signal channel. However, in clinical research, critical events with diagnostic or evaluative significance are often complex conditions defined by multiple physiological and biomechanical parameters. For example, in a study of gait freeze in Parkinson's patients, intervention devices and imaging recordings might only be triggered at the instant when "the patient's gait frequency decreases by more than 20% and the integrated value of the tibialis anterior muscle electromyography signal is below the normal threshold." Current technology is completely unable to achieve such complex, user-customizable logical judgments and real-time event triggering based on multi-source heterogeneous biological signals.

[0006] Poor compatibility and scalability make clinical research deployment difficult: Clinical research involves diverse signal types from various devices, including analog voltage signals, TTL digital pulse signals, and software data packets transmitted via Ethernet / USB. Integrating these devices into a cohesive system often requires purchasing multiple signal adapters and data acquisition cards, and coordinating them through complex software programming. This not only makes setting up clinical research environments complex, costly, and unstable, but more seriously, when the research protocol needs to introduce new medical devices or sensors, the entire system often requires time-consuming and laborious redesign and verification, severely limiting the flexibility and iteration speed of clinical research.

[0007] Therefore, the field of clinical medical research urgently needs a brand-new technical solution that aims to provide a high-precision, highly flexible, and highly compatible multimodal data synchronization and equipment linkage control platform to fundamentally solve the above-mentioned technical problems.

[0008] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0009] In view of this, the present invention provides a modular synchronization triggering method and system with a reconfigurable hardware logic engine, which aims to solve the problems of poor synchronization accuracy, rigid triggering mechanism and poor compatibility and scalability when multiple devices work together in the prior art. By adopting a heterogeneous master-slave computing architecture and a reconfigurable hardware logic engine, it realizes real-time intelligent judgment and sub-microsecond-level synchronization triggering of multi-source heterogeneous signals.

[0010] This invention provides a modular synchronization triggering method with a reconfigurable hardware logic engine, comprising:

[0011] The management processor receives user-defined event triggering logic and generates hardware configuration parameters based on the event triggering logic.

[0012] The management processor sends hardware configuration parameters to the reconfigurable hardware executor to configure the event logic execution engine integrated within the reconfigurable hardware executor;

[0013] The configured event logic execution engine monitors in real time and in parallel one or more sources of multimodal input signals containing at least one of the following signal types through input / output units: digital pulse signals, analog data signals, audio and video data streams, software communication data packets, and user operation information.

[0014] At the hardware level, the event logic execution engine compares and judges multimodal input signals with event triggering logic, and generates comparison and judgment results.

[0015] When the comparison and judgment result meets the event triggering logic, the input / output unit generates and sends a multimodal output signal containing at least one of the following signal types to the external device: digital pulse signal, analog control signal, and software control command for controlling the external device.

[0016] In some alternative embodiments, the method is applied to the field of clinical medical research, and the external equipment includes at least one of a motion capture system, a force table, an electromyography / electroencephalography (EEG) acquisition device, and a medical imaging device.

[0017] In some optional embodiments, the event triggering logic includes level triggering logic, which is configured to trigger the generation or cessation of the multimodal output signal when the amplitude of the analog data signal in the multimodal input signal meets a preset threshold condition.

[0018] In some optional embodiments, the level-triggered logic further includes a time limit, which is configured to stop generating the multimodal output signal after the amplitude meets the threshold condition and continues for a preset time t.

[0019] In some optional embodiments, the event triggering logic includes edge triggering logic, which is configured to trigger the generation or cessation of the multimodal output signal when a rising or falling edge of a digital pulse signal in the multimodal input signal is detected.

[0020] In some optional embodiments, the event triggering logic includes instruction triggering logic, which is configured to trigger the generation of a multimodal output signal when a software communication data packet in a multimodal input signal is received and parsed, and it is confirmed that the packet contains a preset instruction code.

[0021] In some optional embodiments, the event triggering logic includes data triggering logic, which is configured to: perform real-time calculation on the data of the received multimodal input signal to obtain a trigger index, and trigger the generation of a multimodal output signal when the trigger index meets a preset condition.

[0022] In some optional embodiments, the event triggering logic is a hybrid triggering logic, which includes a combination of at least two of the triggering logics described above.

[0023] In some optional embodiments, the step of monitoring the multimodal input signals in real time and in parallel further includes:

[0024] The real-time data stream from the multimodal input signal is fed into a hardware-implemented neural network inference accelerator for real-time inference, in order to output an AI analysis result signal.

[0025] Among them, the event logic execution engine monitors and compares the AI ​​analysis result signal as part of the multimodal input signal.

[0026] In some optional embodiments, the steps of configuring the event logic execution engine include:

[0027] Use hardware configuration parameters to configure the parallel comparator array and programmable logic matrix inside the event logic execution engine.

[0028] In some optional embodiments, the hardware-level comparison and judgment steps include:

[0029] A parallel comparator array compares the multimodal input signal with a threshold defined in the hardware configuration parameters in parallel to output the comparison result signal.

[0030] Furthermore, the comparison result signals are combined by a programmable logic matrix according to the Boolean logic relationships defined in the hardware configuration parameters to generate a comparison judgment result.

[0031] In some optional embodiments, the method further includes:

[0032] A reconfigurable hardware actuator uses a unified global clock signal to synchronize the monitoring of multimodal input signals and the transmission of multimodal output signals.

[0033] In some optional embodiments, the method further includes:

[0034] When the comparison and judgment result meets the event triggering logic, the reconfigurable hardware actuator latches the current value of a timestamp counter driven by a global clock signal to generate an event timestamp that is synchronized with the multimodal output signal in time.

[0035] In some alternative embodiments, the step of monitoring the multimodal input signal includes:

[0036] An analog-to-digital converter module is used to acquire analog signals and convert them into digital quantities, which are then monitored as analog data signals.

[0037] In some alternative embodiments, the step of generating a multimodal output signal includes:

[0038] An analog voltage signal is generated as an analog control signal through a digital-to-analog converter module.

[0039] This invention provides a modular synchronous triggering system with a reconfigurable hardware logic engine, comprising:

[0040] The host unit is equipped with standard interface slots.

[0041] The input / output unit is pluggably mounted in a standard interface slot and is configured to interact with external devices using multimodal signals, including multimodal input signals and multimodal output signals.

[0042] A central control unit, electrically connected to a standard interface slot, and including:

[0043] The management processor is configured to receive user-defined event triggering logic and generate hardware configuration parameters based on the event triggering logic.

[0044] A reconfigurable hardware executor, with an integrated event logic execution engine, is configured as follows:

[0045] Receive hardware configuration parameters sent by the management processor to configure the event logic execution engine;

[0046] The configured event logic execution engine, at the hardware level, compares and judges the multi-mode ambiguity input signals (including at least one of digital pulse signals, analog data signals, audio and video data streams, software communication data packets, and user operation information) input through the input / output unit with the event triggering logic, and generates the comparison and judgment results.

[0047] Furthermore, when the comparison and judgment result satisfies the event triggering logic, a multimodal output signal containing at least one of digital pulse signals, analog control signals, and software control instructions is generated and sent to an external device through the input / output unit.

[0048] In some alternative embodiments, the system is applied in the field of clinical medical research, and the external devices include at least one of a motion capture system, a force table, an electromyography / electroencephalography (EEG) acquisition device, and medical imaging equipment.

[0049] In some optional embodiments, the event logic execution engine includes:

[0050] A parallel comparator array is used to compare the input multimodal input signal with a threshold defined in the hardware configuration parameters in parallel and output the comparison result signal.

[0051] And a programmable logic matrix, used to receive the comparison result signal and combine the comparison result signal according to the Boolean logic relationship defined in the hardware configuration parameters to generate the comparison judgment result.

[0052] In some optional embodiments, the central control unit further includes a unified clock module driven by a high-stability crystal oscillator; the reconfigurable hardware actuator also includes a high-resolution timestamp counter driven by a clock signal generated by the unified clock module; the reconfigurable hardware actuator is further configured to latch the current value of the timestamp counter to generate an event timestamp that is time-synchronized with the multimodal output signal when the comparison judgment result satisfies the event triggering logic.

[0053] In some alternative embodiments, the reconfigurable hardware actuator also includes a hardware-implemented neural network inference accelerator configured to perform real-time inference on the real-time data stream in the multimodal input signal to output an AI analysis result signal and provide the AI ​​analysis result signal to the event logic execution engine for comparison and judgment.

[0054] In some alternative embodiments, the reconfigurable hardware actuator is a field-programmable gate array (FPGA), and the management processor is a microcontroller (MCU).

[0055] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0056] The modular synchronous triggering method and system with a reconfigurable hardware logic engine of the present invention has the following beneficial effects:

[0057] This invention achieves sub-microsecond synchronous triggering of multimodal input signals by employing a heterogeneous master-slave computing architecture and a reconfigurable event logic execution engine. Users can customize complex event logic through a graphical interface, enabling intelligent judgment and control of multi-source heterogeneous signals without coding, thus improving triggering flexibility and experimental design freedom. Modular design allows the system to flexibly adapt to various devices, reducing integration difficulty and cost. By integrating an AI inference accelerator, intelligent closed-loop control based on complex scenario understanding is achieved, expanding the system's application scenarios and automation level. This invention can significantly improve scientific research and production efficiency. Attached Figure Description

[0058] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0059] Figure 1 This is a flowchart of a modular synchronous triggering method with a reconfigurable hardware logic engine according to an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of the structure of a modular synchronous triggering system with a reconfigurable hardware logic engine according to an embodiment of the present invention. Detailed Implementation

[0061] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0062] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0063] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined. Therefore, the actual execution order may change depending on the specific circumstances.

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of protection of the invention. The technical solution of this invention relies on a heterogeneous computing architecture, which decomposes computing tasks into control tasks and data processing tasks, and assigns them to different types of processors for execution. Control tasks are typically executed by general-purpose processors, responsible for logic control, task scheduling, and user interaction; data processing tasks are executed by dedicated hardware accelerators, responsible for high-speed parallel data processing and real-time response. This architecture can fully utilize the advantages of different types of processors, achieving a balance between flexibility and high performance. Furthermore, reconfigurable computing technology, through dynamic configuration of hardware logic, adapts to different algorithms and applications, greatly improving the utilization of hardware resources and the flexibility of the system. By transforming complex event triggering logic into configurable hardware parameters and utilizing high-speed parallel hardware circuits for real-time comparison and judgment, sub-millisecond synchronous triggering of multi-source heterogeneous signals is achieved, providing a precise time reference for multimodal data fusion.

[0065] like Figure 1 As shown, this embodiment of the invention provides a modular synchronous triggering method with a reconfigurable hardware logic engine, the method comprising the following steps:

[0066] In step S100, the management processor receives user-defined event triggering logic and generates hardware configuration parameters based on the event triggering logic. In one embodiment, the management processor can be a microcontroller unit (MCU) running an embedded operating system. The user defines the event triggering logic through a graphical user interface (GUI) or a command-line interface (CLI). For example, the user defines a trigger condition as "triggered when the amplitude of input signal A is greater than threshold X and the frequency of input signal B is less than threshold Y". The management processor parses this logic and generates corresponding hardware configuration parameters, such as: {input signal A channel number, comparator type: greater than, threshold X value, input signal B channel number, frequency calculation method, comparator type: less than, threshold Y value, logical relationship: AND}. In some other optional embodiments, the management processor can also be a personal computer or a server, receiving remotely defined user-defined event triggering logic through a network interface.

[0067] In step S200, the management processor sends hardware configuration parameters to the reconfigurable hardware executor to configure the event logic execution engine integrated within the reconfigurable hardware executor. In one embodiment, the reconfigurable hardware executor is a field-programmable gate array (FPGA). The management processor writes the hardware configuration parameters into the configuration registers of the event logic execution engine (RELE) inside the FPGA via a bus interface (such as PCIe, AXI, or SPI). For example, the parameters generated in step S100 are written into the configuration registers of comparators, counters, and logic gates inside the RELE. In some other alternative embodiments, the reconfigurable hardware executor can also be a complex programmable logic device (CPLD).

[0068] In step S300, the configured event logic execution engine monitors in real-time, in parallel, one or more sources of multimodal input signals containing at least one of the following signal types through the input / output unit: digital pulse signals, analog data signals, audio / video data streams, software communication data packets, and user operation information. In one embodiment, the input / output unit includes an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a digital input / output (DIO) interface, and a network interface. RELE acquires multimodal input signals from external devices in real-time through these I / O interfaces. For example, it acquires analog voltage signals from the ADC, reads digital pulse signals from the DIO interface, and receives Ethernet data packets from the network interface. RELE integrates multiple parallel signal processing units internally, enabling it to process signals from different channels simultaneously. In other optional embodiments, the input / output unit may also include a Universal Serial Bus (USB) interface, a Serial Peripheral Interface (SPI), or an Internal Integrated Circuit (I2C) interface.

[0069] In step S400, the event logic execution engine compares the multimodal input signal with the event triggering logic at the hardware level and generates a comparison result. In one embodiment, RELE internally includes a hardware comparator array and a programmable logic unit. The comparator array compares the analog signal acquired in step S300 with the threshold configured in step S200 to generate a comparison result. The programmable logic unit combines the comparison results according to the logic relationship configured in step S200 to generate the final comparison result. For example, if the triggering condition is "signal A > threshold X and signal B threshold Y", the programmable logic unit is configured as an AND gate, with its input connected to the inverted outputs of the comparator for signal A and the comparator for signal B. The output of the AND gate is the comparison result. In some other optional embodiments, a lookup table (LUT) can also be used to implement the programmable logic unit.

[0070] In step S500, when the comparison result satisfies the event triggering logic, a multimodal output signal containing at least one of the following signal types is generated and sent to an external device through the input / output unit: a digital pulse signal for controlling the external device, an analog control signal, and a software control command. In one embodiment, when the comparison result in step S400 is "true," RELE outputs a digital pulse signal through the DIO interface to trigger the external device. Simultaneously, RELE can also output an analog voltage signal through the DAC to control the parameters of another external device. Furthermore, RELE can send a TCP / IP data packet containing control commands through the network interface for remotely controlling a network device. In some other optional embodiments, the on / off state of the external device can be controlled through a relay output.

[0071] The aforementioned technical features work together to achieve a reconfigurable and modular synchronous triggering system. The management processor is responsible for parsing the event triggering logic and generating hardware configuration parameters, the reconfigurable hardware actuator is responsible for real-time signal monitoring and hardware-level comparison and judgment, and the input / output unit is responsible for the acquisition and output of multimodal signals. This architecture combines the flexibility of software with the real-time performance of hardware, solving the problems of poor synchronization accuracy, rigid triggering mechanisms, and poor compatibility and scalability in existing technologies. It realizes a unified control platform that can be compatible with multiple input signals, support user-defined complex event logic, and synchronously trigger multiple external devices with high precision.

[0072] Through the above solution, this embodiment can realize user-defined complex event triggering based on multimodal input signals. Compared with the prior art, the advantages of this embodiment are: it can provide higher synchronization accuracy, greater triggering flexibility, better compatibility and scalability, and stronger real-time performance.

[0073] This system is applied in the field of clinical medical research. Specifically:

[0074] The system can be applied to assess motor function in patients with Parkinson's disease. The motion capture system is configured to capture the three-dimensional motion trajectory of the patient while performing specified actions (such as walking, standing, and balance tests). A force platform is used to measure the ground reaction force during standing and walking. An electromyography (EMG) acquisition device is used to record surface EMG signals from the patient's lower limb muscles. All these devices are connected through the system's I / O modules and are uniformly triggered by the central control unit.

[0075] The trigger condition is set as follows: when the patient begins walking (identified by the motion capture system) and the electromyographic signal of the right biceps femoris muscle exceeds a preset threshold, all devices are triggered to simultaneously begin data acquisition. This system, through its high-precision timestamp function, provides an accurate time reference for subsequent comprehensive analysis of kinematic, dynamic, and neuromuscular electrical activity.

[0076] The system can also be applied to monitor rehabilitation training for stroke patients. An EEG acquisition device is configured to monitor the patient's brain activity in real time. Medical imaging equipment (such as functional magnetic resonance imaging, fMRI) is used to observe brain activation areas during rehabilitation movements. Triggering conditions are set so that when a specific rhythmic pattern appears in the patient's EEG signal (e.g., a mu rhythm associated with motor intention) and the fMRI scanner is ready, the rehabilitation robot is triggered to assist the patient in completing a preset movement. This achieves closed-loop control based on the brain-computer interface, which helps promote the remodeling of the patient's neural function.

[0077] The system can also be used to assess gait characteristics in patients with osteoarthritis. A force table measures plantar pressure distribution during the gait cycle, a high-speed camera records knee joint activity, and ultrasound equipment detects changes in articular cartilage thickness. When the force table data indicates that the patient has entered a single-leg standing phase, and the high-speed camera captures the maximum knee flexion angle, the ultrasound equipment is triggered to perform a scan.

[0078] In other alternative implementations, external devices may include, but are not limited to, eye trackers, respiratory gas analyzers, and heart rate variability analyzers. Analog-to-digital converter modules with higher sampling rates and higher resolutions can be selected. Furthermore, trigger events can also be manually marked by the operator through a user interface as a supplementary triggering method.

[0079] Through the above-described solution, this embodiment provides a high-precision, highly flexible, and highly compatible multimodal data synchronous acquisition and device linkage control platform for clinical medical research, thereby significantly improving research efficiency and data quality. Compared with existing technologies, the beneficial effects of this embodiment are: it enables multimodal, multi-device collaborative research targeting specific diseases or physiological processes, enhancing the depth and breadth of medical research.

[0080] In one specific implementation, based on the above embodiments, the event triggering logic includes level triggering logic, which is configured to trigger the generation or cessation of the multimodal output signal when the amplitude of the analog data signal in the multimodal input signal meets a preset threshold condition.

[0081] Specifically, when configuring event triggering logic on the graphical interface, the user selects the "Level Triggered" mode. At this time, the user interface will present additional configuration options, including: signal source channel selection (e.g., "ADC_CH3"), threshold setting (allowing input of specific values, such as "2.5V"), and comparison method selection (providing options such as "greater than", "less than", and "equal to"). After completing these configurations, the user clicks the "Apply" button, and the MCU will convert these parameters into corresponding hardware configuration parameters.

[0082] Then, the MCU sends the hardware configuration parameters to the Event Logic Execution Engine (RELE) inside the FPGA. RELE configures its internal parallel comparator array based on these parameters. For example, if the user selects "ADC_CH3", the comparison mode is "greater than", and the threshold is "2.5V", RELE connects the input of one comparator in the parallel comparator array to the data bus of ADC_CH3 and sets its threshold register to the digitally encoded value corresponding to 2.5V. The comparator's output signal represents the result of whether the real-time voltage value of ADC_CH3 is greater than 2.5V.

[0083] Next, when the system is running, the analog voltage signal from ADC_CH3 is converted from analog to digital and enters the FPGA's RELE function as a digital signal. The comparator compares this digital signal with a set threshold in real time. If the voltage value is greater than 2.5V (meeting the preset threshold condition), the comparator outputs a high level, indicating that the trigger condition is met. This high-level signal is sent to the RELE output action mapping unit, which generates the corresponding multimode output signal according to the pre-configured output action (e.g., triggering TTL_OUT1 to output a pulse). On the other hand, if the voltage value is less than or equal to 2.5V, the comparator outputs a low level, the trigger condition is not met, and no output signal is generated.

[0084] In some alternative implementations, the comparison mode can be set to "less than," meaning that the output signal is only triggered when the amplitude of the analog signal is lower than a set threshold. In other implementations, a hysteresis comparator can be used, which sets two thresholds (an upper threshold and a lower threshold) to prevent the output signal from frequently changing when signal jitter occurs near the threshold.

[0085] Through the above scheme, this embodiment can realize level triggering based on the amplitude of analog signals, expand the triggering mode of the system, and adapt to a wider range of application needs.

[0086] In one specific implementation, based on the above embodiments, the RELE output action mapping unit, in addition to driving TTL_OUT to output a high level, also starts a programmable timer. First, this timer is pre-configured to the required time interval t, for example, set by configuration parameters written to the MCU, t=500 microseconds. Then, the timer starts counting down from the initial value, the counting clock obtained by frequency division of the aforementioned globally unified clock, thereby ensuring the accuracy and stability of the timing. Next, while TTL_OUT remains high, the timer continues to run. When the timer counts to zero, the output action mapping unit forcibly pulls TTL_OUT back to a low level, regardless of whether the pressure sensor signal is still higher than 3.0V. Specifically, if the pressure sensor signal has dropped below 3.0V before the timer expires, TTL_OUT will naturally stop outputting; if the pressure sensor signal is still higher than 3.0V when the timer expires, the timer will forcibly end the output of TTL_OUT, thereby achieving the limitation of "stopping the generation of multimodal output signals after the amplitude meets the threshold condition and continues for a preset time t." In some other alternative implementations, the timer may also count up and stop outputting TTL_OUT when a preset value is reached. Alternatively, the timer may be replaced with a programmable monostable multivibrator whose output pulse width is the preset time t.

[0087] Through the above solution, this embodiment can avoid the problem of excessively long output signal duration caused by unexpected fluctuations or interference in the input signal, ensuring the accuracy and controllability of the trigger signal, thereby preventing external devices from malfunctioning or being damaged.

[0088] In one specific implementation, based on the above embodiments, the event triggering logic can be set to edge triggering. First, a digital-to-digital converter circuit is added to each channel of the analog input module to convert the analog signal into a corresponding digital pulse signal. Specifically, this circuit can be a zero-crossing comparator, which outputs a high level when the input signal voltage is higher than a preset reference voltage, and outputs a low level otherwise. Then, the digital pulse signal is connected to the input pin of the FPGA.

[0089] Next, an "Edge Triggered" node is added to the graphical user interface. Users can select the trigger edge type (rising edge or falling edge) and trigger channel on this node. After the MCU parses this node, it generates the corresponding hardware configuration parameters.

[0090] The reconfigurable event logic execution engine (RELE) within the FPGA is configured to continuously monitor the digital pulse signal of a specified channel. When a user-defined edge type is detected, RELE immediately triggers the corresponding output action. For example, if the user selects "rising edge trigger," RELE will immediately generate a trigger signal when it detects the digital pulse signal changing from low to high.

[0091] In some alternative implementations, the digital conversion circuit is not limited to a zero-crossing comparator; it can also be a Schmitt trigger to improve noise immunity. Furthermore, edge detection can also be implemented using a D flip-flop within the FPGA. When the rising edge of the clock arrives, if the input signal changes, the D flip-flop outputs a high level, thereby generating a trigger signal.

[0092] Through the above solution, this embodiment can achieve accurate detection and triggering of digital pulse signal edges, expand the system's triggering modes, and adapt to more application scenarios. Compared with the prior art, the advantages of this embodiment are: no additional hardware circuitry is required; multiple edge triggering modes can be implemented solely through software configuration, reducing system costs and improving flexibility.

[0093] In one specific implementation, based on the above embodiments, the event triggering logic adopts an instruction triggering mode. First, the management processor pre-configures the format of the software communication data packets. The data packet format includes a data packet start identifier, data packet length, instruction code, and checksum. Specifically, the instruction code is defined as a two-byte hexadecimal number, for example, "0x01" represents starting acquisition, "0x02" represents stopping acquisition, and "0x03" represents setting parameters. Then, the management processor receives control instruction data packets from the host computer via an interface such as Ethernet or USB. Next, the event logic execution engine in the reconfigurable hardware actuator parses the received data packets, extracts the instruction code, and verifies the integrity of the data packets using the checksum. If the verification passes and the instruction code matches a preset instruction code, the event logic execution engine generates a trigger signal, thereby generating a corresponding multimodal output signal, such as sending a synchronous trigger pulse through the digital output module or sending a control voltage through the digital-to-analog converter module. In other optional implementations, the data packet format can adopt standard formats such as JSON or XML, and the instruction code can also be an ASCII string or an enumeration type.

[0094] Through the above scheme, this embodiment can realize software instruction-based trigger control, expand the system's triggering methods, and enable it to respond to control instructions from the host computer or other external devices, thereby realizing a more flexible automated control process.

[0095] In one specific implementation, based on the above embodiments, the event triggering logic adopts a data triggering mode. First, multi-channel electromyography (EMG) signal data is received from the analog input module. Specifically, these EMG signals are converted into digital signals by an analog-to-digital converter and sent to a sliding window in real time. Then, the root mean square (RMS) value is calculated for the EMG signal data within the sliding window. Next, the calculated RMS value is compared with a preset threshold. When the RMS value exceeds the threshold, a "muscle activation" event is determined to have occurred, and the digital output module is triggered to send a synchronous trigger signal.

[0096] In other alternative implementations, the trigger index is not limited to the root mean square value; other electromyographic signal characteristic parameters such as integrated electromyography (iEMG), median frequency (MF), or average power frequency (MPF) can also be used. The preset conditions are not limited to a single threshold comparison; they can also be a combination of multiple thresholds or a set allowable RMS value range.

[0097] Through the above scheme, this embodiment can realize trigger control based on real-time analysis of electromyographic signals, which solves the problem that traditional triggering methods cannot respond to complex physiological signal changes and improves the level of intelligence in biomedical experiments.

[0098] In one specific implementation, based on the above embodiments, the event triggering logic adopts a hybrid triggering mode, combining level triggering, edge triggering, instruction triggering, and data triggering.

[0099] First, the analog input module's ADC_CH1 is configured in level-triggered mode with a threshold value of 3.0V. This means that the level-triggered condition is met when the voltage of the pressure sensor connected to ADC_CH1 exceeds 3.0V.

[0100] Specifically, a certain input channel (TTL_IN) of the digital I / O module is configured in rising edge trigger mode. Therefore, if an external device sends a rising edge signal to the TTL_IN port, the edge trigger condition is also met.

[0101] Then, the system receives control commands sent by the host computer via the Ethernet interface. After the command parsing module detects a specific command code (e.g., TRIGGER_CMD), the command triggering condition is met.

[0102] Next, a real-time computing module is implemented within the FPGA to continuously monitor the data from the ADC_CH2 channel. This module calculates the Fast Fourier Transform (FFT) of the ADC_CH2 signal and extracts the amplitude of a specific frequency component as a trigger indicator. When this amplitude exceeds a preset value, the data trigger condition is met.

[0103] Finally, RELE is configured to trigger an output action when any three or all of the above four triggering conditions are met. The programmable logic matrix is ​​configured to implement the following Boolean logic: (Level Trigger AND Edge Trigger AND Instruction Trigger) OR (Level Trigger AND Edge Trigger AND Data Trigger) OR (Level Trigger AND Instruction Trigger AND Data Trigger) OR (Edge Trigger AND Instruction Trigger AND Data Trigger).

[0104] In other alternative implementations, the hybrid triggering logic can include any combination of the four triggering methods mentioned above. The Boolean logic relationships of the programmable logic matrix can also be adjusted according to specific application scenarios, for example, configured to trigger only when all conditions are met simultaneously. The triggering conditions and the final output results can be flexibly configured through a graphical interface.

[0105] Through the above scheme, this embodiment can realize a more complex and flexible trigger control strategy, and can respond to complex events defined by multiple heterogeneous signals, thereby improving the system's adaptability and intelligence level.

[0106] In one specific implementation, based on the above embodiments, firstly, real-time data such as video data streams or bioelectrical signals from externally input multimodal signals are connected to a pre-built hardware neural network inference accelerator within the FPGA. Specifically, this hardware neural network inference accelerator can be implemented using tools such as Xilinx Vitis AI or Intel OpenVINO, which quantize, prune, and convert offline-trained deep learning models into hardware description language (HDL) code. The neural network inference accelerator processes the input data stream in real time; for example, for video data streams, it performs image recognition or object detection; for bioelectrical signals, it performs feature extraction and pattern classification. Then, the accelerator outputs a single-bit AI analysis result signal, indicating whether a specific event has occurred, such as whether a specific object was detected in the video or whether a specific physiological state was identified in the bioelectrical signals. Next, this AI analysis result signal is used as a new logical input source and connected to the input of the programmable logic matrix of the Event Logic Execution Engine (RELE). The Event Logic Execution Engine (RELE) combines the AI ​​analysis result signal with other input signals (e.g., analog signals from a pressure sensor) to implement user-defined complex event triggering logic through a programmable logic matrix. Ultimately, the RELE will only trigger the corresponding output action when the AI ​​analysis result signal and other input signals simultaneously meet preset logic conditions. In some alternative implementations, this hardware-implemented neural network inference accelerator can be replaced with other types of dedicated hardware accelerators, such as hardware accelerators for Fast Fourier Transform (FFT) or Wavelet Transform, to accelerate signal preprocessing and feature extraction, and then input the extracted features as the AI ​​analysis result signal into the RELE.

[0107] Through the above solution, this embodiment can deeply integrate the real-time analysis capabilities of artificial intelligence into the hardware triggering decision loop, enabling the triggering conditions to leap from simple physical thresholds to intelligent scene understanding, and realizing intelligent and automated control based on complex scene understanding.

[0108] In one specific implementation, based on the above embodiments, the process of configuring the event logic execution engine is as follows: First, the management processor receives the event triggering logic set by the user through the graphical user interface. Specifically, the user selects the desired input signal source (e.g., a specific channel from a specific I / O module) on the interface and defines the expected logical relationship (e.g., greater than, less than, equal to, AND, OR, NOT, etc.). Then, the management processor converts these user-defined configuration information into a series of hardware configuration parameters. These parameters specify the specific operating modes of the comparator array and programmable logic matrix inside the event logic execution engine. Next, these hardware configuration parameters are written to a specific memory address of the reconfigurable hardware executor. The reconfigurable hardware executor reads these parameters and, based on the parameter values, configures its internal comparator array, specifying the input signal channel to be monitored by each comparator, the comparison threshold, and the comparison operation type. Simultaneously, the programmable logic matrix is ​​also configured to implement the user-defined Boolean logic operations, combining the outputs of the comparator array to generate the final trigger signal. In some other optional implementations, the configuration information can also be loaded into the reconfigurable hardware executor in the form of a pre-compiled configuration file or firmware image.

[0109] Through the above scheme, this embodiment can flexibly configure the comparator array and programmable logic matrix inside the event logic execution engine according to the user-defined event triggering logic, thereby realizing real-time monitoring and triggering of various complex events, and enhancing the adaptability and programmability of the system.

[0110] In one specific implementation, based on the above embodiments, the configuration and operation process of the parallel comparator array and programmable logic matrix inside the Event Logic Execution Engine (RELE) in the FPGA are further described in detail.

[0111] First, the parallel comparator array consists of multiple independent, configurable comparators. Each comparator has a data input, a threshold input, and a comparison result output. The data input is connected to an input data channel specified by the MCU, such as a sampled data bus from a specific channel of the ADC module, or an event flag signal from the AI ​​accelerator. The threshold input is connected to a register that stores threshold parameters issued by the MCU. The MCU can dynamically change the threshold level of each comparator by writing different values ​​to these registers. The comparator type can also be configured, such as greater than, less than, equal to, greater than or equal to, less than or equal to, not equal to, etc. In a specific example, if a comparator is configured to monitor whether the voltage signal of ADC_CH1 is greater than 3.0V, the MCU will configure the comparator's data input to be connected to the data bus of ADC_CH1, set its comparison type to "greater than", and set its threshold register to the digitally encoded value corresponding to 3.0V.

[0112] Specifically, when RELE starts operating, each comparator compares the data received at its data input with the threshold received at its threshold input on the rising edge of its clock cycle, and outputs the comparison result (a single-bit "true" or "false" signal) to its comparison result output. These comparison result signals are sent in parallel to the inputs of the programmable logic matrix.

[0113] The programmable logic matrix is ​​a hardware circuit composed of lookup tables (LUTs) or logic gate arrays. Its function is determined by configuration parameters written to it by the MCU. The MCU can configure the matrix's internal connections and logic functions to implement any user-defined Boolean logic combinations such as AND, OR, and NOT. Each input of the matrix is ​​connected to the output of a comparator, and the matrix's output is connected to an output action mapping unit. For example, if the user wants to trigger the operation when "ADC_CH1 > 3.0V and the AI ​​recognizes a specific posture," the MCU will configure the logic matrix as a two-input AND gate, connecting one input to the output of the comparator monitoring ADC_CH1 and the other input to the output of the AI ​​accelerator. The AND gate's output is true only when both input signals are true, indicating that the trigger condition is met.

[0114] Next, the matrix's output signal is sent to the output action mapping unit. The output action mapping unit executes the corresponding output action according to the configuration information pre-written by the MCU. For example, it outputs a TTL pulse or sends a control command to an external device. In other alternative implementations, the programmable logic matrix can also be implemented using other forms of logic circuits, such as a NAND gate-based logic array or a multiplexer-based logic function generator. The comparator array can also employ different comparator designs, such as successive approximation comparators or integrating comparators, to accommodate different signal types and accuracy requirements.

[0115] Through the above solution, this embodiment can realize the real-time judgment of complex events in a purely hardware manner, reducing system latency and improving triggering accuracy.

[0116] In one specific implementation, based on the above embodiments, firstly, the global clock module inside the central control unit provides a unified clock signal to the reconfigurable hardware actuator. Specifically, this clock signal may be a fixed-frequency clock, such as 200MHz, or it may be a programmable clock whose frequency can be dynamically adjusted by the management processor to adapt to different application scenarios and I / O module requirements. Then, the reconfigurable hardware actuator uses this unified clock signal as the timing reference for all its internal operations, including but not limited to: data sampling, data transmission, and data processing of input / output units, comparison and judgment by the event logic execution engine, and generation and transmission of output signals. Next, the reconfigurable hardware actuator uses auxiliary signals such as clock enable signals and data valid signals to ensure that the input / output units read and write data within precisely aligned clock cycles. The transmission of output signals is also synchronized with this unified clock signal, ensuring that the output signals can be sent to external devices in a timely and accurate manner when the event triggering logic is satisfied. In some other alternative implementations, the reconfigurable hardware actuator can also derive multiple clock signals of different frequencies from a unified global clock signal through an internal clock divider or multiplier, and use them to drive different modules, as long as these clock signals all originate from the same global clock source.

[0117] Through the above scheme, this embodiment can ensure that the monitoring of multimodal input signals and the transmission of multimodal output signals are based on the same time base, thereby eliminating synchronization errors caused by clock drift or different clock domains, and further improving the synchronization accuracy and reliability of the system.

[0118] In one specific implementation, building upon the above embodiments, firstly, a 64-bit binary counter is implemented within the FPGA using a hardware description language (such as Verilog or VHDL). This counter uses a globally unified clock signal as its clock source and accumulates counts on each rising edge of the clock. Specifically, if the frequency of the globally unified clock signal is 200MHz, the counter's resolution is 5 nanoseconds. Then, when the Reconfigurable Event Logic Execution Engine (RELE) determines that the event triggering condition is met (e.g., the comparator array output meets preset logic), RELE generates a latch control signal that drives a D flip-flop array. The inputs of this D flip-flop array are connected to the respective output bits of the 64-bit counter, and its outputs are connected to a 64-bit event timestamp register. Next, on the valid edge (e.g., rising edge) of the latch control signal, the D flip-flop array latches the current count value of the 64-bit counter into the event timestamp register. This latching operation is completed within a single clock cycle, ensuring the accuracy of the timestamp.

[0119] Specifically, the event timestamp register can be implemented as a double-buffered structure. While one timestamp is being latched and written, the contents of the other buffer can be read by the management processor (MCU), thus avoiding read-write conflicts.

[0120] In other alternative implementations, the timestamp counter can employ different bit widths (e.g., 32-bit or 48-bit) and different counting bases (e.g., decimal BCD code), as long as its resolution and counting range meet the application requirements. Furthermore, the D flip-flop array can be replaced with other hardware circuit structures with latching capabilities, such as transparent latches.

[0121] Through the above scheme, this embodiment can generate a globally unified timestamp for each triggered event in a purely hardware manner with sub-microsecond time accuracy, providing a reliable time reference for the accurate synchronization and fusion analysis of subsequent multimodal data.

[0122] In one specific implementation, based on the above embodiments, the acquisition and conversion of analog signals are achieved through an analog-to-digital converter (ADC) module. First, the analog signal is input to a signal conditioning circuit located on the input / output unit. This signal conditioning circuit includes an instrumentation amplifier and a low-pass filter, used for preliminary amplification, noise filtering, and impedance matching of the input signal to ensure that the signal meets the input requirements of the ADC. Specifically, the instrumentation amplifier uses an AD8221 chip from Analog Devices, with a gain set to 10. The low-pass filter is a second-order Butterworth filter with a cutoff frequency set to 1kHz, used to suppress noise higher than the effective signal frequency.

[0123] The conditioned analog signal is then fed into Analog Devices' AD7606 chip, a 16-bit, 8-channel synchronous sampling analog-to-digital converter. Driven by the sampling clock provided by the FPGA, the AD7606 chip converts the analog signal into a 16-bit digital value at a sampling rate of up to 200kSPS. The converted digital signal is then transmitted to the FPGA's event logic execution engine via a parallel bus.

[0124] Next, the FPGA processes the received digital signal according to pre-configured parameters. For example, if the event triggering logic sets a voltage threshold, the FPGA will compare the converted digital value with the preset digital threshold to determine whether the triggering condition is met.

[0125] In other alternative implementations, the analog-to-digital converter (ADC) module can utilize Analog Devices' AD7779 chip, a 24-bit, 8-channel synchronous sampling ADC that offers higher conversion accuracy and signal-to-noise ratio. The cutoff frequency of the low-pass filter in the signal conditioning circuit can be adjusted according to the specific application scenario; for example, a higher cutoff frequency can be set when acquiring higher frequency signals. Furthermore, different analog-to-digital conversion technologies, such as Σ-Δ ADCs, can be employed to suit various application requirements.

[0126] Through the above-described scheme, this embodiment can achieve high-precision acquisition and conversion of analog signals, providing a reliable data foundation for subsequent event-triggered logic judgment. Compared with the prior art, the advantages of this embodiment are: it can provide high-precision data acquisition, and through flexible configuration of signal conditioning circuits and optional ADC chip solutions, it can adapt to different types and frequency ranges of analog signals, thus expanding the application range of the system.

[0127] In one specific implementation, based on the above embodiments, the process of generating a multimodal output signal includes: First, the management processor determines the amplitude of the analog voltage signal to be output. Then, the management processor sends this amplitude data, in digital form, to the digital-to-analog converter (DAC) module via an internal bus. Specifically, the DAC module can use the Analog Devices AD5791 chip, which is a voltage output DAC with 16-bit resolution. Next, after receiving the digital amplitude data, the DAC module converts it into a corresponding analog voltage signal through its internal digital-to-analog conversion circuit. The voltage range of this analog voltage signal can be configured to 0-5V or ±10V. The analog voltage signal passes through a signal conditioning circuit (such as an amplifier or attenuator) to meet the voltage range and driving capability required by the external device. Finally, the conditioned analog voltage signal is output through an I / O interface (such as a BNC interface) as an analog control signal to control external devices, such as controlling the output voltage of a programmable power supply or controlling the displacement of a piezoelectric ceramic.

[0128] In other alternative implementations, the digital-to-analog converter module may also use different DAC chips, such as the AD9708 with a higher conversion rate or the LTC2645 with a higher output current, to suit different application requirements.

[0129] Through the above solution, this embodiment can generate accurate analog voltage signals, providing continuously adjustable control inputs for external devices, thereby expanding the application scope of the system and enabling it to support more application scenarios that require analog quantity control.

[0130] like Figure 2 As shown, this embodiment of the invention provides a modular synchronous triggering system with a reconfigurable hardware logic engine, the system comprising:

[0131] The host unit M100 is equipped with standard interface slots. The host unit M100 can be a standard industrial control computer chassis, providing power supply, cooling, and structural support. The standard interface slots are used to connect various functional modules, such as PCIe, USB, or custom backplane bus interfaces.

[0132] An input / output unit M200, pluggably mounted in a standard interface slot, is configured to interact with external devices using multimodal signals, including multimodal input and output signals. The input / output unit M200 performs the acquisition, conditioning, and output of various signals, enabling the system to be compatible with different types and standards of external devices. For example, the input / output unit M200 may include analog signal acquisition circuitry, digital signal transceiver circuitry, and physical layer interfaces for various communication protocols. In other alternative implementations, the input / output unit M200 may employ fiber optic interfaces, wireless communication interfaces, etc., to adapt to different application scenarios.

[0133] A central control unit M300, which is electrically connected to a standard interface slot, and includes:

[0134] A management processor is configured to receive user-defined event-triggered logic and generate hardware configuration parameters based on that logic. The management processor handles high-level tasks such as human-computer interaction, logic parsing, parameter calculation, and communication. The management processor can be a general-purpose CPU, microcontroller, or embedded system.

[0135] A reconfigurable hardware actuator integrates an event logic execution engine. The reconfigurable hardware actuator is configured to: receive hardware configuration parameters from a management processor to configure the event logic execution engine; at the hardware level, the configured event logic execution engine compares and judges at least one of the following multi-mode input signals (including digital pulse signals, analog data signals, audio / video data streams, software communication data packets, and user operation information) input through the input / output unit M200 with the event triggering logic, and generates a comparison result; and when the comparison result satisfies the event triggering logic, it generates and sends a multi-mode output signal (including at least one of digital pulse signals, analog control signals, and software control instructions) to an external device through the input / output unit M200. The reconfigurable hardware actuator is the real-time component of the system, responsible for high-speed data processing and precise signal control. In one example, the reconfigurable hardware actuator can be an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), implementing different hardware logic functions by loading different configuration data.

[0136] In one implementation, the management processor communicates with the reconfigurable hardware executor via a bus interface (e.g., PCIe, AXI) to write hardware configuration parameters into the internal memory or registers of the reconfigurable hardware executor, thereby configuring the behavior of the event logic execution engine. The reconfigurable hardware executor, in turn, connects directly to the input / output unit M200 through its I / O interface to acquire input signals in real time and output control signals.

[0137] The aforementioned technical features work together to achieve real-time intelligent judgment and synchronous triggering of multi-source heterogeneous signals. The management processor is responsible for parsing user-defined complex event logic and converting it into hardware configuration parameters that the reconfigurable hardware actuator can understand. The reconfigurable hardware actuator, leveraging its highly parallel processing capabilities and reconfigurability, executes the event triggering logic at high speed and in real-time at the hardware level, and precisely controls the timing of output signals. Modular input / output interfaces provide physical layer compatibility with various signal types, enabling the system to flexibly adapt to different device combinations. This solution addresses the technical problems of poor synchronization accuracy, rigid triggering mechanisms, and poor compatibility and scalability in existing technologies on a unified and scalable platform.

[0138] Through the above solution, this embodiment provides a high-precision, highly flexible, and highly compatible multi-modal, multi-device synchronous triggering control platform. Compared with the prior art, the advantages of this embodiment are: it achieves compatibility with multiple input signals, supports user-defined complex event logic, and can synchronously trigger multiple external devices with sub-millisecond precision.

[0139] In one specific implementation, based on the above embodiments, this modular synchronous triggering system is applied to a clinical medical study on human motion control. The external equipment specifically includes: a Vicon motion capture system for accurately recording the motion trajectory of the human skeleton; an AMTI force table for measuring the force between the human body and the ground; a Delsys surface electromyography (sEMG) acquisition device for recording the electrical activity of muscles; and an ultrasound imaging device for observing morphological changes in muscles.

[0140] In this application scenario, the input / output unit M200 is configured as follows:

[0141] A 16-channel analog input module is used to acquire analog voltage signals output from the force platform, representing the magnitude of the vertical ground reaction force (vGRF), and analog signals output from the sEMG acquisition unit, representing the electrical activity of muscles. This analog input module includes high-precision, low-noise signal conditioning circuitry and a 24-bit analog-to-digital converter to ensure accurate capture of weak bioelectrical signals.

[0142] An 8-channel analog output module is used to send analog control signals to the ultrasound imaging equipment to control its scanning depth and frequency.

[0143] An Ethernet interface module is used to receive kinematic data from the Vicon motion capture system, which is transmitted in the form of UDP packets and contains three-dimensional coordinates and attitude information.

[0144] The central control unit M300 achieves the following collaborative workflow through these input / output units M200:

[0145] The motion capture system transmits human motion data to the central control unit M300 in real time; the management processor analyzes this data and extracts the knee joint angle information.

[0146] The force table measures the vertical ground reaction force in real time. This signal is acquired by the analog input module and converted into a digital signal, which is then transmitted to the reconfigurable hardware actuator.

[0147] The reconfigurable hardware actuator determines whether the triggering conditions are met based on preset event triggering logic. An exemplary event triggering logic is: "When the knee flexion angle is greater than 30 degrees and the vertical ground reaction force is greater than 50% of body weight," the ultrasound imaging device and sEMG acquisition instrument are triggered to perform synchronous acquisition.

[0148] Once the triggering conditions are met, the reconfigurable hardware actuator immediately sends a control signal to the ultrasound imaging device through the analog output module, causing it to begin scanning the target muscle; at the same time, it sends a TTL trigger signal to the sEMG acquisition instrument through the digital I / O module, causing it to begin recording the electrical activity of the muscle.

[0149] The reconfigurable hardware actuator latches a hardware timestamp and associates the timestamp with the acquired kinematic, mechanical, and electromyographic data, providing an accurate time reference for subsequent data fusion analysis.

[0150] In some alternative embodiments, the motion capture system, force platform, electromyography / electroencephalography (EMG) acquisition device, and medical imaging equipment described above can be replaced with other commonly used detection, stimulation, or treatment devices in the field of clinical medicine, such as transcranial magnetic stimulation (TMS) devices, deep brain stimulation (DBS) devices, and electrocardiogram (ECG) monitors. In other alternative embodiments, the central control unit M300 of this embodiment can also integrate a function for monitoring the safety status of medical devices, such as real-time monitoring of parameters like temperature, voltage, and current, and immediately stopping triggering when these parameters exceed safe limits to ensure patient safety.

[0151] Through the above solution, this embodiment can achieve precise synchronous control and data fusion of multiple clinical medical research devices on a unified platform, which greatly improves experimental efficiency and data quality, and provides powerful research tools for clinicians and researchers.

[0152] In one specific implementation, based on the above embodiments, the event logic execution engine (RELE) integrated inside the reconfigurable hardware actuator (FPGA) consists of a parallel comparator array and a programmable logic matrix.

[0153] The parallel comparator array comprises multiple independent, configurable digital comparators. Each comparator includes a data input, a threshold input, a comparison type selection, and a comparison result output. The data input is connected to the corresponding data bus of the input / output unit M200 (such as an ADC module or digital I / O module) to receive multimodal input signals. The threshold input is connected to a set of configuration registers to receive hardware configuration parameters from the management processor (MCU), which determine the comparator's threshold. The comparison type selection is also connected to the configuration registers to set the comparator's comparison mode, such as greater than (>), less than (==), greater than or equal to (>=), less than or equal to (=), and not equal to (!=). Each clock cycle, the comparator compares the input signal received at its data input with the threshold value at its threshold input according to the set comparison mode and outputs the comparison result (true / false) from its comparison result output. The number of comparators can be expanded according to the application scenario to support parallel monitoring of multiple input signal channels.

[0154] A programmable logic matrix consists of a two-dimensional lookup table (LUT) array or logic gate array. Each input of the matrix is ​​connected to the output of a comparator in a parallel comparator array. The internal connectivity and logic function of the matrix are determined by hardware configuration parameters from a microcontroller unit (MCU). By configuring these parameters, arbitrary Boolean logic combinations such as AND, OR, NOT, and XOR can be implemented within the matrix. For example, the matrix can be configured as a two-input AND gate, with its two inputs connected to the outputs of comparator 1 and comparator 2, respectively. The output of the AND gate is true only when both comparator 1 and comparator 2 are true. The output of the matrix is ​​connected to an output action mapping unit to trigger subsequent output actions. In other alternative implementations, the programmable logic matrix can also be implemented using other programmable logic devices, such as an interconnect structure based on a crossbar switch matrix or a logic selection structure based on a multiplexer (MUX).

[0155] Through the above scheme, this embodiment can realize parallel comparison of multiple input signals and complex Boolean logic operations, providing a hardware foundation for realizing user-defined complex event triggering logic.

[0156] In one specific implementation, based on the above embodiments, an OCXO (Oven Controlled Crystal Oscillator) is soldered onto the main control card of the central control unit M300 as a high-stability unified clock module. This OCXO typically operates at 10MHz with a frequency stability better than ±0.01ppm. The 10MHz clock signal generated by the unified clock module is input to the PS (Processing System) section of the Zynq-7020 SoC chip, where the clock management unit within the PS drives the FPGA logic in the PL (Programmable Logic) section.

[0157] Inside the FPGA, the Xilinx Vivado tool's Clocking Wizard IP core is used to multiply and divide the 10MHz clock from the PS, generating multiple clock signals of different frequencies to meet the needs of various system modules. For example, a 200MHz clock is generated as the operating clock for the RELE and high-speed data acquisition modules, and a 100MHz clock is generated as the clock for the Ethernet interface module. In this way, it is ensured that all timing-related operations in the entire system are synchronized with the same high-precision, low-jitter clock source.

[0158] Meanwhile, within the FPGA, a 64-bit timestamp counter module is implemented using Verilog HDL code. This counter is driven by the aforementioned 200MHz clock, incrementing by 1 each clock cycle, thus providing a timestamp resolution of 5 nanoseconds. The initial value of the timestamp counter can be set by the MCU at system startup, or it can be periodically synchronized with an external NTP server for absolute time calibration. When RELE detects that the trigger condition is met, it generates a latch signal, latching the current timestamp counter value into a separate register. This timestamp value can be read by the MCU and recorded along with the trigger event, or it can be embedded into the data stream for subsequent data synchronization and analysis.

[0159] In other alternative implementations, a rubidium atomic clock or a GPS-disciplined OCXO can be used as a unified clock module to achieve higher frequency stability and long-term accuracy. The number of bits in the timestamp counter can also be adjusted according to the needs of the application, for example, using a 48-bit or 32-bit counter to reduce resource consumption or simplify data processing. The timestamp can also be latched using a double-buffering mechanism, that is, using two registers to alternately latch the timestamp to avoid data conflicts during reading.

[0160] Through the above solution, this embodiment can provide a globally unified, high-precision time base, ensuring that all triggering events and data acquisition operations have nanosecond-level synchronization accuracy, which greatly improves the reliability of the system and the accuracy of data analysis.

[0161] In one specific implementation, based on the above embodiments, the reconfigurable hardware executor further includes a hardware-implemented neural network inference accelerator. This neural network inference accelerator is connected to the event logic execution engine within the reconfigurable hardware executor via a high-speed data bus. The neural network inference accelerator is configured to receive a real-time data stream from the multimodal input signals of the input / output unit M200, perform real-time inference on the data stream, and output an AI analysis result signal. This AI analysis result signal is then sent to the event logic execution engine as one of the bases for triggering event judgments.

[0162] Specifically, neural network inference accelerators can be implemented using dedicated hardware logic within a field-programmable gate array (FPGA), such as Xilinx's DPU (Deep Learning Processing Unit) or Intel's NPU (Neural Processing Unit). The accelerator is loaded with pre-trained neural network model parameters, designed to recognize specific types of events or patterns. For example, in medical monitoring applications, this model can be trained to identify abnormal waveforms in electrocardiogram (ECG) signals, such as premature ventricular contractions (PVCs) or atrial fibrillation (AFib).

[0163] Analog signals from the ECG acquisition unit are converted into digital signals via an analog-to-digital converter (ADC) module. These digital signals are simultaneously fed into two pathways: one pathway directly enters the parallel comparator array of the event logic execution engine for traditional amplitude threshold judgment; the other pathway enters the neural network inference accelerator. The accelerator analyzes the ECG data in real time and outputs a single-bit AI analysis result signal, which, for example, is set to high level when a premature ventricular contraction (PVC) is detected. The programmable logic matrix of the event logic execution engine is configured to perform a logical AND operation between the amplitude comparison result signal from the ADC module and the AI ​​analysis result signal from the neural network inference accelerator. Subsequent control operations, such as recording the timestamp of the event or sending an alarm to medical staff, are triggered only when the ECG signal amplitude exceeds a preset threshold and the AI ​​analysis indicates the presence of a PVC.

[0164] In other alternative implementations, the neural network inference accelerator can employ different hardware architectures, such as GPU (Graphics Processing Unit)-based or ASIC (Application-Specific Integrated Circuit)-based accelerator cards. The neural network model can also be of different types, such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), or Transformer models, to adapt to different types of data streams and recognition tasks. The AI ​​analysis result signal can also be multi-bit, representing different confidence levels or multiple event types.

[0165] Through the above solution, this embodiment can integrate the real-time analysis capabilities of artificial intelligence into the hardware triggering decision chain, realize intelligent scene triggering based on complex pattern recognition, and expand the application scenarios and automation level of the system.

[0166] In one specific implementation, based on the above embodiments, the main control card of the central control unit M300 uses an STM32H7 series high-performance microcontroller from STMicroelectronics as the management processor (MCU). This MCU has an integrated ARM Cortex-M7 core with a clock speed of up to 480MHz, providing ample computing power and rich peripheral interfaces. Simultaneously, a Xilinx Artix-7 series FPGA is selected as the reconfigurable hardware actuator. This FPGA has medium-sized logic resources, sufficient to implement the reconfigurable event logic execution engine (RELE) and other necessary hardware acceleration modules.

[0167] The MCU connects to the FPGA via a high-speed parallel interface (such as FSMC or bus) to enable rapid configuration parameter delivery and status information retrieval. The MCU runs a real-time operating system such as FreeRTOS, providing a graphical user interface (GUI), parsing complex user-defined triggering logic, and translating high-level logic into low-level hardware configuration parameters. These parameters include the threshold of the RELE internal comparator array, the connection relationships of the programmable logic matrix, and the configuration of the output action mapping unit. The MCU then writes these configuration parameters into the FPGA's internal configuration registers, thereby dynamically configuring RELE's behavior.

[0168] The FPGA handles all timing-critical high-speed parallel I / O and logic checks. It connects directly to each I / O module via a high-speed data bus, acquiring input signals in real time, executing logic checks in the RELE loop, and precisely controlling the timing of output signals when trigger conditions are met. Because all these operations are executed in parallel at the FPGA hardware level, sub-microsecond response speeds and synchronization accuracy can be achieved.

[0169] In other alternative implementations, the MCU can be selected from other brands or models of microcontrollers, such as the NXP i.MX RT series or the Microchip SAM series. The FPGA can also be selected from other series or models, such as the Xilinx Spartan series or the Intel Cyclone series. The connection between the MCU and the FPGA can also be achieved using other high-speed interfaces, such as Ethernet, USB, or PCIe.

[0170] Through the above scheme, this embodiment can clarify the specific selection of the management processor and reconfigurable hardware actuator in the central control unit M300, and further explain the hardware connection and data interaction method for the two to work together to complete complex triggering tasks.

[0171] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A modular synchronous triggering method with a reconfigurable hardware logic engine, characterized in that, include: The management processor receives user-defined event triggering logic and generates hardware configuration parameters based on the event triggering logic. The management processor sends the hardware configuration parameters to the reconfigurable hardware executor to configure the event logic execution engine integrated within the reconfigurable hardware executor; The configured event logic execution engine monitors in real time and in parallel one or more sources of multimodal input signals containing at least one of the following signal types through input / output units: digital pulse signals, analog data signals, audio and video data streams, software communication data packets, and user operation information; At the hardware level, the event logic execution engine compares and judges the multimodal input signal with the event triggering logic, and generates a comparison and judgment result. When the comparison result satisfies the event triggering logic, the input / output unit generates and sends a multimodal output signal containing at least one of the following signal types to an external device: a digital pulse signal, an analog control signal, and a software control command for controlling the external device.

2. The method according to claim 1, characterized in that, The method is applied in the field of clinical medical research, and the external equipment includes at least one of a motion capture system, a force table, an electromyography / electroencephalography acquisition device, and medical imaging equipment.

3. The method according to claim 1, characterized in that, The event triggering logic includes level triggering logic, which is configured to trigger the generation or cessation of the multimodal output signal when the amplitude of the analog data signal in the multimodal input signal meets a preset threshold condition.

4. The method according to claim 3, characterized in that, The level-triggered logic also includes a time limit, which is configured to stop the generation of the multimodal output signal after the amplitude meets the threshold condition and continues for a preset time t.

5. The method according to claim 1, characterized in that, The event triggering logic includes edge triggering logic, which is configured to trigger the generation or cessation of the multimodal output signal when a rising edge or falling edge of the digital pulse signal in the multimodal input signal is detected.

6. The method according to claim 1, characterized in that, The event triggering logic includes instruction triggering logic, which is configured to trigger the generation of the multimodal output signal when the software communication data packet in the multimodal input signal is received and parsed, and it is confirmed that it contains a preset instruction code.

7. The method according to claim 1, characterized in that, The event triggering logic includes data triggering logic, which is configured to: perform real-time calculation on the data of the received multimodal input signal to obtain a triggering index, and trigger the generation of the multimodal output signal when the triggering index meets a preset condition.

8. The method according to claim 1, characterized in that, The step of real-time parallel monitoring of multimodal input signals further includes: The real-time data stream from the multimodal input signal is input into a hardware-implemented neural network inference accelerator for real-time inference, so as to output an AI analysis result signal. The event logic execution engine monitors and compares the AI ​​analysis result signal as part of the multimodal input signal.

9. The method according to claim 1, characterized in that, The steps for configuring the event logic execution engine include: Using the aforementioned hardware configuration parameters, configure the parallel comparator array and programmable logic matrix within the event logic execution engine.

10. A modular synchronous triggering system with a reconfigurable hardware logic engine, characterized in that, include: A host unit, wherein a standard interface slot is provided on the host unit; An input / output unit that is pluggably mounted in the standard interface slot is configured to interact with an external device via multimodal signals, the multimodal signals including multimodal input signals and multimodal output signals; A central control unit, electrically connected to the standard interface slot, and comprising: A management processor is configured to receive user-defined event triggering logic and generate hardware configuration parameters based on the event triggering logic. A reconfigurable hardware executor, wherein the reconfigurable hardware executor integrates an event logic execution engine, and the reconfigurable hardware executor is configured to: The system receives the hardware configuration parameters sent by the management processor to configure the event logic execution engine. The configured event logic execution engine, at the hardware level, compares and judges the multi-mode input signal, which includes at least one of digital pulse signals, analog data signals, audio and video data streams, software communication data packets, and user operation information, input through the input / output unit, with the event triggering logic, and generates a comparison and judgment result. Furthermore, when the comparison judgment result satisfies the event triggering logic, the input / output unit generates and sends the multimodal output signal containing at least one of digital pulse signals, analog control signals, and software control instructions to the external device.

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