Information code processor, memory and operating method thereof

Abstract

The invention relates to an information code processor, a memory and an operating method thereof. An information code processor may include: a first sampling circuit configured to sample an information code at a first point in time to generate a first sampled code; a second sampling circuit configured to sample the information code at a second time point after the first time point to generate a second sampling code; and a processing circuit configured to generate a processing code using the first sampling code, the second sampling code, and the previously generated pre-processing code.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0136568, filed on October 8, 2024, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Various embodiments of the present disclosure relate to integrated circuits, and more particularly, to a memory and an information code processor for processing an information code including internal information of an integrated circuit such as a memory. BACKGROUND

[0003] Since various integrated circuits contain a large number of transistors, their electrical characteristics can vary depending on the operating temperature. For example, in a memory such as a DRAM, the data retention time varies depending on the temperature, and thus temperature information is exchanged between the memory and a memory controller to adjust the refresh period according to the temperature.

[0004] In a case where temperature information generated by a temperature sensing circuit included in an integrated circuit is output outside the integrated circuit, when the time when the temperature information is updated overlaps with the time when the temperature information is output, a glitch can occur, and the temperature information can be changed and output due to various other factors. Therefore, a technology for stably processing and outputting temperature information generated in an integrated circuit is needed. SUMMARY

[0005] According to an embodiment of the present disclosure, an information code processor can include a first sampling circuit configured to sample an information code at a first time point to generate a first sample code, a second sampling circuit configured to sample the information code at a second time point after the first time point to generate a second sample code, and a processing circuit configured to generate a processed code using the first sample code, the second sample code, and a previously generated pre-processed code.

[0006] According to an embodiment of the present disclosure, a memory can include a temperature sensing circuit configured to generate an information code indicating a temperature, a command decoder configured to decode a command and an address to generate a temperature read signal, a first sampling circuit configured to sample the information code at a first time point in response to the temperature read signal to generate a first sample code, a second sampling circuit configured to sample the information code at a second time point after the first time point in response to the temperature read signal to generate a second sample code, a processing circuit configured to generate a processed code using the first sample code, the second sample code, and a previously generated pre-processed code, and a transmitting circuit configured to transmit the processed code.

[0007] According to an embodiment of the disclosure, a method of operating a memory can include generating an information code indicating a temperature, decoding a command and an address to generate a temperature read signal, sampling the information code at a first time point to generate a first sample code in response to the temperature read signal, sampling the information code at a second time point after the first time point to generate a second sample code in response to the temperature read signal, and generating a process code based on the first sample code, the second sample code, and a pre-processed code generated earlier to transmit the process code to the outside. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a memory according to an embodiment of the disclosure.

[0009] Figure 2 is a block diagram illustrating Figure 1 an embodiment of the information code processor illustrated in

[0010] Figure 3 is a block diagram illustrating Figure 2 an embodiment of the processing circuit illustrated in

[0011] Figure 4 is a block diagram illustrating Figure 1 another embodiment of the information code processor illustrated in

[0012] Figure 5 is a block diagram illustrating Figure 4 an embodiment of the code correction circuit illustrated in DETAILED DESCRIPTION

[0013] Various embodiments of the disclosure relate to a technology of stably processing an information code generated by an integrated circuit.

[0014] According to an embodiment of the disclosure, an information code generated by an integrated circuit can be stably processed and the processed information code can be output to the outside of the integrated circuit.

[0015] Various embodiments according to the technical spirit of the disclosure will be described below with reference to the accompanying drawings.

[0016] Figure 1 is a block diagram illustrating a memory 100 according to an embodiment of the disclosure.

[0017] Referring to Figure 1 , the memory 100 can include a command address receiving circuit 101, a data receiving circuit 103, a data transmitting circuit 105, a command decoder 110, an address control circuit 120, a memory core 130, a temperature sensing circuit 140, and an information code processor 150.

[0018] The command address receiving circuit 101 can receive a command and address CA. The command and address CA can be input through the same input terminal or can be input through separate input terminals according to the specification of the memory 100. Here, an example in which the command and address CA are input through the same input terminal is described. The command and address CA can have a plurality of bits.

[0019] The data receiving circuit 103 can receive data DATA, and the data transmitting circuit 105 can transmit the data DATA. During a write operation, the data receiving circuit 103 can receive data DATA to be written into the memory core 130, and during a read operation, the data transmitting circuit 105 can transmit data DATA read from the memory core 130.

[0020] The command decoder 110 can decode the command and address CA and find out the type of operation that the memory controller instructs the memory 100 to perform. The activation signal ACT can be activated when an activation operation is instructed, the precharge signal PCG can be activated when a precharge operation is instructed, and the refresh signal REF can be activated when a refresh operation is instructed. The write signal WR can be activated when a write operation is instructed, and the read signal RD can be activated when a read operation is instructed. In addition, the temperature read signal TEMP_RD can be activated when a request for temperature information of the memory 100 is made from the memory controller.

[0021] The address control circuit 120 can classify the address received from the command decoder 110 as a row address R_ADD and a column address C_ADD and transfer the address to the memory core 130. The address control circuit 120 can classify the address as a row address R_ADD when an activation operation is instructed as a result of decoding by the command decoder 110, and can classify the address as a column address C_ADD when a read / write operation is instructed as a result of decoding by the command decoder 110.

[0022] The memory core 130 can perform operations instructed by the signals ACT, PCG, RD, WR, and REF. The memory core 130 can include components for activation, precharge, read, write, and refresh operations, such as a cell array including memory cells arranged in a plurality of rows and a plurality of columns, a row decoder for activating / deactivating rows of the cell array, a column decoder for inputting / outputting data from / to the cell array, and input / output circuits.

[0023] The temperature sensing circuit 140 can sense the internal temperature of the memory 100 to generate an information code TEMP_CODE<0:2>.

[0024] The information code processor 150 can process the information code TEMP_CODE<0:2> in response to the temperature read signal TEMP_RD to generate a processed code TEMP_VALID<0:2>. The temperature sensing circuit 140 can operate in synchronization with a periodic wave generated by an oscillator (not shown) included in the memory 100, and the temperature read signal TEMP_RD can be activated in synchronization with a clock (not shown) applied from outside the memory 100. When the temperature read signal TEMP_RD is activated while the temperature sensing circuit 140 updates or changes the information code TEMP_CODE<0:2>, the value of the information code TEMP_CODE<0:2> can not be correctly transmitted. In addition, glitches can occur in the value of the information code TEMP_CODE<0:2> due to a variety of other reasons, and the information code processor 150 can process the information code TEMP_CODE<0:2> so that the value of the information code TEMP_CODE<0:2> can be stably and error-free output to the outside of the memory 100.

[0025] The processed code TEMP_VALID<0:2> obtained through the processing of the information code processor 150 can be transmitted to the memory controller by the data transmission circuit 105. Here, it is shown that the processed code TEMP_VALID<0:2> is transmitted to the memory controller by the data transmission circuit 105, but according to the design, a separate transmission circuit can also be provided to transmit the processed code TEMP_VALID<0:2> to the memory controller.

[0026] Figure 2 For Figure 1 a block diagram of an embodiment of the information code processor 150 shown.

[0027] Referring to Figure 2 , the information code processor 150 can include a first sampling circuit 210, a second sampling circuit 220, a processing circuit 230, and delay circuits 241 to 243.

[0028] The first sampling circuit 210 can sample the information code TEMP_CODE<0:2> when the temperature read signal TEMP_RD is activated. The first sampling circuit 210 can include D flip-flops 211 and 212. The D flip-flop 211 receives and stores the information code TEMP_CODE<0:2> at the activation time of the temperature read signal TEMP_RD. When the activation time of the temperature read signal TEMP_RD coincides with the time at which the information code TEMP_CODE<0:2> changes or is updated, the internal node and the output value of the D flip-flop 211 can become unstable and fall into a metastable state. For this reason, the D flip-flop 212 is provided. In response to the activation of the temperature read signal TEMP_RD_D1 obtained by delaying the temperature read signal TEMP_RD by the delay circuit 241, the D flip-flop 212 samples and stores the output of the D flip-flop 211 again to output the result as the first sampled code TEMP1<0:2>.

[0029] The second sampling circuit 220 samples the information code TEMP_CODE<0:2> at a time later than the sampling time of the first sampling circuit 210, i.e., when the temperature read signal TEMP_RD_D1 is activated. The D flip-flop 221 receives and stores the information code TEMP_CODE<0:2> at the activation time of the temperature read signal TEMP_RD_D1. When the temperature read signal TEMP_RD_D2 obtained by further delaying the temperature read signal TEMP_RD_D1 by the delay circuit 242 is activated, the D flip-flop 222 samples and stores the output of the D flip-flop 221 again and outputs the result as the second sampled code TEMP2<0:2>.

[0030] The processing circuit 230 can generate the processing code TEMP_VALID<0:2> using the first sampled code TEMP1<0:2>, the second sampled code TEMP2<0:2>, and a pre-processed code PRE_TEMP<0:2> generated in advance. The pre-processed code PRE_TEMP<0:2> can be a processing code generated in advance by the processing circuit 230. When the temperature read signal TEMP_RD_D3 obtained by delaying the temperature read signal TEMP_RD_D2 by the delay circuit 243 is activated, the D flip-flop 231 can sample the processing code TEMP_VALID<0:2> as the output of the processing circuit 230 to generate the pre-processed code PRE_TEMP<0:2>.

[0031] The processing circuit 230 can generate the processing code TEMP_VALID<0:2> having a stable value through the following processing.

[0032] (1) In the case where the value of the first sampled code TEMP1<0:2> is equal to the value of the second sampled code TEMP2<0:2> When the value of the first sampled code TEMP1<0:2> is equal to the value of the second sampled code TEMP2<0:2>, in a case where the two sampled codes are sampled with a slight time difference, it can be determined that the values of the sampled codes have no error. Therefore, in this case, the processing code TEMP_VALID<0:2> can be generated to have the same value as the first sampled code TEMP1<0:2>.

[0033] (2) In a case where the value of the first sampled code TEMP1<0:2> is different from the value of the second sampled code TEMP2<0:2> When the value of the first sampled code TEMP1<0:2> is different from the value of the second sampled code TEMP2<0:2>, in a case where the two sampled codes are sampled with a slight time difference, both the first sampled code TEMP1<0:2> and the second sampled code TEMP2<0:2> are unreliable. Therefore, the processing circuit 230 can generate the processing code TEMP_VALID<0:2> as described in (2-1), (2-2), and (2-3) below.

[0034] (2-1) In a case where the values of the first sampled code TEMP1<0:2> and the second sampled code TEMP2<0:2> are smaller than the value of the pre-processing code PRE_TEMP<0:2> In this case, it can be determined that the value of the information code TEMP_CODE<0:2> becomes smaller than the pre-processing code PRE_TEMP<0:2> which is the preceding value. Therefore, the processing circuit 230 can generate the processing code TEMP_VALID<0:2> having a value obtained by subtracting a predetermined first value (for example, "1") from the value of the pre-processing code PRE_TEMP<0:2>.

[0035] (2-2) In a case where the values of the first sampled code TEMP1<0:2> and the second sampled code TEMP2<0:2> are larger than the value of the pre-processing code PRE_TEMP<0:2> In this case, it can be determined that the value of the information code TEMP_CODE<0:2> becomes larger than the pre-processing code PRE_TEMP<0:2> which is the preceding value. Therefore, the processing circuit 230 can generate the processing code TEMP_VALID<0:2> having a value obtained by adding a predetermined second value (for example, "1") to the value of the pre-processing code PRE_TEMP<0:2>.

[0036] (2-3) In a case where the values of the first sampled code TEMP1<0:2> and the second sampled code TEMP2<0:2> are different and do not belong to the cases (2-1) and (2-2) In this case, the values of the first sample code TEMP1<0:2> and the second sample code TEMP2<0:2> are unreliable. Therefore, the processing circuit 230 can generate the processing code TEMP_VALID<0:2> having the same value as the value of the pre-processing code PRE_TEMP<0:2>.

[0037] Since the number of bits of the illustrated information code TEMP_CODE<0:2> is 3 bits, the number of each of the D flip-flops 211, 212, 221, 222, and 231 can be 3, and the number of each of the D flip-flops can vary when the number of bits of the information code varies.

[0038] Further, although the final output of the information code processor 150 is illustrated as the processing code TEMP_VALID<0:2>, the final output of the information code processor 150 can also be the pre-processing code PRE_TEMP<0:2>. Since the pre-processing code PRE_TEMP<0:2> is a code obtained by sampling the processing code TEMP_VALID<0:2> by the D flip-flop 231, as long as the processing code TEMP_VALID<0:2> is updated, the pre-processing code PRE_TEMP<0:2> can be generated with the same value.

[0039] Figure 3 is a block diagram illustrating Figure 2 the processing circuit 230.

[0040] Referring to Figure 3 , the processing circuit 230 can include a first subtraction circuit 310, a second subtraction circuit 320, a comparison circuit 330, a logic operation unit 340, an operation circuit 370, and a selection circuit 380.

[0041] The first subtraction circuit 310 can subtract the value of the pre-processing code PRE_TEMP<0:2> from the value of the first sample code TEMP1<0:2> to generate a first subtraction result DELT_TEMP1<0:2> and a first borrow signal BO_TEMP1. When the value of the first sample code TEMP1<0:2> is greater than the value of the pre-processing code PRE_TEMP<0:2>, the first subtraction result DELT_TEMP1<0:2> has a value other than "000", and the first borrow signal BO_TEMP1 is deactivated. Further, when the value of the first sample code TEMP1<0:2> is less than the value of the pre-processing code PRE_TEMP<0:2>, the first borrow signal BO_TEMP1 is activated to "1".

[0042] The second subtraction circuit 320 can subtract the value of the pre-processing code PRE_TEMP<0:2> from the value of the second sample code TEMP2<0:2> to generate a second subtraction result DELT_TEMP2<0:2> and a second borrow signal BO_TEMP2. When the value of the second sample code TEMP2<0:2> is greater than the value of the pre-processing code PRE_TEMP<0:2>, the second subtraction result DELT_TEMP2<0:2> has a value other than "000" and the second borrow signal BO_TEMP2 is deactivated. Also, when the value of the second sample code TEMP2<0:2> is less than the value of the pre-processing code PRE_TEMP<0:2>, the second borrow signal BO_TEMP2 is activated to "1".

[0043] The comparison circuit 330 can compare the value of the first sample code TEMP1<0:2> with the value of the second sample code TEMP2<0:2> to generate an equal signal EQUAL. When the values of the two codes TEMP1<0:2> and TEMP2<0:2> are equal to each other, the equal signal EQUAL can be activated to "1".

[0044] The logic operation unit 340 can perform a logic operation on the first subtraction result DELT_TEMP1<0:2>, the first borrow signal BO_TEMP1, the second subtraction result DELT_TEMP2<0:2>, and the second borrow signal BO_TEMP2 to generate an increase signal INC and a decrease signal DEC.

[0045] The logic operation unit 340 can include NOR gates 341 and 348, inverters 342, 343, 345, 347, 349, 350, 352, and 354, and NAND gates 344, 346, 351, and 353. When the first subtraction result DELT_TEMP1<0:2> is not "000" and the first borrow signal BO_TEMP1 is deactivated to "0", i.e., when the value of the first sample code TEMP1<0:2> is greater than the value of the pre-processing code PRE_TEMP<0:2>, the first increase signal INC_1 is activated to "1". When the second subtraction result DELT_TEMP2<0:2> is not "000" and the second borrow signal BO_TEMP2 is deactivated to "0", i.e., when the value of the second sample code TEMP2<0:2> is greater than the value of the pre-processing code PRE_TEMP<0:2>, the second increase signal INC_2 is activated to "1". Also, when both the first increase signal INC_1 and the second increase signal INC_2 are activated, the increase signal INC is activated to "1".

[0046] When both the first borrow signal BO_TEMP1 and the second borrow signal BO_TEMP2 are activated to "1", that is, when the value of the first sample code TEMP1<0:2> is smaller than the value of the pre-processing code PRE_TEMP<0:2> and the value of the second sample code TEMP2<0:2> is smaller than the value of the pre-processing code PRE_TEMP<0:2>, the decrease signal DEC is activated.

[0047] When the decrease signal DEC is activated, the operation circuit 370 can output a value obtained by subtracting a predetermined first value (e.g., "1") from the value of the pre-processing code PRE_TEMP<0:2>, and when the increase signal INC is activated, the operation circuit 370 can output a value obtained by adding a predetermined second value (e.g., "1") to the value of the pre-processing code PRE_TEMP<0:2>.

[0048] The operation circuit 370 can include a selection circuit 371 and an addition circuit 372. The selection circuit 371 can select and output "000" when both the increase signal INC and the decrease signal DEC are deactivated, "001" when the increase signal INC is activated, and "111" when the decrease signal DEC is activated. The addition circuit 372 can add the value of the pre-processing code PRE_TEMP<0:2> to the output value of the selection circuit 371 to output a result value. Thus, the output value of the addition circuit 372 can be output as a value equal to the value of the pre-processing code PRE_TEMP<0:2>, a value obtained by adding "1" to the value of the pre-processing code PRE_TEMP<0:2>, or a value obtained by subtracting "1" from the value of the pre-processing code PRE_TEMP<0:2>. For reference, a value obtained by adding "111" to the value of a code can be equal to a value obtained by subtracting "1" from the value of the code.

[0049] The selection circuit 380 can select the first sample code TEMP1<0:2> when the equal signal EQUAL is activated to "1" and output the selected code as the processing code TEMP_VALID<0:2>, and select the output value of the operation circuit 370 when the equal signal EQUAL is deactivated to "0" and output the selected value as the processing code TEMP_VALID<0:2>.

[0050] Having reference Figure 3 The processing circuit 230 of the described configuration can operate in the same manner as in the cases (1), (2-1), (2-2), and (2-3) described above.

[0051] Figure 4 is a block diagram illustrating Figure 1 Another embodiment of the information code processor 150 shown in FIG. 1.

[0052] Figure 4 The information code processor 150 shown Figure 2 may further include code correction circuits 410, 420, and 430, compared to the information code processor 150 shown in

[0053] When the value of the first sample code TEMP1<0:2> deviates from a specified criterion, the code correction circuit 410 can correct the value of the first sample code TEMP1<0:2> to a value within the specified criterion to output the corrected value. When the value of the second sample code TEMP2<0:2> deviates from a specified criterion, the code correction circuit 420 can correct the value of the second sample code TEMP2<0:2> to a value within the specified criterion to output the corrected value. Similarly, when the value of the processing code TEMP_VALID<0:2> deviates from a specified criterion, the code correction circuit 430 can correct the value of the processing code TEMP_VALID<0:2> to a value within the specified criterion to output the corrected value. The output TEMP_VALID_CORR<0:2> of the code correction circuit 430 can be the final output of the information code processor 150.

[0054] Table 1 represents an example of a specified criterion for the information code TEMP_CODE<0:2>.

[0055] [Table 1] TEMP_CODE<0:2> Temperature 000 Not defined 001 Below 80 °C 010 80℃-85℃ 011 85℃-90℃ 100 90℃-95℃ 101 Above 95 °C 110 Not defined 111 Not defined When the value of the information code TEMP_CODE<0:2> is 001 to 101, Table 1 indicates information about temperature. However, when the value of the information code TEMP_CODE<0:2> is 000, 110, or 111, temperature is not defined. When the value of the information code TEMP_CODE<0:2> is 000, 110, or 111, it can be seen that temperature has a value other than the specified criterion, i.e., an error.

[0056] When the input code value deviates from the specified criterion, the code correction circuits 410, 420, and 430 can correct the input code value to a code value that conforms to the closest criterion. Since it is important that the value of the final output code TEMP_VALID_CORR<0:2> of the information code processor 150 conforms to the criterion, the code correction circuit 430 can be the most important among the code correction circuits 410, 420, and 430. That is, the code correction circuits 410 and 420 can be omitted, and only the code correction circuit 430 can be provided.

[0057] Figure 5 is a block diagram illustrating an embodiment of the code correction circuit 430 shown in Figure 4 . The other code correction circuits 410 and 420 can have the same configuration as the code correction circuit 430 shown in Figure 5 .

[0058] Referring to Figure 5 , the code correction circuit 430 can include NAND gates 501 and 503, NAND gates 502 and 505, and inverters 504, 506, 507, and 508.

[0059] When the value of the processing code TEMP_VALID<1:2> is "00", the value of the output code TEMP_VALID_CORR<0> can be fixed to "1" regardless of the value of the processing code TEMP_VALID<0>. Thus, when the value of the processing code TEMP_VALID<0:2> is "000", the value of the output code TEMP_VALID_CORR<0:2> can be "001". That is, the code value of "000" that does not meet the standard can be corrected to "001".

[0060] When the value of the processing code TEMP_VALID<1:2> is "11", the value of the output code TEMP_VALID_CORR<1> can be fixed to "0" regardless of the value of the processing code TEMP_VALID<1>. Thus, when the value of the processing code TEMP_VALID<0:2> is "110", the value of the output code TEMP_VALID_CORR<0:2> can be "100". Also, when the value of the processing code TEMP_VALID<0:2> is "111", the value of the output code TEMP_VALID_CORR<0:2> can be "101". That is, the code value of "110" that does not meet the standard can be corrected to "100", and the code value of "111" that does not meet the standard can be corrected to "101".

[0061] Although it is described according to the above-described embodiment that the information code processor 150 processes the information code including the temperature information, the information code processor 150 can also be used to process the information code including other information than the temperature information.

[0062] Although the technical spirit of the present disclosure has been described above according to the embodiments, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above-described embodiments. Those skilled in the art to which the present disclosure pertains can apply various embodiments within the scope of the technical spirit of the present disclosure. Also, the embodiments can be combined to form additional embodiments.

Claims

1. An information code processor comprising: a first sampling circuit that samples an information code at a first time point to generate a first sample code; a second sampling circuit that samples the information code at a second time point after the first time point to generate a second sample code; and a processing circuit that generates a processed code based on the first sample code, the second sample code, and a previously generated pre-processed code. the processing circuit generates the first sample code as the processed code when a value of the first sample code is equal to a value of the second sample code.

2. The information code processor of claim 1, wherein, the processing circuit generates the processed code having a value obtained by subtracting a predetermined first value from the value of the pre-processed code when the value of the first sample code is different from the value of the second sample code and the values of the first sample code and the second sample code are both smaller than the value of the pre-processed code.

3. The information code processor of claim 2, wherein, the processing circuit generates the processed code having a value obtained by adding a predetermined second value to the value of the pre-processed code when the value of the first sample code is different from the value of the second sample code and the values of the first sample code and the second sample code are both larger than the value of the pre-processed code.

4. The information code processor of claim 3, wherein, the processing circuit generates the processed code having the same value as the value of the pre-processed code when the value of the first sample code is different from the value of the second sample code and neither the value of the first sample code nor the value of the second sample code is smaller than the value of the pre-processed code or neither the value of the first sample code nor the value of the second sample code is larger than the value of the pre-processed code.

5. The information code processor of claim 4, wherein, 6. The information code processor according to claim 1, further comprising a first code correction circuit that corrects the value of the processed code to a value within a specified criterion when the value of the processed code deviates from the specified criterion.

7. The information code processor according to claim 6, further comprising: a second code correction circuit that corrects the value of the first sample code to the value within the specified criterion when the value of the first sample code deviates from the specified criterion, and transmits the corrected value to the processing circuit; and a third code correction circuit that corrects the value of the second sample code to the value within the specified criterion when the value of the second sample code deviates from the specified criterion, and transmits the corrected value to the processing circuit. the processing circuit includes:

8. The information code processor of claim 1, wherein, a first subtraction circuit that subtracts the value of the pre-processed code from the value of the first sample code to generate a first subtraction result and a first borrow signal; a second subtraction circuit that subtracts the value of the pre-processed code from the value of the second sample code to generate a second subtraction result and a second borrow signal; a comparison circuit that compares the value of the first sample code with the value of the second sample code to generate an equality signal; a logic operation unit that logically operates the first subtraction result, the first borrow signal, the second subtraction result, and the second borrow signal to generate an increase signal and a decrease signal; and a selection circuit that selects one of the increase signal and the decrease signal based on the equality signal to generate the processed code. an operation circuit that: outputs a value obtained by subtracting a predetermined first value from the value of the preprocessed code when the decrease signal is activated; outputs a value obtained by adding a predetermined second value to the value of the preprocessed code when the increase signal is activated; and outputs the value of the preprocessed code when the increase signal and the decrease signal are deactivated; and a selection circuit that: selects the output code of the operation circuit to output the selected code as the processed code when the equality signal is deactivated; and selects the first sample code to output the selected code as the processed code when the equality signal is activated.

9. The information code processor of claim 8, wherein, the logic operation unit that: activates the decrease signal when the first borrow signal and the second borrow signal are activated; and activates the increase signal when the first borrow signal and the second borrow signal are deactivated and the first subtraction result and the second subtraction result are not "0".

10. A memory, comprising: a temperature sensing circuit that generates an information code indicative of a temperature; a command decoder that decodes a command with an address to generate a temperature read signal; a first sampling circuit that: samples the information code at a first time point in response to the temperature read signal to generate a first sample code; a second sampling circuit that: samples the information code at a second time point after the first time point in response to the temperature read signal to generate a second sample code; a processing circuit that generates a processed code based on the first sample code, the second sample code, and a preprocessed code generated earlier; and a transmission circuit that transmits the processed code to the outside.

11. The memory of claim 10, wherein, the processing circuit that generates the first sample code as the processed code when a value of the first sample code is equal to a value of the second sample code.

12. The memory of claim 11, wherein, the processing circuit that generates the processed code having a value obtained by subtracting a predetermined first value from the value of the preprocessed code when the value of the first sample code is different from the value of the second sample code and the values of the first sample code and the second sample code are both smaller than the value of the preprocessed code.

13. The memory of claim 12, wherein, the processing circuit that generates the processed code having a value obtained by adding a predetermined second value to the value of the preprocessed code when the value of the first sample code is different from the value of the second sample code and the values of the first sample code and the second sample code are both larger than the value of the preprocessed code.

14. The memory of claim 13, wherein, the processing circuit that generates the processed code having the same value as the value of the preprocessed code when the value of the first sample code is different from the value of the second sample code and neither the value of the first sample code nor the value of the second sample code is smaller than the value of the preprocessed code or neither the value of the first sample code nor the value of the second sample code is larger than the value of the preprocessed code.

15. The memory according to claim 10, further comprising a first code correction circuit that corrects the value of the processed code to a value within a specified criterion when the value of the processed code deviates from the specified criterion.

16. The memory of claim 15, further comprising: a second code correction circuit that, when a value of the first sample code deviates from the specified criteria, corrects the value of the first sample code to be within the specified criteria and transmits the corrected value to the processing circuit; and a third code correction circuit that, when a value of the second sample code deviates from the specified criteria, corrects the value of the second sample code to be within the specified criteria and transmits the corrected value to the processing circuit.

17. A method of operating a memory, the method comprising: generating an information code indicative of temperature; decoding a command and address to generate a temperature read signal; sampling the information code at a first point in time in response to the temperature read signal to generate a first sample code; sampling the information code at a second point in time after the first point in time in response to the temperature read signal to generate a second sample code; and generating a processing code based on the first sample code, the second sample code, and a previously generated pre-processing code to send the processing code externally. correcting the value of the processing code to be within a specified criteria when the value of the processing code deviates from the specified criteria.

18. The method of claim 17, further comprising:

19. The method of claim 18, further comprising: correcting a value of the first sample code to be within the specified criteria when the value of the first sample code deviates from the specified criteria and transmitting the corrected value to the processing circuit; and correcting the value of the second sample code to be within the specified criteria when the value of the second sample code deviates from the specified criteria and transmitting the corrected value to the processing circuit. ​ ​

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