Read-write control system and method based on single clock domain SRAM (Static Random Access Memory)

Abstract

The invention provides a read-write control system and method based on a single clock domain SRAM (Static Random Access Memory). The read-write control system comprises an SRAM control module, an odd SRAM module, an even SRAM module, an odd-even data selection module and an FIFO (First In First Out) module. Comprising the following steps: setting an SRAM read-write mode and an SRAM clock frequency division factor n; and based on the SRAM read-write mode and the SRAM clock frequency division factor n, using a single port to read and write the SRAM. The single-clock-domain SRAM has the advantages that the single-clock-domain SRAM is smaller in use area, lower in power consumption and lower in cost, the odd SRAM module and the even SRAM module are designed, and the function of reading and writing at the same time is achieved; the SRAM control module is designed to realize special SRAM control, so that the memory can simultaneously read and write in a first-in and second-out mode; an odd-even selection module and a matched FIFO (First In First Out) are designed, so that the memory can carry out 1 / n-time frequency reduction on a data stream; and the complexity caused by multiple clock domains is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of digital integrated circuits, and particularly relates to a read-write control system and method based on single-clock-domain SRAM. BACKGROUND

[0002] With the increasing requirements of digital circuits for SRAM, the application scenarios of SRAM with simultaneous read and write are more and more, and generally, dual-clock-domain (dual-port) SRAM is selected when there is a simultaneous read and write requirement. Compared with single-clock-domain (single-port) SRAM, dual-clock-domain SRAM has a wider application range. This type of SRAM contains two bidirectional I / O buses, and each port supports a completely independent clock domain. However, most of the current dual-clock-domain SRAMs adopt 8-tube storage units, and compared with the traditional single-clock-domain SRAMs which adopt 6-tube storage units, two more gate tubes and a set of bit lines are added. At the same time, due to the irregularity of the layout connection, the actual area of the dual-clock-domain SRAM is much larger than that of the single-clock-domain SRAM. Moreover, the use of more devices to realize storage in the dual-clock-domain SRAM leads to relatively high power consumption. The dual-clock-domain SRAM itself has a cross-clock-domain operation, which leads to more complex design work and timing analysis, and there is a hidden danger of causing timing mismatch, such as metastability, which is not conducive to implementation and debugging; at the same time, the delay of data transmission is high, which is not conducive to improving the overall performance of the system, and is particularly unsuitable for application in high-speed transmission. As for the cost, the IP price of the dual-clock-domain SRAM is also much higher, and some special process conditions do not support the dual-clock-domain SRAM. SUMMARY

[0003] Therefore, the present application aims to provide a read-write control system and method based on single-clock-domain SRAM to solve the problems that the traditional single-port SRAM cannot simultaneously read and write, and the traditional single-clock-domain SRAM cannot change the clock frequency of read data.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows: In a first aspect, the present application provides a read-write control system based on single-clock-domain SRAM, which comprises an SRAM control module, an odd SRAM module, an even SRAM module, an odd-even data selection module and a FIFO module. The SRAM control module is connected with the odd SRAM module and the even SRAM module through signal lines, the odd SRAM module and the even SRAM module are connected with the odd-even data selection module through signal lines, the odd-even data selection module is connected with the FIFO module through signal lines, and the FIFO module is connected with external equipment through signal lines. The signal lines connecting the SRAM control module and the odd SRAM module include an odd SRAM chip selection signal line, an odd SRAM write enable signal line, an odd SRAM address signal line, and an odd SRAM data input signal line; The signal lines connecting the SRAM control module and the even SRAM module include an even SRAM chip selection signal line, an even SRAM write enable signal line, an even SRAM address signal line, and an even SRAM data input signal line; The signal lines connecting the odd SRAM module and the odd-even data selection module include an odd SRAM data output signal line; The signal lines connecting the even SRAM module and the odd-even data selection module include an even SRAM data output signal line; The signal lines connecting the odd-even data selection module and the FIFO module include an SRAM data output signal line; The signal lines connecting the FIFO module and the external device include a data output signal line.

[0005] Further, the odd SRAM data input signal line, the even SRAM data input signal line, the odd SRAM data output signal line, the even SRAM data output signal line, and the SRAM data output signal line are all synchronized with the SRAM clock CLK.

[0006] Further, the data output signal line is synchronized with the SRAM clock CLK divided by 1 / n, where n is an SRAM clock division factor, which is a positive integer.

[0007] Further, the SRAM control module is configured to receive original input data and send chip selection, write enable, address, and data input instructions to the odd SRAM module and the even SRAM module; The odd SRAM module and the even SRAM module are configured to serve as single-clock-domain SRAMs without redundant storage depth, and alternately perform read and write operations; The odd-even data selection module is configured to splice the data output by the odd SRAM module and the even SRAM module into complete SRAM data; The FIFO module is configured to buffer data and synchronize the output data stream to the SRAM clock CLK divided by 1 / n.

[0008] Further, the odd SRAM chip selection signal line is configured to transmit an odd SRAM chip selection signal; and the even SRAM chip selection signal line is configured to transmit an even SRAM chip selection signal; The odd SRAM write enable signal line is configured to transmit an odd SRAM write enable signal; and the even SRAM write enable signal line is configured to transmit an even SRAM write enable signal; The odd SRAM address signal line is used to transmit the odd SRAM address signal; the even SRAM address signal line is used to transmit the even SRAM address signal. The odd SRAM data input signal line is used to input odd SRAM data signals; the even SRAM data input signal line is used to input even SRAM data signals. The odd SRAM data output signal line is used to output odd SRAM data signals; the even SRAM data output signal line is used to output even SRAM data signals. The SRAM data output signal line is used to output complete SRAM data; The data output signal line is used to output the buffered data stream.

[0009] Secondly, based on the same concept, the present invention also provides a read / write control method for single-clock-domain SRAM, comprising the following steps: S1. Set the SRAM read / write mode and the SRAM clock division factor n; S2. Based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port; In step S2, based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port, including: If the SRAM read / write mode is set to first-in-first-out read / write mode, and the SRAM clock divider factor n is set to 1, then the SRAM read / write steps include: when writing data to the odd SRAM module, reading data from the even SRAM module; when writing data to the even SRAM module, reading data from the odd SRAM module.

[0010] Furthermore, in step S2, based on the SRAM read / write method and the SRAM clock division factor n, reading and writing the SRAM using a single port also includes: If the SRAM read / write mode is set to first-in, last-out (LIFO) and the SRAM clock divider factor n is set to 1, then the SRAM read / write steps include: storing new data in the address of the old data that has already been read; when writing data to the odd SRAM module, reading data from the even SRAM module; and when writing data to the even SRAM module, reading data from the odd SRAM module.

[0011] Furthermore, in step S2, based on the SRAM read / write method and the SRAM clock division factor n, reading and writing the SRAM using a single port also includes: If the SRAM read / write mode is set to first-in-first-out (FIFO) and the SRAM clock division factor n is set to a positive integer greater than 1, then the SRAM read / write steps include: when reading data from the odd or even SRAM module, the process lasts for n-1 more cycles; when the FIFO module outputs the data stream, synchronization processing is performed to synchronize the data stream with 1 / n times the SRAM clock CLK.

[0012] Compared with existing technologies, the read / write control system and method based on single-clock domain SRAM described in this invention have the following advantages: (1) Using a single-clock domain SRAM with smaller area, lower power consumption and lower cost, we designed an odd SRAM module and an even SRAM module to realize simultaneous read and write functions.

[0013] (2) An SRAM control module was designed to implement special SRAM control, so that the memory can be read and written simultaneously in the first-in-last-out mode.

[0014] (3) An odd-even selection module and a matching FIFO were designed so that the memory can reduce the frequency of the data stream by 1 / n times. When the amount of data accumulates, the pressure of data transmission through the interface can be effectively reduced.

[0015] (4) Since all operations are performed in the same clock domain, design and timing analysis become simpler, reducing the complexity caused by multiple clock domains. Attached Figure Description

[0016] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the overall architecture as described in an embodiment of the present invention; Figure 2 This is a schematic diagram of the first-in-first-out (n=1) read / write method described in an embodiment of the present invention; Figure 3 This is a schematic diagram of the first-in-last-out (n=1) read / write method described in an embodiment of the present invention; Figure 4 This is a schematic diagram of the first-in-first-out (n=2) read / write method described in an embodiment of the present invention. Detailed Implementation

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] A read / write control system based on single-clock domain SRAM includes an SRAM control module, an odd SRAM module, an even SRAM module, an odd / even data selection module, and a FIFO module. The SRAM control module is connected to the odd and even SRAM modules via signal lines. The odd and even SRAM modules are both connected to the odd / even data selection module via signal lines. The odd / even data selection module is connected to the FIFO module via a signal line. The FIFO module is connected to an external device via a signal line. The signal lines connecting the SRAM control module and the odd SRAM module include an odd SRAM chip select signal line, an odd SRAM write enable signal line, and an odd SRAM write enable signal line. RAM address signal lines, odd SRAM data input signal lines; signal lines connecting the SRAM control module and the even SRAM module include even SRAM chip select signal lines, even SRAM write enable signal lines, even SRAM address signal lines, and even SRAM data input signal lines; signal lines connecting the odd SRAM module and the odd / even data selection module include odd SRAM data output signal lines; signal lines connecting the even SRAM module and the odd / even data selection module include even SRAM data output signal lines; signal lines connecting the odd / even data selection module and the FIFO module include SRAM data output signal lines; signal lines connecting the FIFO module and external devices include data output signal lines.

[0022] The odd SRAM data input signal line, even SRAM data input signal line, odd SRAM data output signal line, even SRAM data output signal line, and SRAM data output signal line are all synchronized with the SRAM clock CLK; the data output signal line is synchronized with 1 / n times the SRAM clock CLK, where n is the SRAM clock division factor, which is set to a positive integer.

[0023] The SRAM control module receives raw input data and sends chip select, write enable, address, and data input commands to the odd and even SRAM modules. The odd and even SRAM modules are used as single-clock domain SRAMs with no redundant storage depth, alternately performing read and write operations. The odd / even data selection module concatenates the data output from the odd and even SRAM modules into complete SRAM data. The FIFO module buffers data and synchronizes the output data stream to 1 / n times the SRAM clock CLK.

[0024] The odd SRAM chip select signal line is used to transmit the odd SRAM chip select signal; the even SRAM chip select signal line is used to transmit the even SRAM chip select signal; the odd SRAM write enable signal line is used to transmit the odd SRAM write enable signal; the even SRAM write enable signal line is used to transmit the even SRAM write enable signal; the odd SRAM address signal line is used to transmit the odd SRAM address signal; the even SRAM address signal line is used to transmit the even SRAM address signal; the odd SRAM data input signal line is used to input the odd SRAM data signal; the even SRAM data input signal line is used to input the even SRAM data signal; the odd SRAM data output signal line is used to output the odd SRAM data signal; the even SRAM data output signal line is used to output the even SRAM data signal; the SRAM data output signal line is used to output the complete SRAM data; the data output signal line is used to output the buffered data stream.

[0025] A read / write control method based on single-clock-domain SRAM includes the following steps: S1. Set the SRAM read / write mode and the SRAM clock division factor n; S2. Based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port; In step S2, based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port, including: (1) If the SRAM read / write mode is set to first-in-first-out read / write mode and the SRAM clock division factor n is set to 1, the SRAM read / write steps include: when writing data to the odd SRAM module, reading data from the even SRAM module; when writing data to the even SRAM module, reading data from the odd SRAM module.

[0026] (2) If the SRAM read / write mode is set to first-in-last-out read / write mode and the SRAM clock divider factor n is set to 1, then the SRAM read / write steps include: storing new data into the address of the old data that has been read; when writing data to the odd SRAM module, reading data from the even SRAM module; when writing data to the even SRAM module, reading data from the odd SRAM module.

[0027] (3) If the SRAM read / write mode is set to first-in-first-out read / write mode, and the SRAM clock division factor n is set to a positive integer greater than 1, then the SRAM read / write steps include: when reading data from the odd SRAM module or the even SRAM module, it lasts for n-1 more cycles; when the FIFO module outputs the data stream, it performs synchronization processing to synchronize the data stream with 1 / n times the SRAM clock CLK.

[0028] Example 1: likeFigure 1 As shown, the raw input data synchronized with the SRAM clock CLK is transmitted to the SRAM control module. After processing, the SRAM control module outputs the odd SRAM chip select signal (sram_cen_odd), the odd SRAM write enable signal (sram_wen_odd), the odd SRAM address signal (sram_addr_odd), and the odd SRAM data input signal synchronized with the SRAM clock CLK (sram_din_odd) to the odd SRAM module; and outputs the even SRAM chip select signal (sram_cen_even), the even SRAM write enable signal (sram_wen_even), the even SRAM address signal (sram_addr_even), and the even SRAM data input signal synchronized with the SRAM clock CLK (sram_din_even) to the even SRAM module.

[0029] Meanwhile, the SRAM control module also controls the data output of the two SRAM modules. When the odd SRAM module writes data, it controls the even SRAM to read data, and when the even SRAM module writes data, it controls the odd SRAM module to read data. The odd SRAM module outputs odd SRAM output data (sram_dout_odd) synchronized with the SRAM clock CLK, and the even SRAM module outputs even SRAM output data (sram_dout_even) synchronized with the SRAM clock CLK. Both odd and even SRAM output data are transmitted to the odd-even data selection module. The odd-even data selection module concatenates the odd and even SRAM output data together, and then outputs complete SRAM output data (sram_dout) synchronized with the SRAM clock CLK. The complete SRAM output data (sram_dout) is transmitted to the FIFO. After synchronization by the FIFO, the FIFO outputs the final data stream (outputdata) synchronized with 1 / n times the SRAM clock CLK, where n=1, 2, 3...

[0030] Example 2: like Figure 2 As shown, in a first-in-first-out (FIFO) read / write mode (n=1), new data (data4) is sequentially written to the address of the already read data (data0), and subsequent data (data5, data6, and data7) are also sequentially stored in the addresses of the already read data (data1, data2, and data3). While writing data4 to the even-numbered SRAM module, data1 is also read from the odd-numbered SRAM module; similarly, while writing data5 and data6, data2 and data3 are also read. In other words, under the FIFO read / write mode, SRAM is read and written simultaneously.

[0031] Example 3: like Figure 3 As shown, in the Last-In-First-Out (LIFO) read / write mode (n=1), new data (data4) is sequentially written to the address of the already read data (data3). Subsequent data (data5, data6, and data7) are also sequentially written to the addresses of the already read data (data2, data1, and data0), avoiding overwriting valid data. While writing data4 to the odd-numbered SRAM module, data2 is also read from the even-numbered SRAM module. Similarly, while writing data5 and data6, data1 and data0 are also read from the even-numbered SRAM module. In other words, in the LIFO read / write mode, SRAM is read and written simultaneously.

[0032] Example 4: like Figure 4 As shown, in the first-in-first-out read / write mode (n=2), when reading data0, data0 is allowed to continue for one more clock cycle, that is, the read data0 is maintained for two clock cycles. The subsequent data1, data2 and data3 are processed in the same way. After the subsequent FIFO synchronization, the read data is synchronized with 1 / 2 times the SRAM clock CLK, thus achieving a 1 / 2 reduction in the frequency of the data stream.

[0033] The innovative aspects of this invention: (1) In view of the problem that traditional single-port SRAM cannot be read and written at the same time, this invention designs odd and even SRAM to be read and written separately. Data can be read and written at the same time using single-port SRAM, which improves data transmission efficiency and does not have to wait until all data is read or written before writing or reading. In the first-in-last-out (FIFO) mode, the speed is improved by changing the data storage address: by changing the write address of the data to the address of the data that has already been read, valid data is prevented from being overwritten, so that the FIFO mode can also read and write data simultaneously, thus improving the overall data transmission speed of the design.

[0034] (2) FIFO module synchronous frequency reduction: In view of the problem that traditional single-clock domain SRAM cannot change the clock frequency of read data, the present invention designs a FIFO module to keep the data stream output compatible with the external device. When reading data, it can keep the time n-1 time. Then, the odd-even selection module combines the data read from the odd SRAM module and the even SRAM module into complete SRAM data. Finally, through the synchronization of the FIFO module, the output data stream is synchronized with 1 / n times the SRAM clock CLK.

[0035] Advantages and beneficial effects of the present invention: (1) Using a single-clock domain SRAM with smaller area, lower power consumption and lower cost, we designed an odd SRAM module and an even SRAM module to realize simultaneous read and write functions.

[0036] (2) An SRAM control module was designed to implement special SRAM control, so that the memory can be read and written simultaneously in the first-in-last-out mode.

[0037] (3) An odd-even selection module and a matching FIFO were designed so that the memory can reduce the frequency of the data stream by 1 / n times. When the amount of data accumulates, the pressure of data transmission through the interface can be effectively reduced.

[0038] (4) Since all operations are performed in the same clock domain, design and timing analysis become simpler, reducing the complexity caused by multiple clock domains.

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A read / write control system based on single-clock-domain SRAM, characterized in that: It includes an SRAM control module, an odd SRAM module, an even SRAM module, an odd / even data selection module, and a FIFO module; The SRAM control module is connected to the odd SRAM module and the even SRAM module respectively via signal lines. The odd SRAM module and the even SRAM module are both connected to the odd-even data selection module via signal lines. The odd-even data selection module is connected to the FIFO module via signal lines. The FIFO module is connected to external devices via signal lines. The signal lines connecting the SRAM control module and the odd SRAM module include the odd SRAM chip select signal line, the odd SRAM write enable signal line, the odd SRAM address signal line, and the odd SRAM data input signal line. The signal lines connecting the SRAM control module and the even SRAM module include the even SRAM chip select signal line, the even SRAM write enable signal line, the even SRAM address signal line, and the even SRAM data input signal line. The signal lines connecting the odd SRAM module and the odd / even data selection module include the odd SRAM data output signal lines; The signal lines connecting the even SRAM module and the odd / even data selection module include the even SRAM data output signal lines; The signal lines connecting the parity data selection module and the FIFO module include the SRAM data output signal lines; The signal lines connecting the FIFO module and external devices include data output signal lines.

2. The read / write control system based on single-clock domain SRAM according to claim 1, characterized in that: The odd SRAM data input signal line, even SRAM data input signal line, odd SRAM data output signal line, even SRAM data output signal line, and SRAM data output signal line are all synchronized with the SRAM clock CLK.

3. The read / write control system based on single-clock domain SRAM according to claim 2, characterized in that: The data output signal line is synchronized with 1 / n times the SRAM clock CLK, where n is the SRAM clock division factor, which is set to a positive integer.

4. The read / write control system based on single-clock domain SRAM according to claim 3, characterized in that: The SRAM control module is used to receive raw input data and send chip select, write enable, address and data input instructions to the odd SRAM module and even SRAM module. The odd SRAM module and even SRAM module are used as single-clock domain SRAMs with no redundant storage depth, and alternately perform read and write operations. The odd / even data selection module is used to concatenate the data output by the odd SRAM module and the even SRAM module into complete SRAM data. The FIFO module is used to cache data and synchronize the output data stream to 1 / n times the SRAM clock CLK.

5. The read / write control system based on single-clock domain SRAM according to claim 3, characterized in that: The odd SRAM chip select signal line is used to transmit the odd SRAM chip select signal; the even SRAM chip select signal line is used to transmit the even SRAM chip select signal. The odd SRAM write enable signal line is used to transmit the odd SRAM write enable signal; the even SRAM write enable signal line is used to transmit the even SRAM write enable signal. The odd SRAM address signal line is used to transmit the odd SRAM address signal; the even SRAM address signal line is used to transmit the even SRAM address signal. The odd SRAM data input signal line is used to input odd SRAM data signals; the even SRAM data input signal line is used to input even SRAM data signals. The odd SRAM data output signal line is used to output odd SRAM data signals; the even SRAM data output signal line is used to output even SRAM data signals. The SRAM data output signal line is used to output complete SRAM data; The data output signal line is used to output the buffered data stream.

6. A read / write control method based on single-clock-domain SRAM, applied to the read / write control system based on single-clock-domain SRAM as described in any one of claims 1-5, characterized in that: Includes the following steps: S1. Set the SRAM read / write mode and the SRAM clock division factor n; S2. Based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port; In step S2, based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port, including: If the SRAM read / write mode is set to first-in-first-out read / write mode, and the SRAM clock divider factor n is set to 1, then the SRAM read / write steps include: when writing data to the odd SRAM module, reading data from the even SRAM module; when writing data to the even SRAM module, reading data from the odd SRAM module.

7. The read / write control method based on single-clock domain SRAM according to claim 6, characterized in that: In step S2, based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port, which also includes: If the SRAM read / write mode is set to first-in, last-out (LIFO) and the SRAM clock divider factor n is set to 1, then the SRAM read / write steps include: storing new data in the address of the old data that has already been read; when writing data to the odd SRAM module, reading data from the even SRAM module; and when writing data to the even SRAM module, reading data from the odd SRAM module.

8. The read / write control method based on single-clock domain SRAM according to claim 7, characterized in that: In step S2, based on the SRAM read / write method and the SRAM clock division factor n, SRAM is read and written using a single port, which also includes: If the SRAM read / write mode is set to first-in-first-out (FIFO) and the SRAM clock division factor n is set to a positive integer greater than 1, then the SRAM read / write steps include: when reading data from the odd or even SRAM module, the process lasts for n-1 more cycles; when the FIFO module outputs the data stream, synchronization processing is performed to synchronize the data stream with 1 / n times the SRAM clock CLK.

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