Level conversion circuit, PCB and chip

Abstract

The invention relates to the technical field of electronics, and discloses a level conversion circuit, a PCB and a chip, and the level conversion circuit comprises a current compensation unit, a switch trigger unit, a level conversion unit, a bias unit and an output unit. The switch triggering unit is used for receiving an external low-voltage domain control signal; the current compensation unit is used for suppressing power supply interference in a signal conversion process; the level conversion unit is used for converting a low-voltage domain signal into a high-voltage domain signal; the bias unit is used for providing working current for the level conversion unit; the output unit is used for shaping the high-voltage domain signal to output a high-voltage domain control signal of a standard logic level; through cooperation of all the units, stable conversion from low-voltage domain signals to high-voltage domain signals is achieved, and the problem that in the prior art, signal conversion is not stable due to power interference is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a level conversion circuit, a PCB and a chip. BACKGROUND

[0002] In the application scenario of converting a low-voltage domain control signal into a high-voltage domain signal, the power supply of the high-voltage domain is easily affected by external load switches and other factors to generate interference, which can invade the signal conversion link, resulting in level jitter, false triggering and other problems of the converted signal, and further affecting the accurate recognition of the control signal by the subsequent circuit, and it is difficult to achieve stable and reliable signal conversion. SUMMARY

[0003] The technical problem to be solved by the present application is to solve at least one of the technical problems mentioned above.

[0004] The solution to the technical problem of the present application is: The first aspect of the present application provides a level conversion circuit, comprising: a current compensation unit, a switch trigger unit, a level conversion unit, a bias unit and an output unit; the level conversion unit is electrically connected with the bias unit, the current compensation unit, the switch trigger unit and the output unit; the current compensation unit is electrically connected with the switch trigger unit; the bias unit is electrically connected with the output unit; the switch trigger unit is used for receiving an external low-voltage domain control signal; the current compensation unit is used for suppressing power supply interference in the signal conversion process; the level conversion unit is used for converting a low-voltage domain signal into a high-voltage domain signal; the bias unit is used for providing working current for the level conversion unit; and the output unit is used for shaping the high-voltage domain signal to output a high-voltage domain control signal with a standard logic level.

[0005] The beneficial effects of the first aspect of the present application are as follows: first, the switch trigger unit receives an external low-voltage domain control signal to provide an accurate starting basis for signal conversion; in the signal conversion process, the current compensation unit specifically suppresses power supply interference to reduce the damage of interference to the conversion link from the source and create a stable environment for signal conversion; the bias unit provides stable working current for the level conversion unit to ensure that the conversion process of the low-voltage domain signal into the high-voltage domain signal has continuous and reliable driving support; finally, the output unit shapes the converted high-voltage domain signal to make the output signal meet the standard logic level requirement, which is convenient for accurate recognition by the subsequent circuit; through the cooperation of each unit, the present application realizes stable conversion of the low-voltage domain signal into the high-voltage domain signal, and effectively solves the problem of unstable signal conversion caused by power supply interference in the prior art.

[0006] As some sub-schemes of the above technical solutions, the level conversion circuit further comprises a high-voltage ground VSSH; the switch trigger unit comprises a first voltage-resistant tube NLD1, a second voltage-resistant tube NLD2, a first signal input end IN1 and a second signal input end IN2; the high-voltage ground VSSH is connected with a source of the first voltage-resistant tube NLD1 and a source of the second voltage-resistant tube NLD2; a drain of the first voltage-resistant tube NLD1 is connected with the current compensation unit, and a gate of the first voltage-resistant tube NLD1 is connected with the first signal input end IN1; a drain of the second voltage-resistant tube NLD2 is connected with the current compensation unit, and a gate of the second voltage-resistant tube NLD2 is connected with the second signal input end IN2.

[0007] As some sub-schemes of the above technical solutions, the level conversion circuit further comprises a high-voltage power supply end VDDH; the current compensation unit comprises a first transistor M1, an eighth transistor M8, a ninth transistor M9 and a fourteenth transistor M14; the high-voltage power supply end VDDH is connected with a source of the first transistor M1 and a source of the eighth transistor M8; a gate of the first transistor M1 and a gate of the eighth transistor M8 are connected with the level conversion unit; a drain of the first transistor M1 is connected with the ninth transistor M9, a gate of the ninth transistor M9 is connected with a drain of the ninth transistor M9, the first voltage-resistant tube NLD1 and the level conversion unit; a drain of the eighth transistor M8 is connected with a source of the fourteenth transistor M14, a gate of the fourteenth transistor M14 is connected with a drain of the fourteenth transistor M14, the second voltage-resistant tube NLD2 and the level conversion unit.

[0008] As some sub-schemes of the above technical solutions, the level conversion unit comprises a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7; the high-voltage power supply end VDDH is connected with the source of the second transistor M2, the source of the third transistor M3, the source of the fourth transistor M4, the source of the fifth transistor M5, the source of the sixth transistor M6 and the source of the seventh transistor M7; the gate of the second transistor M2 is connected with the drain of the second transistor M2, the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the eighth transistor M8 and the gate of the ninth transistor M9; the gate of the seventh transistor M7 is connected with the drain of the seventh transistor M7, the gate of the sixth transistor M6, the gate of the fifth transistor M5, the gate of the first transistor M1 and the gate of the fourteenth transistor M14; the drain of the third transistor M3 and the drain of the sixth transistor M6 are connected with the bias unit; the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are connected with the bias unit and the output unit.

[0009] As some sub-schemes of the above technical solutions, the bias unit comprises a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13; the drain of the tenth transistor M10 is connected with the drain of the third transistor M3, the gate of the tenth transistor M10 and the gate of the eleventh transistor M11; the source of the tenth transistor M10 is connected with the source of the eleventh transistor M11, the source of the twelfth transistor M12 and the source of the thirteenth transistor M13; the drain of the eleventh transistor M11 is connected with the drain of the fifth transistor M5 and the output unit; the drain of the thirteenth transistor M13 is connected with the drain of the sixth transistor M6, the gate of the thirteenth transistor M13 and the gate of the twelfth transistor M12; the drain of the twelfth transistor M12 is connected with the drain of the fourth transistor M4 and the output unit.

[0010] As some sub-schemes of the technical scheme, the output unit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a non-inverted output terminal VOUTP and an inverted output terminal VOUTN; an input terminal of the first inverter INV1 is connected with a drain of the eleventh transistor M11, an input terminal of the third inverter INV3 and an output terminal of the second inverter INV2, an output terminal of the first inverter INV1 is connected with a drain of the twelfth transistor M12, an input terminal of the fourth inverter INV4 and an input terminal of the second inverter INV2; an output terminal of the third inverter INV3 is connected with the non-inverted output terminal VOUTP; an output terminal of the fourth inverter INV4 is connected with the inverted output terminal VOUTN.

[0011] The second aspect embodiment of the present application provides a PCB board, which is printed with the level conversion circuit according to any one of the above.

[0012] The PCB board according to the second aspect embodiment of the present application has the corresponding beneficial effects due to the level conversion circuit according to the above technical scheme.

[0013] The third aspect embodiment of the present application provides a chip, which is realized for work control by using the level conversion circuit according to any one of the above.

[0014] The chip according to the third aspect embodiment of the present application has the corresponding beneficial effects due to the level conversion circuit according to the above technical scheme. BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 is a circuit block diagram of the level conversion circuit provided by the present application; Fig. 2 is a circuit principle diagram of the level conversion circuit of the present application; Reference signs in the drawings: 1 - current compensation unit, 2 - switch trigger unit, 3 - level conversion unit, 4 - bias unit, 5 - output unit. DETAILED DESCRIPTION

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the above description of the embodiments needed to use the drawings is briefly described. Obviously, the described drawings are only some of the embodiments of the present application, not all embodiments, and those skilled in the art can obtain other design schemes and drawings according to these drawings without creative labor.

[0017] The concept, specific structure and generated technical effects of the present application will be described clearly and completely in combination with the embodiments and drawings, so as to fully understand the purposes, features and effects of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments, and other embodiments obtained by those skilled in the art without creative labor based on the embodiments of the present application are within the protection scope of the present application. In addition, all the coupling / connection relationships mentioned in the text do not mean that the components are directly connected, but that a better coupling structure can be formed by adding or reducing coupling accessories according to the specific implementation. The technical features in the present application can be combined interactively without conflict.

[0018] Reference Figs. 1-2 The embodiments of the present application are described; The first aspect of the present application provides a level conversion circuit, comprising: A current compensation unit 1, a switch trigger unit 2, a level conversion unit 3, a bias unit 4 and an output unit 5; the level conversion unit 3 is electrically connected with the bias unit 4, the current compensation unit 1, the switch trigger unit 2 and the output unit 5; the current compensation unit 1 is electrically connected with the switch trigger unit 2; the bias unit 4 is electrically connected with the output unit 5; the switch trigger unit 2 is used for receiving an external low-voltage domain control signal; the current compensation unit 1 is used for suppressing power interference in the signal conversion process; the level conversion unit 3 is used for converting the low-voltage domain signal into a high-voltage domain signal; the bias unit 4 is used for providing working current for the level conversion unit 3; and the output unit 5 is used for shaping the high-voltage domain signal to output a high-voltage domain control signal of standard logic level.

[0019] In the embodiment, the switch trigger unit 2 first receives an external low-voltage domain control signal to provide an accurate starting basis for signal conversion; in the signal conversion process, the current compensation unit 1 suppresses the power interference in a targeted manner to reduce the damage of the interference to the conversion link from the source, creating a stable environment for signal conversion; the bias unit 4 provides stable working current for the level conversion unit 3 to ensure that the conversion process of the low-voltage domain signal to the high-voltage domain signal has continuous and reliable driving support; finally, the output unit 5 shapes the converted high-voltage domain signal to make the output signal meet the standard logic level requirement, facilitating accurate identification of subsequent circuits; through the cooperation of each unit, the present application realizes stable conversion of the low-voltage domain signal to the high-voltage domain signal, effectively solving the problem of unstable signal conversion caused by power interference in the prior art.

[0020] Specifically, the level conversion circuit further comprises a high-voltage ground VSSH; the switch trigger unit 2 comprises a first voltage-resistant tube NLD1, a second voltage-resistant tube NLD2, a first signal input end IN1 and a second signal input end IN2; the high-voltage ground VSSH is connected with the source of the first voltage-resistant tube NLD1 and the source of the second voltage-resistant tube NLD2; the drain of the first voltage-resistant tube NLD1 is connected with the current compensation unit 1, and the gate of the first voltage-resistant tube NLD1 is connected with the first signal input end IN1; the drain of the second voltage-resistant tube NLD2 is connected with the current compensation unit 1, and the gate of the second voltage-resistant tube NLD2 is connected with the second signal input end IN2; In the embodiment, the high-voltage ground VSSH serves as a low-potential reference end of the high-voltage domain and, together with the high-voltage power end VDDH, forms a high-voltage domain power supply loop to provide a potential reference for stable operation of the switch trigger unit 2 and subsequent circuits; the switch trigger unit 2 undertakes the function of connecting the low-voltage domain control signal and the high-voltage domain circuit, and the core elements, the first voltage-resistant tube NLD1 and the second voltage-resistant tube NLD2, are both high-voltage compatible NMOS tubes, which have the characteristic of resisting high-voltage domain voltage and can effectively isolate the potential difference between the high-voltage domain and the low-voltage domain to avoid damage to low-voltage domain elements due to bearing high voltage; The signals received by the first signal input end IN1 and the second signal input end IN2 are generated by external low-voltage domain control signals through a pulse generation circuit, wherein the first signal input end IN1 receives a high pulse signal triggered by the rising edge of the low-voltage domain control signal, and the second signal input end IN2 receives a high pulse signal triggered by the falling edge of the low-voltage domain control signal, and the two signals are complementary in time sequence and output high level only at the corresponding edge time, thereby realizing precise time sequence control of signal conversion. When the low-voltage domain control signal generates a rising edge, the first signal input end IN1 outputs a high pulse, so that the gate of the first voltage-resistant tube NLD1 obtains sufficient driving voltage and turns on, at this time, the corresponding high rail branch forms a current loop of "level conversion unit 3 branch node-first voltage-resistant tube NLD1 drain-first voltage-resistant tube NLD1 source-high voltage ground VSSH", which provides a conduction basis for signal amplification and conversion of the subsequent level conversion unit 3; at the same time, the second signal input end IN2 is at a low level, and the second voltage-resistant tube NLD2 remains off, and no current flows through the corresponding branch, avoiding mutual interference between the two signals; conversely, when the low-voltage domain control signal generates a falling edge, the second signal input end IN2 outputs a high pulse, and the second voltage-resistant tube NLD2 turns on, and the corresponding high rail branch "level conversion unit 3 branch node-second voltage-resistant tube NLD2 drain-second voltage-resistant tube NLD2 source-high voltage ground VSSH" forms an effective current loop, while the first voltage-resistant tube NLD1 is off; through this "single-edge triggering and alternating conduction" design, the switch triggering unit 2 realizes accurate transmission of low-voltage domain timing signals to the high-voltage domain branch, provides clear start trigger signals for the subsequent current compensation, level conversion and other processes, and at the same time, with the isolation characteristics of the voltage-resistant tube, the independent working safety of the high and low voltage domain circuits is ensured.

[0021] Specifically, the level conversion circuit further comprises a high-voltage power supply end VDDH; the current compensation unit 1 comprises a first transistor M1, an eighth transistor M8, a ninth transistor M9 and a fourteenth transistor M14; the high-voltage power supply end VDDH is connected with the source of the first transistor M1 and the source of the eighth transistor M8; the gate of the first transistor M1 and the gate of the eighth transistor M8 are connected with the level conversion unit 3; the drain of the first transistor M1 is connected with the ninth transistor M9, the gate of the ninth transistor M9 is connected with the drain of the ninth transistor M9, the first voltage-resistant tube NLD1 and the level conversion unit 3; the drain of the eighth transistor M8 is connected with the source of the fourteenth transistor M14, the gate of the fourteenth transistor M14 is connected with the drain of the fourteenth transistor M14, the second voltage-resistant tube NLD2 and the level conversion unit 3; In this embodiment, the high-voltage power supply end VDDH provides power support for the high-voltage domain of the entire level conversion circuit; The current compensation unit 1 is a core structure for suppressing dv / dt interference, and the connection mode of each transistor is as follows: the source of the first transistor M1 and the source of the eighth transistor M8 are directly connected to the high-voltage power supply end VDDH, and the power supply is quickly obtained to generate a compensation current; the gate of each of the two is connected to the A node (the gate of the second transistor M2, the gate of the third transistor M3, and the gate of the fourth transistor M4) and the B node (the gate of the fifth transistor M5, the gate of the sixth transistor M6, and the gate of the seventh transistor M7) of the level conversion unit 3, which can detect the node voltage change of the level conversion unit 3 in real time and provide a trigger basis for interference suppression; the drain of the first transistor M1 is connected to the source of the ninth transistor M9, and the ninth transistor M9 adopts a diode connection mode (the gate is short-circuited with the drain), so that the ninth transistor M9 forms a stable current path, and the drain thereof is interconnected with the branch node of the level conversion unit 3 and the output end (the drain of the first voltage-resistant tube NLD1) of the switch trigger unit 2, so as to realize precise connection of the compensation current and the signal conversion branch; similarly, the drain of the eighth transistor M8 is connected to the source of the fourteenth transistor M14, and the fourteenth transistor M14 also adopts a diode connection mode (the gate is short-circuited with the drain), and the drain thereof is interconnected with the other branch node of the level conversion unit 3 and the other output end (the drain of the second voltage-resistant tube NLD2) of the switch trigger unit 2, so as to form a symmetrical compensation branch structure. When the high-voltage power supply end VDDH or the high-voltage ground end VSSH of the high-voltage domain generates a large dv / dt interference due to IGBT switching, the A node and the B node of the level conversion unit 3 will have abnormal voltage drop due to charging of the parasitic capacitance, at this time, the gate voltage of the first transistor M1 or the eighth transistor M8 changes synchronously with the node voltage and turns on, the electric energy of the high-voltage power supply end VDDH flows to the ninth transistor M9 / eighth transistor M14 through the first transistor M1 / eighth transistor M8, and the compensation current is stably output through the diode connection structure of the ninth transistor M9 / fourteenth transistor M14, so as to accurately lift the abnormal voltage of the A node and the B node, avoid the mismatch of the current of the related branch of the level conversion unit 3 due to the too low node voltage, and thus suppress the generation of false short pulses; and in the normal working of the circuit (when dv / dt is small), the voltage of the A node and the B node is in a stable state, the first transistor M1 and the eighth transistor M8 remain off, and no current flows through the compensation branch, so as not to increase the static power consumption of the circuit.

[0022] Specifically, the level conversion unit 3 comprises a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7; the high-voltage power supply end VDDH is connected with the source of the second transistor M2, the source of the third transistor M3, the source of the fourth transistor M4, the source of the fifth transistor M5, the source of the sixth transistor M6 and the source of the seventh transistor M7; the gate of the second transistor M2 is connected with the drain of the second transistor M2, the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the eighth transistor M8 and the gate of the ninth transistor M9; the gate of the seventh transistor M7 is connected with the drain of the seventh transistor M7, the gate of the sixth transistor M6, the gate of the fifth transistor M5, the gate of the first transistor M1 and the gate of the fourteenth transistor M14; the drain of the third transistor M3 and the drain of the sixth transistor M6 are connected with the bias unit 4; the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are connected with the bias unit 4 and the output unit 5; In the embodiment, the high-voltage power supply end VDDH provides high-voltage domain power supply for the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7, so as to ensure that each transistor has sufficient driving capability to complete signal amplification and latching; on the core node connected with the gate, the second transistor M2 adopts a diode connection mode (the gate is short-circuited with the drain), and the gate of the second transistor M2 is interconnected with the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the eighth transistor M8 in the current compensation unit 1 and the gate of the ninth transistor M9, thereby forming a left common node (i.e. node A in Fig. 2 ); the node A serves as a signal reference of the left branch of the level conversion unit 3, and synchronously transmits the node voltage state to the current compensation unit 1, thereby providing a trigger basis for interference suppression; the seventh transistor M7 also adopts a diode connection mode (the gate is short-circuited with the drain), and the gate of the seventh transistor M7 is interconnected with the gate of the sixth transistor M6, the gate of the fifth transistor M5, the gate of the first transistor M1 in the current compensation unit 1 and the gate of the fourteenth transistor M14, thereby forming a right common node (i.e. node B in Fig. 2 ); the node B and the node A form a strictly symmetrical structure, thereby guaranteeing the balanced working characteristics of the circuit; In the signal amplification and latching link, the third transistor M3 and the fourth transistor M4, the sixth transistor M6 and the fifth transistor M5 respectively form two complementary differential branches: the third transistor M3 and the fourth transistor M4 form the left differential amplification branch, the third transistor M3 as a current mirror load converts the current signal into a voltage signal, and the fourth transistor M4 as a differential amplifier receives the signal of node A and amplifies it; the sixth transistor M6 and the fifth transistor M5 form the right differential amplification branch, the sixth transistor M6 as a symmetrical current mirror load, and the fifth transistor M5 as a right differential amplifier, forming a mirror structure with the left branch to ensure balanced amplification of the differential signal; and the cross-coupling between the fourth transistor M4 and the fifth transistor M5 is the key to realizing signal latching: when the switch trigger unit 2 is turned on for the corresponding branch (such as the first voltage-resistant tube NLD1 being turned on), the voltage change of node A triggers the left branch to generate current, which is amplified through the third transistor M3 and the fourth transistor M4, and the cross-coupling structure accelerates the signal inversion, so that the circuit quickly enters the latching state, improving the conversion speed and anti-interference performance; When dv / dt interference in the high-voltage domain causes abnormal voltage at nodes A / B, the current compensation unit 1 can quickly detect and compensate the current through these interconnected nodes, further ensuring the stability of the level conversion unit 3; finally, the drain of the third transistor M3, the drain of the sixth transistor M6, and the bias unit 4 are connected to obtain a stable bias current; the gates of the fourth transistor M4 and the fifth transistor M5 transmit the latched node N, P signals to the output unit 5 to provide the original high / low level signals for subsequent shaping.

[0023] Specifically, the bias unit 4 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; the drain of the tenth transistor M10 is connected with the drain of the third transistor M3, the gate of the tenth transistor M10, and the gate of the eleventh transistor M11; the source of the tenth transistor M10 is connected with the source of the eleventh transistor M11, the source of the twelfth transistor M12, and the source of the thirteenth transistor M13; the drain of the eleventh transistor M11 is connected with the drain of the fifth transistor M5 and the output unit 5; the drain of the thirteenth transistor M13 is connected with the drain of the sixth transistor M6, the gate of the thirteenth transistor M13, and the gate of the twelfth transistor M12; the drain of the twelfth transistor M12 is connected with the drain of the fourth transistor M4 and the output unit 5; In this embodiment, the left current mirror branch (the tenth transistor M10 and the eleventh transistor M11) is responsible for providing a bias current for the right differential amplification branch (the branch where the fifth transistor M5 is located) of the level conversion unit 3: the tenth transistor M10 adopts a diode connection mode (the drain and the gate are shorted), and the drain thereof is connected with the drain of the third transistor M3 in the level conversion unit 3 and the gate of the eleventh transistor M11; the tenth transistor M10 forms a stable reference current when working in the saturation region, and the reference current is accurately copied to the eleventh transistor M11 through gate coupling, so that the eleventh transistor M11 outputs a bias current consistent with the reference current and directly supplies the drain of the fifth transistor M5, thereby ensuring that the fifth transistor M5 works in the saturation region as a differential amplifier and guaranteeing the linearity of signal amplification of the right branch; The right current mirror branch (the thirteenth transistor M13 and the twelfth transistor M12) is completely symmetrical with the left branch, and provides a bias current for the left differential amplification branch (the branch where the fourth transistor M4 is located) of the level conversion unit 3: the thirteenth transistor M13 adopts the same diode connection mode (the drain and the gate are shorted) as the tenth transistor M10, and the drain thereof is connected with the drain of the sixth transistor M6 in the level conversion unit 3 and the gate of the twelfth transistor M12; the thirteenth transistor M13 also forms a stable reference current, which is copied to the twelfth transistor M12 through gate coupling, so that the twelfth transistor M12 outputs a bias current matched with the eleventh transistor M11 and supplies the drain of the fourth transistor M4, thereby realizing strict symmetry of bias currents of the left and right differential branches. As an active load, the design of the bias unit 4 has double advantages compared with the traditional resistance load: on the one hand, the equivalent impedance of the active load composed of the NMOS current mirror is higher, which can significantly improve the differential amplification gain of the level conversion unit 3, so that the weak differential signal can be fully amplified; on the other hand, the integrated structure of the MOS tube greatly reduces the chip area, which meets the miniaturization demand of integrated circuit mass production.

[0024] Specifically, the output unit 5 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a same-phase output end VOUTP and an inverse-phase output end VOUTN; the input end of the first inverter INV1 is connected with the drain of the eleventh transistor M11, the input end of the third inverter INV3 and the output end of the second inverter INV2, the output end of the first inverter INV1 is connected with the drain of the twelfth transistor M12, the input end of the fourth inverter INV4 and the input end of the second inverter INV2; the output end of the third inverter INV3 is connected with the same-phase output end VOUTP; the output end of the fourth inverter INV4 is connected with the inverse-phase output end VOUTN; In the embodiment, the second inverter INV2 and the first inverter INV1 form a positive feedback latch structure; the input end of the second inverter INV2 is connected to the output end (node N signal) of the first inverter INV1, and the output end is connected to the input end (node P signal) of the first inverter INV1, forming a closed loop feedback; when the level conversion unit 3 is in a high level (VDDH) at the node N and a low level (VSSH) at the node P through the positive feedback latch, the closed loop latch structure further consolidates the state, accelerates the signal stabilization, avoids the node level jitter caused by external interference, and waits for the next low voltage domain control signal; The third inverter INV3 and the fourth inverter INV4 are used as a final stage shaping unit, and are respectively responsible for signal optimization of the non-inverted output end VOUTP and the inverted output end VOUTN: through the high gain characteristics of the inverters, the weak differential signal is amplified to a high level (VDDH) or a low level (VSSH) with stable amplitude, and then output to the output end, so as to ensure that the output signal is consistent with the logic phase of the low voltage domain control signal.

[0025] The second aspect embodiment of the present application provides a PCB board, and the PCB board is printed with the level conversion circuit according to any one of the above.

[0026] The third aspect embodiment of the present application provides a chip, and the chip is used for work control by using the level conversion circuit according to any one of the above.

[0027] The preferred embodiments of the present application are specifically described above, but the present application is not limited to the above-mentioned embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A level conversion circuit, characterized in that, include: The unit includes a current compensation unit, a switch triggering unit, a level conversion unit, a bias unit, and an output unit. The level conversion unit is electrically connected to the bias unit, the current compensation unit, the switch triggering unit, and the output unit; the current compensation unit is electrically connected to the switch triggering unit; the bias unit is electrically connected to the output unit; the switch triggering unit is used to receive external low-voltage domain control signals; the current compensation unit is used to suppress power supply interference during signal conversion. The level conversion unit is used to convert a low-voltage domain signal into a high-voltage domain signal; the bias unit is used to provide operating current for the level conversion unit; and the output unit is used to shape the high-voltage domain signal to output a high-voltage domain control signal with a standard logic level.

2. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit further includes a high-voltage ground terminal VSSH; the switch triggering unit includes a first withstand voltage transistor NLD1, a second withstand voltage transistor NLD2, a first signal input terminal IN1, and a second signal input terminal IN2; the high-voltage ground terminal VSSH is connected to the source of the first withstand voltage transistor NLD1 and the source of the second withstand voltage transistor NLD2; the drain of the first withstand voltage transistor NLD1 is connected to the current compensation unit, and the gate of the first withstand voltage transistor NLD1 is connected to the first signal input terminal IN1; the drain of the second withstand voltage transistor NLD2 is connected to the current compensation unit, and the gate of the second withstand voltage transistor NLD2 is connected to the second signal input terminal IN2.

3. The level conversion circuit according to claim 2, characterized in that: The level conversion circuit further includes a high-voltage power supply terminal VDDH; the current compensation unit includes a first transistor M1, an eighth transistor M8, a ninth transistor M9, and a fourteenth transistor M14; the high-voltage power supply terminal VDDH is connected to the source of the first transistor M1 and the source of the eighth transistor M8; the gate of the first transistor M1 and the gate of the eighth transistor M8 are connected to the level conversion unit; the drain of the first transistor M1 is connected to the ninth transistor M9, and the gate of the ninth transistor M9 is connected to the drain of the ninth transistor M9, the first withstand voltage transistor NLD1, and the level conversion unit; the drain of the eighth transistor M8 is connected to the source of the fourteenth transistor M14, and the gate of the fourteenth transistor M14 is connected to the drain of the fourteenth transistor M14, the second withstand voltage transistor NLD2, and the level conversion unit.

4. The level conversion circuit according to claim 3, characterized in that: The level conversion unit includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The high-voltage power supply terminal VDDH is connected to the source of the second transistor M2, the source of the third transistor M3, the source of the fourth transistor M4, the source of the fifth transistor M5, the source of the sixth transistor M6, and the source of the seventh transistor M7. The gate of the second transistor M2 is connected to the drain of the second transistor M2, the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the eighth transistor M8, and the gate of the ninth transistor M9. The gate of the seventh transistor M7 is connected to the drain of the seventh transistor M7, the gate of the sixth transistor M6, the gate of the fifth transistor M5, the gate of the first transistor M1, and the gate of the fourteenth transistor M14. The drain of the third transistor M3 and the drain of the sixth transistor M6 are connected to the bias unit. The gate of the fourth transistor M4 and the gate of the fifth transistor M5 are connected to the bias unit and the output unit.

5. The level conversion circuit according to claim 4, characterized in that: The bias unit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; the drain of the tenth transistor M10 is connected to the drain of the third transistor M3, the gate of the tenth transistor M10, and the gate of the eleventh transistor M11; the source of the tenth transistor M10 is connected to the source of the eleventh transistor M11, the source of the twelfth transistor M12, and the source of the thirteenth transistor M13; the drain of the eleventh transistor M11 is connected to the drain of the fifth transistor M5 and the output unit; the drain of the thirteenth transistor M13 is connected to the drain of the sixth transistor M6, the gate of the thirteenth transistor M13, and the gate of the twelfth transistor M12; the drain of the twelfth transistor M12 is connected to the drain of the fourth transistor M4 and the output unit.

6. The level conversion circuit according to claim 5, characterized in that: The output unit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a non-inverting output terminal VOUTP, and an inverting output terminal VOUTN. The input terminal of the first inverter INV1 is connected to the drain of the eleventh transistor M11, the input terminal of the third inverter INV3, and the output terminal of the second inverter INV2. The output terminal of the first inverter INV1 is connected to the drain of the twelfth transistor M12, the input terminal of the fourth inverter INV4, and the input terminal of the second inverter INV2. The output terminal of the third inverter INV3 is connected to the non-inverting output terminal VOUTP. The output terminal of the fourth inverter INV4 is connected to the inverting output terminal VOUTN.

7. A PCB board, characterized in that, The PCB board is printed with a level conversion circuit as described in any one of claims 1-6.

8. A chip, characterized in that, The chip employs a level conversion circuit as described in any one of claims 1-6 to achieve operational control.

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