Ethernet self-checking method and device, computer readable storage medium and program product

Abstract

The invention relates to an Ethernet self-checking method and device, a computer readable storage medium and a program product. The Ethernet self-checking method is characterized in that the Ethernet self-checking method is applied to a processor in an Ethernet self-checking device, and the device comprises a master station, a slave station and the processor; the master station and the slave station are located on the same tested PCBA board, and a master station network port of the master station is connected with a slave station network port of the slave station; the processor is respectively connected with the master station and the slave station through an Ethernet peripheral interface; the method comprises the following steps: when a starting signal of an upper computer is received, controlling the master station and the slave station to execute an Ethernet test process to obtain test results of the master station and the slave station; and feeding back the test result to the upper computer. By adopting the method, the test process can be simplified.

Description

Technical Field

[0001] This application relates to the field of network testing technology, and in particular to an Ethernet self-testing method, apparatus, computer-readable storage medium, and program product. Background Technology

[0002] Industrial Ethernet topologies are basically divided into master nodes and slave nodes. In PCBA testing, industrial Ethernet devices that integrate dedicated Ethernet peripherals need to undergo outgoing network performance testing before being used as slave devices in bus links. This requires deploying the front and rear stages of the link and the master station to cover all physical components and functional modules. In addition to industrial Ethernet, other functions of the slave devices also need to be tested and confirmed, making the entire set of test fixtures and test procedures often cumbersome and complex. Summary of the Invention

[0003] Therefore, it is necessary to provide an Ethernet self-testing method, apparatus, computer-readable storage medium, and program product that can simplify the testing process to address the aforementioned technical problems.

[0004] An Ethernet self-test method, characterized in that it uses a processor in an Ethernet self-test device, the device comprising a master station, a slave station, and a processor; the master station and the slave station are located on the same PCBA board under test, the master station's master port and the slave station's slave port are connected; the processor is connected to the master station and the slave station respectively via Ethernet peripheral interfaces; the method includes: When a start signal is received from the host computer, the master station and the slave station are controlled to execute the Ethernet test process and obtain the test results of the master station and the slave station. The test results are fed back to the host computer.

[0005] In one embodiment, an Ethernet self-test device is characterized in that the device includes a master station, a slave station, and a processor; the master station and the slave station are located on the same PCBA board under test, and the master station's master port and the slave station's slave port are connected; the processor is connected to the master station and the slave station respectively through an Ethernet peripheral interface; when the processor executes a computer program, it implements the steps of the above-described method embodiments.

[0006] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method embodiments.

[0007] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the above-described method embodiments.

[0008] The aforementioned Ethernet self-testing method, device, computer-readable storage medium, and program products address the traditional Ethernet testing requirements of deploying external network devices (such as switches and routers) and multiple independent nodes. By integrating the master and slave stations on the same PCBA board and directly connecting their network ports to form an internal loopback test path, the deployment overhead of other nodes in normal bus communication is saved. This transforms off-chip material and software deployment into on-chip self-testing as much as possible, thereby simplifying the testing process and reducing costs and space requirements. The processor automatically executes the entire testing process, reducing manual intervention. The host computer only needs to send a start signal to obtain the results, making it suitable for batch testing on production lines and improving testing efficiency. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a structural block diagram of an Ethernet self-test device in one embodiment; Figure 2 This is a flowchart illustrating an Ethernet self-test method in one embodiment. Detailed Implementation

[0011] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0013] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly. The connection can be a direct connection or an indirect connection.

[0014] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0015] The terms "first," "second," etc., used herein may be used to describe various types of data, but such data are not limited by these terms. These terms are only used to distinguish one type of data from another. For example, without departing from the scope of this application, a first data frame may be referred to as a second data frame, and similarly, a second data frame may be referred to as a first data frame. Both the first and second data frames are data frames, but they are not the same data frame.

[0016] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0017] It is understood that the "data acquisition" operation in the embodiments of this application includes, but is not limited to, the following implementation methods: directly reading the raw data pre-stored in the device; or the indirect acquisition method after data collection, conversion and processing.

[0018] The Ethernet self-test method provided in this application can be applied to, for example... Figure 1 In the application environment. Figure 1 This is a block diagram of an Ethernet self-test device in one embodiment. Ethernet self-testing includes industrial Ethernet self-testing. Figure 1The master station and slave station are located on the same PCBA (Printed Circuit Board Assembly) under test, and both are at the physical layer. The master station includes a connected master station network port, a transformer, and PHY1. PHY stands for Physical Layer Transceiver. The master station network port refers to the physical network interface of the master station on the PCBA under test. The slave station includes a connected slave station network port, a transformer, and PHY2. The slave station network port refers to the physical network interface of the slave station on the PCBA under test. The master station's master station network port and the slave station's slave station network port are connected. Processors are connected to both the master station and slave station via Ethernet peripheral interfaces. Processors include, but are not limited to, CPUs (Central Processing Units), MCUs (Microcontroller Units), and FPGAs (Field Programmable Gate Arrays). The Ethernet peripheral interface is connected to the memory, and both the Ethernet peripheral and the memory are located at the data link layer. From a topology perspective, the PCBA board under test is both a master node and a slave node, connected to the physical interfaces within the board only using network cables or fixtures.

[0019] Taking the application of this Ethernet self-test method to the processor in an Ethernet self-test device as an example, such as... Figure 2 The diagram shown is a flowchart of an Ethernet self-test method in one embodiment, including the following steps: Step 202: When the start signal from the host computer is received, control the master station and slave station to execute the Ethernet test process and obtain the test results of the master station and slave station.

[0020] The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The start signal refers to the instruction sent by the host computer, which includes at least the target protocol type and test parameters.

[0021] Specifically, upon receiving a start signal from the host computer, the processor parses the signal content to determine the start of the test. It then sends control commands, such as initialization configuration and test initiation, to the master and slave stations via the Ethernet peripheral interface. For example, the processor might configure the MAC addresses, IP addresses, and operating modes of the master and slave stations. The Ethernet testing process may include, but is not limited to, physical layer testing, basic network protocol testing and protocol data interaction testing, and error injection testing. The processor monitors the testing process in real time, collecting test data from the status registers of the master and slave stations or through polling, and storing it in memory. Test results can be binary states (e.g., pass or fail), quantitative indicators such as throughput, or analyzed test results.

[0022] Step 204: Feed back the test results to the host computer.

[0023] Specifically, the processor sends the test results to the host computer, enabling the host computer to display, store, or further process the test results.

[0024] In this embodiment, traditional Ethernet testing requires the deployment of external network devices (such as switches and routers) and multiple independent nodes. However, by integrating the master station and slave station on the same PCBA board and directly connecting their network ports to form an internal loopback test path, the deployment overhead of other nodes for normal bus communication is saved, thereby simplifying the testing process and reducing costs and space requirements. The processor automatically executes the entire testing process, reducing manual intervention. The host computer only needs to send a start signal to obtain the results, which is suitable for batch testing on the production line and improves testing efficiency.

[0025] In one embodiment, the master station's network port and the slave station's network port are connected via a network cable or a fixture.

[0026] Specifically, the network cable can be a standard Ethernet cable used to connect the network ports of the master and slave stations. A test fixture refers to a customized test fixture for the PCBA board under test. Its core function is to provide a stable and reliable electrical connection path, connecting the signal lines of the master and slave network ports on the board under test. It may be a simple connector adapter board or a complex test base with multiplexing and signal conditioning functions.

[0027] In this embodiment, the master station network port and the slave station network port are connected by a network cable or fixture to provide an effective communication link between the master station and the slave station, realize protocol self-testing, save the deployment overhead of other nodes for normal bus communication, and improve the automation efficiency of the testing process.

[0028] In one embodiment, upon receiving a start signal from the host computer, the master station and slave station are controlled to execute an Ethernet test procedure to obtain the test results of the master station and slave station, including: When the start signal from the host computer is received, the master station and slave station are controlled to perform physical layer tests and obtain the physical layer test results. Control the master station and slave station to perform basic network protocol tests and obtain basic communication test results; Control the master station and slave station to perform protocol data interaction tests and obtain the interaction test results.

[0029] Understandably, the processor can be tested in the following order: physical layer testing, basic network protocol testing, and protocol data interaction testing.

[0030] Specifically, physical layer testing involves configuring the link polarity and auto-negotiation attributes of the PHY chip through the MDIO (Management Data Input / Output) interface, and verifying the validity of the physical link configuration by reading the pin status and PHY status register.

[0031] Basic network protocol testing involves conducting a period of ordinary TCP (Transmission Control Protocol) or UDP (User Datagram Protocol) communication tests based on a valid physical link. During this period, the validity of the MAC address (Media Access Control Address), IP address (Internet Protocol Address), and plaintext data of the communication data are checked.

[0032] Protocol data interaction testing refers to the process where, based on the target protocol type in the startup signal, the bootloader selects and loads the corresponding industrial Ethernet master and slave protocol stacks; a real-time communication link is established via a dedicated industrial Ethernet network to perform periodic process data interaction; and the master protocol stack monitors the jitter of the communication cycle and the validity of the process data. The processor can generate a comprehensive test report based on the above-mentioned tiered test results and send it back to the host computer.

[0033] In this embodiment, a complete testing loop is formed, from the lowest physical layer test to the basic network protocol test, and then to the top-level protocol data interaction test. Since the master station and the slave station are on the same PCBA board, they can be tested by the same processor to complete the protocol self-test.

[0034] In one embodiment, upon receiving a start signal from the host computer, the master station and slave station are controlled to perform physical layer testing and obtain the physical layer test results, including: Configure the link status output polarity of the master transceiver through the first MDIO interface, and read the connection data through the first MDIO interface to obtain the physical link status of the master and slave stations. Configure the link status output polarity of the slave transceiver through the second MDIO interface, and read the connection data through the second MDIO interface to obtain the physical link status between the slave and master stations.

[0035] The link status refers to the physical layer connection status. When the network cables of two devices are correctly connected and their network port settings match (such as speed and duplex mode), the transceiver chip will establish a "Link Up" state. The transceiver (PHY) chip is a physical layer interface chip, which converts the MCU's digital signals into analog signals transmitted over the network cable, and handles link establishment, collision detection, etc.

[0036] Specifically, a specific bit in the PHY chip's internal register can be used to toggle the output polarity of its LINK status indicator pin. The processor configures and reads the state of the PHY chip's internal register via MDIO, thus configuring the transceiver's link status output polarity. Different master and slave stations may have different definitions of the active level. Through software configuration, it can be ensured that regardless of the PCBA hardware design, the LINK status signal ultimately sent to the processor can be correctly interpreted, thus providing flexibility and avoiding compatibility issues caused by fixed hardware designs. For example, if configured to be active high, the link is normal when the processor reads a high level; otherwise, the link is disconnected.

[0037] The processor configures a register of the master PHY through the first MDIO interface, and subsequently reads the link status register of the master PHY through the first MDIO interface, thereby obtaining the physical link status between the master PHY and the slave PHY as perceived by the master PHY. Similarly, the processor configures a register of the master PHY through the second MDIO interface, and subsequently reads the link status register of the slave PHY through the second MDIO interface, thereby obtaining the physical link status between the slave PHY and the master PHY as perceived by the slave PHY.

[0038] In this embodiment, the link status output polarity of the master transceiver is configured through the MDIO interface, and the MDIO interface level is read to obtain the connection status between the master and slave stations. This enables the determination of whether the connection between the processor and the master and slave stations is valid, thereby achieving Ethernet self-test.

[0039] In one embodiment, upon receiving a start signal from the host computer, the master station and slave station are controlled to perform physical layer testing and obtain the physical layer test results, including: Configure the master transceiver of the master station in the first specific mode and configure the slave transceiver of the slave station in the compatibility mode. When the link between the master station and the slave station is auto-negotiating, read the peer configuration of the slave transceiver. When the peer configuration is in the first specific mode, it is determined that the auto-negotiation between the master station and the slave station is successful. Configure the slave transceiver in the second specific mode and the master transceiver in the compatibility mode. When the link between the master and slave stations is auto-negotiating, read the peer configuration of the master transceiver. When the peer is set to the second specific mode, it is determined that the auto-negotiation between the slave and master stations is successful.

[0040] The first specific mode configures the master transceiver, and the second specific mode configures the slave transceiver. Both the first and second specific modes support, but are not limited to, 10M, 100M, full-duplex, and half-duplex communication capabilities. The compatibility mode encompasses all capabilities of the local end, designed to ensure the ability to receive any specific mode requested by the other end and to create an ideal, controlled testing environment.

[0041] Specifically, the processor configures the master transceiver of the master station to operate in 10M, 100M, full-duplex, or half-duplex mode, and configures the slave transceiver of the slave station to operate in compatibility mode. When the link between the master station and the slave station is in auto-negotiation mode, the peer configuration of the slave transceiver is stored in the link partner capability register of the slave transceiver. Then, the master station configuration is read from the link partner capability register of the slave transceiver. When the peer configuration is in the first specific mode, the auto-negotiation between the master station and the slave station is successful.

[0042] Similarly, the processor configures the slave transceiver in 10M, 100M, full-duplex or half-duplex mode, and configures the master transceiver in compatibility mode. When the link between the master and slave stations is auto-negotiating, the processor reads the slave configuration received by the master transceiver. When the slave is set to the second specific mode, it determines that the auto-negotiation between the slave and the master station is successful.

[0043] In this embodiment, the processor can be configured with both a master station and a slave station simultaneously. One station can be configured in a specific mode, while the other can be configured in a compatible mode and perform auto-negotiation. This enables efficient and automated bidirectional auto-negotiation of the Ethernet link, saving the deployment overhead of other nodes in normal bus communication and improving the automation efficiency of the testing process.

[0044] In one embodiment, the master station and slave station are controlled to perform basic network protocol tests to obtain basic communication test results, including: The master station sends the first data frame to the slave station through the master station's network port; When a data frame received from the slave station matches the first data frame, it is determined that the communication between the master station and the slave station is normal. The slave station is controlled to send the second data frame to the master station through the slave station's network port; When a data frame received from the master station matches a second data frame, it is determined that communication between the slave station and the master station is normal.

[0045] The system consists of a master station network port and a slave station network port, which are connected to each other. The contents of the first and second data frames are different. The first data frame contains the slave station's MAC address (destination MAC address), the master station's MAC address (source MAC address), the slave station's IP address (destination IP address), the destination port (slave station's port), and plaintext. The second data frame contains the master station's MAC address (destination MAC address), the slave station's MAC address (source MAC address), the slave station's IP address (destination IP address), the destination port (slave station's port), and plaintext.

[0046] The processor connects to both the master and slave stations via Ethernet peripherals. These Ethernet peripherals include switches.

[0047] Specifically, the processor controls the master station to generate the first data frame, and the master station sends the first data frame to the slave station through the master station's network port. The processor receives data frames from the slave station. When the data frame received by the slave station matches the first data frame, that is, when the slave station's MAC (destination MAC), master station's MAC (source MAC), slave station's IP (destination IP), destination port (slave station's port), and plaintext are all consistent, it is determined that the communication between the master station and the slave station is normal.

[0048] Similarly, the processor controls the slave station to generate a second data frame, and the slave station sends the second data frame to the master station through the slave station's network port. The processor receives data frames from the master station. When the data frame received from the master station matches the second data frame, that is, when the master station MAC (destination MAC), slave station MAC (source MAC), slave station IP (destination IP), destination port (slave station port), and plaintext are all consistent, it is determined that the communication between the master station and the slave station is normal.

[0049] In this embodiment, the processor controls the master station and slave station to send data frames respectively, and receives data frames from the other end to determine whether the communication is normal. This enables the master station and slave station to perform network self-testing, saving the deployment overhead of other nodes in normal bus communication and improving the automation efficiency of the testing process.

[0050] In one embodiment, the master station and slave station are controlled to perform protocol data interaction tests to obtain the interaction test results, including: Start the bootloader, which reads the target protocol from the boot signal and loads the target protocol. Switch both the master and slave stations to the target protocol; Based on the target protocol, establish communication connections between the master station and the slave station respectively and perform data exchange. Receive the exchange data between the master station and the slave station and monitor the jitter and validity of the exchange data.

[0051] Specifically, the processor starts the bootloader, which reads the target communication protocol specified in the startup signal and finds the corresponding protocol image partition from FLASH. It then moves the protocol stack and data from this partition to the execution area in RAM, begins running the protocol stack, and initializes the Ethernet peripherals. The processor switches the master station to the target protocol and vice versa. Thus, the protocol stack, acting as either the master or slave station, establishes a real-time communication link with the peer. Taking master station mode as an example, the protocol stack performs a network scan, discovers slave devices, allocates addresses, configures parameters, and synchronizes communication cycles, eventually entering a stable data exchange state. The master station outputs data to the slave station, which receives the data, executes its logic, and then returns input data (such as status feedback) to the master station. The processor checks for periodic jitter in the communication data and verifies its validity. Slave station mode is similar and will not be elaborated upon here.

[0052] In this embodiment, a bootloader is started, and the self-test process of industrial Ethernet is realized through a single hardware platform, which saves the deployment overhead of other nodes in normal bus communication and improves the automation efficiency of the test process.

[0053] In one embodiment, traditional master and slave testing involves deploying complete bus nodes and preparing corresponding master stations and test software for different industrial Ethernet protocols. Ethernet master stations have requirements for operating systems and network interface cards (NICs), and the test software needs to be compatible with various industrial Ethernet frameworks. Material and PCBA switching increases time overhead and carries the risk of misconnections, making automation difficult. The purpose of this embodiment is to simplify the PCBA testing process by converting off-chip material and software deployment to on-chip self-testing as much as possible.

[0054] Therefore, this embodiment provides a self-testing software framework that deploys industrial Ethernet master and slave protocols on a single embedded processor. Using this framework, the test fixture or test software informs the MCU of the industrial Ethernet type being tested. The software periodically encapsulates the corresponding protocol stack data and outputs it externally, parsing the input messages to form the protocol stack. The test results are referenced to the accuracy of the message text, the error register of the dedicated industrial Ethernet peripheral, and the status register of the PHY chip. After a period of data interaction, the results are fed back to the host test computer.

[0055] from Figure 1 As shown in the topology, the PCBA under test is both a master node and a slave node, and is connected to the physical interface inside the board only by using a network cable or fixture.

[0056] The testing process generally consists of three steps: MDIO, standard Ethernet MII interface (Media Independent Interface), and industrial Ethernet application. The example will be based on an MCU processor.

[0057] The processor starts the test process based on the start signal from the host computer or test fixture.

[0058] The first step is to configure the LINK polarity and PHY auto-negotiation attributes through MDIO, and then verify the validity of the configuration through the pin status and PHY status register.

[0059] Connection status: The LINK polarity on the PCBA network is affected by the PHY address. The phylink output polarity is configured through MDIO. When the connection is valid, the MCU can directly read the link IO status to determine whether the connection is valid.

[0060] Self-negotiation: Configure the PHY1 Advertisement register via MDIO to adjust the local capability to 10M / 100M / full-duplex / half-duplex, and enable full-mode development for the PHY2 local capability. Check if the Link Partner Ability register matches the previously configured PHY1 capability. Reverse testing: Configure the PHY2 local capability and check the PHY1 peer capability.

[0061] The second step involves a period of normal Ethernet TCP / UDP communication, during which the MAC address, IP address, and plaintext validity are checked.

[0062] Protocol stack: Main station network port -> Virtual MAC1 -> IP1 -> Port 1 (Network Layer) From the network port of the station: Virtual MAC2: IP2: Port 2 (Network Layer) First round: The master station sends data via its network port, and the slave station receives data via its network port. The test program checks the destination MAC address, source MAC address, destination IP address, source IP address, port, and plaintext of the data frames (round number). Second round: The main station sends and receives data via its network port. The test program checks the destination MAC address, source MAC address, destination IP address, source IP address, port, and plaintext (round number) of the data frame. After several rounds of looping, the program jumps to the protocol selection stage.

[0063] The third step involves protocol selection. The bootloader first selects and loads the corresponding industrial Ethernet master / slave protocol stack based on the selection information from the test host computer or test fixture. A link is established through a dedicated industrial Ethernet peripheral, enabling the corresponding real-time functions and exchanging data. During this process, the master protocol stack checks for cycle jitter and the validity of the process data.

[0064] Specifically, the bootloader is executed when the MCU starts, and the loaded content can be changed through hardware signals or the host computer.

[0065] Startup process: The MCU starts from a fixed boot area, checks the hardware signals or the image information recorded in the FLASH, moves the protocol stack of the corresponding partition of the FLASH to the execution area, checks the validity of the image, and then jumps to the execution area.

[0066] In this embodiment, a network self-test method is used to test the effectiveness of the Ethernet PCBA, saving the deployment overhead of other nodes for normal bus communication and improving the automation efficiency of the test process. Experiments were conducted on the five-axis low-voltage driver PCBA, and destructive experiments on network components were successfully detected and reported. Under normal circuit conditions, communication and feedback results were also successfully achieved.

[0067] In one embodiment, an Ethernet self-test method is applied to a processor in an Ethernet self-test device, the device including a master station, a slave station, and a processor; the master station and the slave station are located on the same PCBA board under test, and the master station's master port and the slave station's slave port are connected via a network cable or fixture; the processor is connected to the master station and the slave station respectively via Ethernet peripheral interfaces; including: Step (a1): When the start signal from the host computer is received, the link status output polarity of the master transceiver of the master station is configured through the first MDIO interface, and the connection data is read through the first MDIO interface to obtain the physical link status of the master station and the slave station.

[0068] Step (a2): Configure the link status output polarity of the slave transceiver through the second MDIO interface, and read the connection data through the second MDIO interface to obtain the physical link status of the slave and master stations.

[0069] Step (a3): Configure the master transceiver of the master station in the first specific mode and configure the slave transceiver of the slave station in the compatibility mode. When the link between the master station and the slave station is auto-negotiating, read the peer configuration of the slave transceiver. When the peer configuration is in the first specific mode, determine that the auto-negotiation between the master station and the slave station is successful.

[0070] Step (a4): Configure the slave transceiver in the second specific mode and configure the master transceiver in the compatibility mode. When the link between the master and slave stations is auto-negotiating, read the peer configuration of the master transceiver. When the peer is set to the second specific mode, determine that the auto-negotiation between the slave and master stations is successful.

[0071] Step (a5): Control the master station to send the first data frame to the slave station through the master station network port.

[0072] Step (a6): Receive data frames from the slave station. When the data frame received from the slave station matches the first data frame, it is determined that the communication from the master station to the slave station is normal.

[0073] Step (a7): Control the slave station to send the second data frame to the master station through the slave station network port.

[0074] Step (a8): Receive data frames from the master station. When the data frame received from the master station matches the second data frame, it is determined that the communication from the slave station to the master station is normal.

[0075] Step (a9): Start the bootloader, read the target protocol from the startup signal and load the target protocol.

[0076] Step (a10): Switch the master station and slave station to the target protocol respectively.

[0077] Step (a11): Establish communication connections between the master station and the slave station based on the target protocol and perform data interaction; receive the interaction data between the master station and the slave station and monitor the jitter and validity of the interaction data.

[0078] Step (a12) feeds back to the host computer the physical link status between the master station and the slave station, the physical link status between the slave station and the master station, the auto-negotiation results between the master station and the slave station, the auto-negotiation results between the slave station and the master station, the communication test results between the master station and the slave station, the communication test results between the slave station and the master station, and the interaction data between the master station and the slave station, and monitors the jitter and validity of the interaction data.

[0079] In this embodiment, traditional Ethernet testing requires the deployment of external network devices (such as switches and routers) and multiple independent nodes. However, by integrating the master station and slave station on the same PCBA board and directly connecting their network ports to form an internal loopback test path, the deployment overhead of other nodes for normal bus communication is saved, reducing costs and space requirements. The processor automatically executes the entire test process, reducing manual intervention. The host computer only needs to send a start signal to obtain the results, which is suitable for batch testing on the production line and improves testing efficiency.

[0080] It should be understood that although steps (a1) through (a12) are shown sequentially according to their numbers, these steps are not necessarily executed in the order indicated by the arrows or numbers. Unless explicitly stated herein, there is no strict order requirement for the execution of these steps, and they can be executed in other orders. Furthermore, Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0081] In one embodiment, an Ethernet self-test device is characterized in that the device includes a master station, a slave station, and a processor; the master station and the slave station are located on the same PCBA board under test, and the master station's master port and the slave station's slave port are connected; the processor is connected to the master station and the slave station respectively through an Ethernet peripheral interface; when the processor executes a computer program, it implements the steps of the above-described method embodiments.

[0082] For specific limitations regarding the Ethernet self-test device, please refer to the limitations on the Ethernet self-test method above, which will not be repeated here. Each module in the aforementioned Ethernet self-test device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0083] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method embodiments.

[0084] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the above-described method embodiments.

[0085] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0086] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An Ethernet self-test method, characterized by, A processor applied to an Ethernet self-checking device, the device comprising a master station, a slave station and the processor; the master station and the slave station are located on the same PCBA board to be tested, and a master station network port of the master station and a slave station network port of the slave station are connected; The processor is connected with the master station and the slave station through an Ethernet peripheral interface; the method comprises: When receiving a starting signal of an upper computer, controlling the master station and the slave station to execute an Ethernet test process to obtain test results of the master station and the slave station; feeding back the test results to the upper computer.

2. The method of claim 1, wherein, The master station network port and the slave station network port are connected through a network cable or a jig.

3. The method of claim 1, wherein, The step of, when receiving the starting signal of the upper computer, controlling the master station and the slave station to execute the Ethernet test process to obtain the test results of the master station and the slave station, comprises: When receiving the starting signal of the upper computer, controlling the master station and the slave station to perform a physical layer test to obtain a physical layer test result; controlling the master station and the slave station to perform a basic network protocol test to obtain a basic communication test result; controlling the master station and the slave station to perform a protocol data interaction test to obtain an interaction test result.

4. The method of claim 3, wherein, The step of, controlling the master station and the slave station to perform the physical layer test to obtain the physical layer test result, comprises: configuring a link state output polarity of a master station transceiver of the master station through a first MDIO interface, and performing connection data reading through the first MDIO interface to obtain physical link states of the master station and the slave station; configuring a link state output polarity of a slave station transceiver of the slave station through a second MDIO interface, and performing connection data reading through the second MDIO interface to obtain physical link states of the slave station and the master station.

5. The method of claim 3, wherein, The step of, when receiving the starting signal of the upper computer, controlling the master station and the slave station to perform the physical layer test to obtain the physical layer test result, comprises: configuring the master station transceiver in a first specific mode and configuring the slave station transceiver in a compatible mode, when the link of the master station and the slave station performs self negotiation, reading a peer configuration of the slave station transceiver, and when the peer configuration is the first specific mode, determining that the master station to the slave station self negotiation is successful; configuring the slave station transceiver in a second specific mode and configuring the master station transceiver in a compatible mode, when the link of the master station and the slave station performs self negotiation, reading a peer configuration of the master station transceiver, and when the peer configuration is the second specific mode, determining that the slave station to the master station self negotiation is successful.

6. The method of claim 3, wherein, The step of, controlling the master station and the slave station to perform the basic network protocol test to obtain the basic communication test result, comprises: controlling the master station to send a first data frame to the slave station through the master station network port; receiving a data frame from the slave station, and when the data frame received from the slave station matches the first data frame, determining that the communication from the master station to the slave station is normal; controlling the slave station to send a second data frame to the master station through the slave station network port; receiving a data frame from the master station, and determining that communication from the slave station to the master station is normal when the data frame received from the master station matches the second data frame.

7. The method of claim 3, wherein, The method further comprises: starting a boot program, reading a target protocol in the start signal through the boot program, and loading the target protocol; switching the master station and the slave station to the target protocol respectively; establishing a communication connection between the master station and the slave station based on the target protocol, and performing data interaction, receiving interaction data between the master station and the slave station, and monitoring jitter and validity of the interaction data.

8. An Ethernet self-test apparatus, characterized by: The device comprises a master station, a slave station, and a processor; the master station and the slave station are located on the same PCBA board to be tested, a master station network port of the master station and a slave station network port of the slave station are connected; the processor is connected with the master station and the slave station through an Ethernet peripheral interface respectively; The processor executes the computer program to implement the steps of the method in any one of claims 1 to 7.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 7.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 7.

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