Identification conversion method and device, electronic equipment, chip and storage medium
By optimizing the address translation of the NAT submodule through a two-level hash table structure and an entry eviction mechanism, the problem of low matching efficiency of the NAT submodule is solved, achieving efficient address and port translation, meeting communication requirements and reducing system power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-04-10
Smart Images
Figure CN121842151A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of communication technology, and in particular to an identifier conversion method, apparatus, electronic device, chip, and storage medium. Background Technology
[0002] In the field of communications, the NAT (Network Address Translation) submodule, which is responsible for address translation across networks, needs to complete the matching and translation of addresses and ports in TCP / IP headers within a certain time when dealing with the address translation needs of thousands of streams from multiple local area network hosts. However, the matching efficiency of the NAT submodule is currently low and it is difficult to meet the communication requirements. Summary of the Invention
[0003] This disclosure provides an identifier conversion method, apparatus, electronic device, chip, and storage medium to solve problems in the related art.
[0004] A first aspect of this disclosure provides an identifier conversion method, the method comprising: determining a target entry from a plurality of first entries stored in a first storage space and / or a plurality of second entries stored in a second storage space, based on a hash value corresponding to a target message, wherein the linked list depth of the first storage space is less than the linked list depth of the second storage space; and converting the source identifier of the target message into a target identifier indicated by the target entry.
[0005] In some embodiments of this disclosure, determining a target entry from a plurality of first entries stored in a first storage space and / or a plurality of second entries stored in a second storage space based on the hash value corresponding to the target message includes at least one of the following: determining a target entry from a plurality of first entries stored in the first storage space based on a first portion of bits corresponding to the hash value; determining a target entry from a plurality of second entries stored in the second storage space based on a second portion of bits corresponding to the hash value, wherein the number of bits in the second portion of bits is greater than the number of bits in the first portion of bits.
[0006] In some embodiments of this disclosure, determining a target entry from multiple first entries stored in a first storage space and / or multiple second entries stored in a second storage space based on the hash value corresponding to the target message includes: determining a target linked list from multiple first linked lists stored in the first storage space based on a first portion of bits; traversing the multiple first entries included in the target linked list to determine whether there is a first entry that matches the source identifier; if there is a first entry that matches the source identifier, determining the first entry that matches the source identifier as the target entry; if there is no first entry that matches the source identifier, determining the target entry from multiple second entries stored in the second storage space based on a second portion of bits.
[0007] In some embodiments of this disclosure, the method further includes: determining that among the plurality of first entries included in the target linked list, there is no first entry that matches the source identifier; determining that among the plurality of second entries, there is a second entry that matches the source identifier; and adding the second entry to the first storage space.
[0008] In some embodiments of this disclosure, the method further includes: when the remaining capacity of the first storage space is less than or equal to a preset threshold, determining the access frequency corresponding to each of the plurality of first entries; determining at least one entry to be eliminated based on at least one of the remaining capacity of the first storage space and the access frequency corresponding to each of the plurality of first entries; and removing at least one entry to be eliminated from the first storage space.
[0009] In some embodiments of this disclosure, the method further includes: determining the characteristics of the target message, wherein the characteristics of the target message include at least one of source address, destination address, source port, destination port, and transport layer protocol; and determining the hash value corresponding to the target message based on the characteristics of the target message.
[0010] A second aspect of this disclosure provides an identifier conversion apparatus, comprising: a processing module, configured to determine a target entry from a plurality of first entries stored in a first storage space and / or a plurality of second entries stored in a second storage space, based on a hash value corresponding to a target message, wherein the linked list depth of the first storage space is less than the linked list depth of the second storage space; and to convert the source identifier of the target message into a target identifier indicated by the target entry.
[0011] In some embodiments of this disclosure, the processing module is further configured to: determine a target entry from a plurality of first entries stored in a first storage space based on a first portion of bits corresponding to a hash value; and determine a target entry from a plurality of second entries stored in a second storage space based on a second portion of bits corresponding to a hash value, wherein the number of bits in the second portion of bits is greater than the number of bits in the first portion of bits.
[0012] In some embodiments of this disclosure, the processing module is further configured to: determine a target linked list from a plurality of first linked lists stored in a first storage space based on a first portion of bits; traverse a plurality of first entries included in the target linked list to determine whether there is a first entry that matches the source identifier; if there is a first entry that matches the source identifier, determine the first entry that matches the source identifier as the target entry; if there is no first entry that matches the source identifier, determine the target entry from a plurality of second entries stored in a second storage space based on a second portion of bits.
[0013] A third aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.
[0014] A fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this disclosure.
[0015] A fifth aspect of this disclosure provides a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in the first aspect of this disclosure through logic circuits or executing code instructions.
[0016] In summary, the identifier conversion method proposed in this disclosure can determine the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space based on the hash value corresponding to the target message. The linked list depth of the first storage space is less than that of the linked list depth of the second storage space. When the target entry can be found in the first storage space, the query efficiency of the target entry can be improved. Furthermore, the source identifier of the target message can be converted based on the target identifier, which can improve the identifier conversion efficiency.
[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.
[0019] Figure 1 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 1 ; Figure 2 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 2 ; Figure 3 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 3 ; Figure 4A A schematic diagram of a communication architecture provided in an embodiment of this disclosure; Figure 4BA flowchart illustrating a cache management method based on a two-level hash linked list provided in this embodiment of the disclosure; Figure 4C A schematic diagram of a two-level hash linked list provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of an identifier conversion device provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the chip structure provided in an embodiment of this disclosure. Detailed Implementation
[0020] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.
[0021] Integrating Transmission Control Protocol (TCP) / Internet Protocol (IP) hardware acceleration modules into cellular terminals is a key direction in the development of current communication technologies, aiming to improve data processing efficiency, reduce system power consumption, meet high real-time requirements, and meet the high bandwidth requirements of 5G networks.
[0022] Mobile cellular terminals access cellular networks and provide methods such as hotspots and USB tethering to share cellular network traffic with other devices, such as... Figure 4A As shown, tablets, other mobile phones, and computers access the Internet through the network provided by the "Mobile Phone / Communication Module" in the diagram. The "Mobile Phone / Communication Module" can provide the ability to forward TCP / IP packets across networks.
[0023] The NAT (Network Address Translation) submodule, which is responsible for address translation across networks in the TCP / IP protocol hardware acceleration module, needs to complete the matching and address and port translation in the TCP / IP header within a certain time when dealing with the address translation needs of tens of thousands of streams (Sockets) on multiple local area network hosts. However, the matching efficiency of the NAT submodule is currently low and it is difficult to meet the communication requirements.
[0024] Therefore, in order to solve the above problems, this disclosure proposes an identifier conversion method that can provide fast and efficient query capabilities to support the NAT submodule in performing efficient address and port conversion.
[0025] The specific details of this method are as follows.
[0026] Figure 1 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 1 .like Figure 1 As shown, the method may include the following steps.
[0027] Step 101: Based on the hash value corresponding to the target message, determine the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space.
[0028] In some embodiments, the first storage space may be a memory unit deployed on an electronic device or a chip, and the second storage space may be a memory unit existing as a separate chip. For example, the first storage space may be the storage space of Static Random Access Memory (SRAM), and the second storage space may be the storage space of Double Data Rate (DDR) Synchronous Dynamic Random Access Memory.
[0029] In some embodiments, the first storage space may store a plurality of first linked lists, each of which may include at least one first entry, and the second storage space may store a plurality of second linked lists, each of which may include at least one second entry, wherein the depth of the first linked list is less than the depth of the second linked list, wherein the depth of the linked list may refer to the number of entries included in the linked list, for example, the depth of the first linked list may be 64 and the depth of the second linked list may be 2048.
[0030] Alternatively, some of the linked lists in the multiple first linked lists and the multiple second linked lists may not include any entries, i.e., empty linked lists may exist.
[0031] In some embodiments, the method further includes: determining the characteristics of the target message, wherein the characteristics of the target message include at least one of source address, destination address, source port, destination port, and transport layer protocol; and determining the hash value corresponding to the target message based on the characteristics of the target message.
[0032] In some embodiments, the target message may be a message that requires identification conversion. Optionally, the identification may include at least one of address identification, port identification, and transport layer protocol identification (transmission type identification) for conversion.
[0033] In some embodiments, after receiving a message that requires identification conversion, the characteristics of the target message can be obtained from the message header of the target message. The characteristics of the target message can be, for example, a 5-tuple feature, that is, the characteristics of the target message can include at least one of the following: source address, destination address, source port, destination port, and transport layer protocol. The source address can be the address that sends the target message, the destination address can be the address that receives the target message, the source port can be the port that sends the target message, the destination port can be the port that receives the target message, the transport layer protocol can be the protocol type of the message, etc. Alternatively, other characteristics of the target message can also be obtained.
[0034] In some embodiments, the hash value corresponding to the target message can be determined based on the characteristics of the target message. For example, a hash algorithm can be used to take the characteristics of the target message as input data to determine the hash value of the target message.
[0035] In some embodiments, after determining the hash value of the target message, a target linked list matching the hash value of the target message can be queried from the first storage space and / or the second storage space based on the hash value of the target message, and multiple entries included in the target linked list can be traversed to determine the target entry matching the target message.
[0036] In some embodiments, determining a target entry from a plurality of first entries stored in a first storage space and / or a plurality of second entries stored in a second storage space based on the hash value corresponding to the target message includes at least one of the following: determining a target entry from a plurality of first entries stored in a first storage space based on a first portion of bits corresponding to the hash value; determining a target entry from a plurality of second entries stored in a second storage space based on a second portion of bits corresponding to the hash value, wherein the number of bits in the second portion of bits is greater than the number of bits in the first portion of bits.
[0037] In other words, multiple bits corresponding to a hash value can be determined. For example, a hash value can correspond to 32 bits. The value indicated by the 32 bits can be a hash value. The target entry can be determined from multiple first entries stored in the first storage space using the first part of the bits, and / or the target entry can be determined from multiple second entries stored in the second storage space using the second part of the bits.
[0038] The number of bits in the second part and the number of bits in the first part are related to the number of linked lists stored in the first and second storage spaces. For example, when the second storage space is larger than the first storage space, the number of bits in the second part is greater than the number of bits in the first part. For example, if the number of bits in the first part is 6, it can indicate 64 values, and if the number of bits in the second part is 11, it can indicate 2048 values. Therefore, the first storage space can include a maximum of 64 linked lists, and the second storage space can include a maximum of 2048 linked lists. Alternatively, the number of bits in the second part and the number of bits in the first part can be other values, which can be determined based on the actual number of linked lists stored in the first and second storage spaces, or based on the maximum number of linked lists that can actually be stored in the first and second storage spaces.
[0039] In some embodiments, the first part of bits and the second part of bits can be the low-order bits among the multiple bits corresponding to the hash value. For example, the first part of bits can be the low 6 bits among the 32 bits corresponding to the hash value, or the first part of bits can be the low 11 bits among the 32 bits corresponding to the hash value. However, it is not limited to these. It can also be the high-order bits or middle bits among the multiple bits, etc. This disclosure does not limit this.
[0040] Step 102: Convert the source identifier of the target message into the target identifier indicated by the target entry.
[0041] In some embodiments, a target entry may include a first identifier and a second identifier, wherein the first identifier represents the identifier before the identifier conversion, and the second identifier represents the identifier after the identifier conversion. In other words, the target entry may be used to indicate the conversion of the first identifier to the second identifier. For example, taking address conversion as an example, the target entry may be represented as {192.168.1.1, 123.123.123.123}, which indicates the conversion of the identifier 192.168.1.1 to 123.123.123.123, meaning the second identifier can be the target identifier. The first and second identifiers may also include other identifiers, such as port identifiers. The above examples are merely illustrative of the scheme; the actual structure of the first and second identifiers in the entry may also be different.
[0042] In some embodiments, the source identifier of the target message can be converted into the target identifier indicated by the target entry, thereby completing the identifier conversion.
[0043] In some embodiments, the method of this application can be executed by an electronic device, such as a terminal device, a communication device, or a communication module. Furthermore, the method can be executed by a chip, such as a system on a chip (SOC).
[0044] Optionally, when the method is executed by an electronic device, the electronic device may include a first module, a second module, a first storage space, and a second storage space. The first module may be used to calculate the hash value corresponding to the target packet, and the second module may be used to determine the target entry. The second module may read multiple first entries and multiple second entries stored in the first and second storage spaces to determine the target entry and convert the source identifier of the target packet according to the target entry. For example, the first module may be a TCP / IP protocol hardware acceleration module, and the second module may be a NAT submodule. In this case, the hardware acceleration module management program may be responsible for adding or removing (removing / deleting) entries in the first and / or second storage spaces.
[0045] Optionally, when the method is executed by the chip, the chip may be deployed with a first module, a second module, and a first storage space. The first module and the second module on the chip may be connected to the second storage space. Multiple first entries and multiple second entries stored in the first storage space and the second storage space are used to determine a target entry. The source identifier of the target message is converted according to the target entry. Entries may be added or removed (removed / deleted) in the first storage space and / or the second storage space.
[0046] In summary, the above embodiments of this application can determine the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space based on the hash value corresponding to the target message. The depth of the linked list stored in the first storage space is less than the depth of the linked list stored in the second storage space. When the target entry can be queried from the first storage space, the query efficiency of the target entry can be improved. Furthermore, the source identifier of the target message can be converted based on the target typology, which can improve the identifier conversion efficiency.
[0047] Figure 2 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 2 .like Figure 2 As shown, the method may include the following steps.
[0048] Step 201: Determine the target linked list from the multiple first linked lists stored in the first storage space based on the first part of the bits.
[0049] In some embodiments, the first storage space may include a portion of the linked list stored in the second storage space, or the first storage space may include a portion of the table entries stored in the second storage space. That is, the first storage space may serve as a cache space for the second storage space, and the first storage space may cache a portion of the data in the second storage space.
[0050] Optionally, the first storage space may cache frequently accessed table entries or linked lists from the second storage space. A high access frequency can mean that the table entry or linked list is queried a high number of times, that is, the table entry or linked list is the target table entry or target linked list a high number of times.
[0051] In some embodiments, when querying a target entry, the first set of bits can be used to query the target entry from the first storage space. Since the number of entries stored in the first storage space is reduced and the depth is smaller, the query efficiency of the target entry can be improved when the target entry can be queried from the first storage space. Furthermore, the source identifier of the target message can be converted according to the target typology, which can improve the identifier conversion efficiency.
[0052] In some embodiments, the target linked list can be determined by determining the value indicated by the first part of the bits. For example, if the first part of the bits is 000101, then the value indicated by the first part of the bits is 5, and the first linked list with the index value of 5 in the first storage space can be determined as the target linked list.
[0053] Step 202: Traverse the multiple first entries in the target linked list to determine whether there is a first entry that matches the source identifier.
[0054] In some embodiments, after determining the target linked list, the multiple first entries included in the target linked list can be traversed, wherein matching the first entry with the source identifier can mean that the first identifier indicated by the first entry (the identifier before identifier conversion) is the same as the source identifier of the target message.
[0055] For example, if there are two first entries {192.168.1.100, 123.123.xxx.xxx} and {192.168.1.102, 180.101.xxx.xxx}, and the destination address in the source identifier of the target message is 192.168.1.100, then {192.168.1.100, 123.123.xxx.xxx} can be identified as the target entry.
[0056] Step 203: If a first table entry that matches the source identifier exists, the first table entry that matches the source identifier is determined as the target table entry.
[0057] In some embodiments, if there is a first entry among the multiple first entries included in the target linked list that matches the source identifier, the first entry that matches the source identifier can be used as the target entry, and the identifier conversion can be performed based on the target entry.
[0058] Step 204: If no first entry matches the source identifier, determine the target entry from a plurality of second entries stored in the second storage space based on the second part of the bits.
[0059] In some embodiments, if there is no first entry matching the source identifier among the multiple first entries included in the target linked list, the target entry can be determined from the multiple second entries stored in the second storage space based on the second part of the bits. The scheme of determining the target entry from the multiple second entries stored in the second storage space using the second part of the bits is the same as the scheme of determining the target entry from the multiple first entries stored in the second storage space using the first part of the bits, and will not be described again here.
[0060] In some embodiments, the method further includes: determining that among the plurality of first entries included in the target linked list, there is no first entry that matches the source identifier; determining that among the plurality of second entries, there is a second entry that matches the source identifier; and adding the second entry to the first storage space.
[0061] In other words, if the target entry does not exist in the first storage space but exists in the second storage space, the target entry in the second storage space can be added to the first storage space. For example, if the target list exists in the first storage space but the target entry does not exist, the target entry in the second storage space can be added to the target list in the first storage space, which can facilitate quick querying of the target entry later.
[0062] Alternatively, if the target entry does not exist in the first storage space but exists in the second storage space, and the target entry in the second storage space is accessed more frequently, the target entry in the second storage space can be added to the first storage space.
[0063] In some embodiments, when the target linked list in the first storage space that matches the hash value of the target message is empty, the target linked list that matches the hash value of the target message can be determined from the second storage space. When the target linked list in the first storage space that matches the hash value of the target message is empty, the identifier conversion of the current message can be skipped. Alternatively, when at least one first entry in the target linked list in the first storage space that matches the hash value of the target message does not contain a target entry that matches the target message, the target entry that matches the target message can be determined from the second storage space. When at least one second entry in the target linked list in the second storage space that matches the hash value of the target message does not contain a target entry that matches the target message, the identifier conversion of the current message can be skipped.
[0064] In summary, the above embodiments of this disclosure can prioritize querying target entries from the first storage space. Since the linked list stored in the first storage space has a small depth and can store frequently accessed entries, prioritizing querying target entries from the first storage space can improve query efficiency. Furthermore, if the target entry is not found in the first storage space, it can be queried from the second storage space, which can meet the identifier conversion requirements. Additionally, the linked list stored in the first storage space can be updated, which can meet the query requirements for different entries at different times and improve the user experience.
[0065] Figure 3 A flowchart illustrating an identifier conversion method provided in this embodiment of the present disclosure. Figure 3 .like Figure 3 As shown, based on Figure 2 The illustrated embodiment shows that the method includes the following steps.
[0066] Step 301: If the remaining capacity of the first storage space is less than or equal to a preset threshold, determine the access frequency corresponding to each of the multiple first entries.
[0067] In some embodiments, when the remaining capacity of the first storage space is small, the first storage space can be cleaned up to save entries with higher access frequency to meet the needs of identity conversion. Therefore, when the remaining capacity of the first storage space is small, the access frequency corresponding to each of the multiple first entries stored in the first storage space can be determined.
[0068] Step 302: Determine at least one entry to be evicted based on at least one of the remaining capacity of the first storage space and the access frequency corresponding to each of the multiple first entries.
[0069] In some embodiments, the number of entries to be evicted, or the number of linked lists to be evicted, can be determined based on the remaining capacity of the first storage space. At least one entry to be evicted can be determined based on the access frequency of each of the multiple first entries. Optionally, entries with lower access frequencies can be identified as those to be evicted.
[0070] Step 303: Remove at least one entry to be evicted from the first storage space.
[0071] In some embodiments, after determining at least one entry to be replaced, at least one entry to be replaced can be removed from the first storage space; or after determining at least one list to be replaced, at least one list to be replaced can be removed from the first storage space.
[0072] Optionally, when a new entry needs to be added to the first storage space and the remaining capacity of the first storage space is less than or equal to a preset threshold, at least one entry to be eliminated can be triggered. Alternatively, at least one entry to be eliminated can be triggered periodically. Or, multiple first entries stored in the first storage space can be updated periodically. That is, the access frequency, popularity, etc. of multiple second entries included in the second storage space can be determined periodically. Then, second entries with higher access frequency and popularity can be updated to the first storage space, and first entries with lower access frequency and popularity can be eliminated.
[0073] In summary, the above embodiments of this application can update the first storage space, maintain the table entries stored in the first storage space, keep the first storage space storing table entries with high access frequency, improve the success rate of querying the target table entry in the first storage space, and improve the query efficiency of the target table entry.
[0074] The technical solutions of this disclosure will be further described in detail below with reference to specific application embodiments.
[0075] The following is a cache management method based on a two-level hash linked list provided by an embodiment of this disclosure. It offers a cache management implementation scheme for a NAT submodule, providing fast and efficient query capabilities to support the NAT submodule in efficiently performing address and port translation. Figure 4B As shown, the complete content of the scheme is as follows.
[0076] 1. The TCP / IP hardware acceleration module has a built-in hash calculation submodule, which calculates the hash value of the input packet based on its characteristics (such as a 5-Tuple). Hash algorithms such as Toeplitz and CRC32C can be selected.
[0077] 2. The NAT submodule is further subdivided into a NAT matching and translation submodule and a cache management submodule. This invention does not involve the specific details of NAT translation, but only describes the design of the cache management submodule. For ease of explanation, the following... Figure 4C The lengths of the two-level hash linked lists are defined as 64 and 2048 respectively.
[0078] A hash linked list with a depth of 2048 is located in Double Data Rate (DDR) memory and is responsible for managing NAT entries in DDR. To facilitate hardware reading, the linked list pointed to by each hash value is implemented as an array. The hardware sets the maximum number of arrays of accessible DDR Entry as needed. A hash chain with a depth of 64 is located in SRAM and is responsible for managing the NAT entries in SRAM. All NAT entries are stored in a linked list structure. SRAM has limited capacity, so the maximum cache size of SRAM NAT entries does not exceed the SRAM cache limit. The hardware acceleration module provides swap-in and swap-out operations for NAT entries between SRAM and DDR. The hardware acceleration module manager is responsible for adding NAT entries to the DDR Hash list; When a message is sent to the NAT module, the lower 6 bits of the Hash Value are first used as the index value of the SRAM Hash linked list to try to find a matching NAT entry in the SRAM. If the search in SRAM fails, take the lower 11 bits of the message hash value as the index value of the DDR hash list and try to find a matching NAT entry in DDR. If the lookup is successful, the DDR Entry is loaded into SRAM and added to the corresponding SRAM hash chain. If the SRAM cache becomes full during this process, the hardware will prematurely evict the Entry.
[0079] In summary, the examples disclosed above, provided that the system memory is sufficient to store all NAT entries, allow the NAT submodule to support unrestricted address translation requirements for sockets, thus enabling more LAN devices to access the cellular network for internet access. Cellular terminals complete address translation within a defined timeframe, without increasing the socket's round-trip time (RTT), and the uplink and downlink speeds of LAN host internet applications are unaffected by the NAT submodule. Furthermore, by offloading TCP / IP packet forwarding processing from the CPU to the TCP / IP hardware acceleration module, packet forwarding capabilities are significantly improved and device power consumption is noticeably reduced.
[0080] Figure 5 This is a schematic diagram of the structure of an identifier conversion device 500 provided in an embodiment of this disclosure. Figure 5 As shown, the device includes: a processing module 510, configured to determine a target entry from a plurality of first entries stored in a first storage space and / or a plurality of second entries stored in a second storage space based on the hash value corresponding to the target message, wherein the linked list depth of the first storage space is less than the linked list depth of the second storage space; and to convert the source identifier of the target message into a target identifier indicated by the target entry.
[0081] In some embodiments, the processing module is further configured to: determine a target entry from a plurality of first entries stored in a first storage space based on a first portion of bits corresponding to a plurality of bits in a hash value; and determine a target entry from a plurality of second entries stored in a second storage space based on a second portion of bits corresponding to a plurality of bits in a second storage space, wherein the number of bits in the second portion of bits is greater than the number of bits in the first portion of bits.
[0082] In some embodiments, the processing module is further configured to determine a target linked list from a plurality of first linked lists stored in a first storage space based on a first portion of bits; traverse a plurality of first entries included in the target linked list to determine whether there is a first entry that matches the source identifier; if there is a first entry that matches the source identifier, determine the first entry that matches the source identifier as the target entry; if there is no first entry that matches the source identifier, determine the target entry from a plurality of second entries stored in a second storage space based on a second portion of bits.
[0083] In some embodiments, the processing module is further configured to determine that among the plurality of first entries included in the target linked list, there is no first entry that matches the source identifier; determine that among the plurality of second entries, there is a second entry that matches the source identifier; and add the second entry to the first storage space.
[0084] In some embodiments, the processing module is further configured to, when the remaining capacity of the first storage space is less than or equal to a preset threshold, determine the access frequency corresponding to each of the plurality of first entries; determine at least one entry to be eliminated based on at least one of the remaining capacity of the first storage space and the access frequency corresponding to each of the plurality of first entries; and remove at least one entry to be eliminated from the first storage space.
[0085] In some embodiments, the processing module is further configured to determine the characteristics of the target message, wherein the characteristics of the target message include at least one of source address, destination address, source port, destination port, and transport layer protocol; and determine the hash value corresponding to the target message based on the characteristics of the target message.
[0086] In summary, the identifier conversion device 500 can determine the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space based on the hash value corresponding to the target message. The depth of the linked list stored in the first storage space is less than the depth of the linked list stored in the second storage space. When the target entry can be found in the first storage space, the query efficiency of the target entry can be improved. Furthermore, the identifier conversion efficiency can be improved by converting the source identifier of the target message based on the target identifier.
[0087] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.
[0088] Figure 6This is a block diagram illustrating an electronic device 600 for implementing the above-described method according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, computer, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.
[0089] Reference Figure 6 The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.
[0090] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.
[0091] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of such data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0092] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.
[0093] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
[0094] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.
[0095] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.
[0096] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.
[0097] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0098] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.
[0099] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of an electronic device 600 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0100] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the above embodiments of this disclosure.
[0101] Figure 7 This is a schematic diagram illustrating the structure of a chip 700 for implementing the above method according to an exemplary embodiment. (Refer to...) Figure 7 The chip 700 includes a communication interface 701 and at least one processor 702. The communication interface 701 is used to receive signals input to the chip 700 or signals output from the chip 700. The processor 702 communicates with the communication interface 701 and implements the methods described in the above embodiments of this disclosure through logic circuits or executing code instructions.
[0102] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in at least one embodiment or example.
[0104] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.
[0105] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having at least one wiring (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.
[0106] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0107] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
[0108] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.
[0109] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A method for identifier conversion, characterized in that, The method includes: Based on the hash value corresponding to the target message, the target entry is determined from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space, wherein the linked list depth of the first storage space is less than the linked list depth of the second storage space. The source identifier of the target message is converted into the target identifier indicated by the target entry.
2. The method according to claim 1, characterized in that, The step of determining the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space based on the hash value corresponding to the target message includes at least one of the following: The target entry is determined from a plurality of first entries stored in the first storage space based on the first portion of bits among the plurality of bits corresponding to the hash value. Based on the second part of the bits corresponding to the hash value, the target entry is determined from the multiple second entries stored in the second storage space, wherein the number of bits in the second part of the bits is greater than the number of bits in the first part of the bits.
3. The method according to claim 2, characterized in that, The step of determining the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space based on the hash value corresponding to the target message includes: Based on the first portion of bits, a target linked list is determined from a plurality of first linked lists stored in the first storage space; The target linked list is traversed to determine whether there is a first entry that matches the source identifier. If a first entry matching the source identifier exists, the first entry matching the source identifier is determined as the target entry. If no first entry matching the source identifier exists, the target entry is determined from a plurality of second entries stored in the second storage space based on the second portion of bits.
4. The method according to claim 3, characterized in that, The method further includes: It is determined that among the multiple first entries included in the target linked list, there is no first entry that matches the source identifier; It is determined that among the plurality of second entries, there is a second entry that matches the source identifier; Add the second entry to the first storage space.
5. The method according to claim 1, characterized in that, The method further includes: When the remaining capacity of the first storage space is less than or equal to a preset threshold, the access frequency corresponding to each of the plurality of first entries is determined; Based on at least one of the remaining capacity of the first storage space and the access frequency corresponding to each of the multiple first entries, at least one entry to be eliminated is determined; Remove at least one entry to be phased out from the first storage space.
6. The method according to claim 1, characterized in that, The method further includes: Determine the characteristics of the target message, wherein the characteristics of the target message include at least one of source address, destination address, source port, destination port, and transport layer protocol; Based on the characteristics of the target message, determine the hash value corresponding to the target message.
7. A label conversion device, characterized in that, include The processing module is used to determine the target entry from multiple first entries stored in the first storage space and / or multiple second entries stored in the second storage space according to the hash value corresponding to the target message, wherein the linked list depth of the first storage space is less than the linked list depth of the second storage space. The source identifier of the target message is converted into the target identifier indicated by the target entry.
8. The apparatus according to claim 7, characterized in that, The processing module is also used for at least one of the following: The target entry is determined from a plurality of first entries stored in the first storage space based on the first portion of bits among the plurality of bits corresponding to the hash value. Based on the second part of the bits corresponding to the hash value, the target entry is determined from the multiple second entries stored in the second storage space, wherein the number of bits in the second part of the bits is greater than the number of bits in the first part of the bits.
9. The apparatus according to claim 8, characterized in that, The processing module is also used for: Based on the first portion of bits, a target linked list is determined from a plurality of first linked lists stored in the first storage space; The target linked list is traversed to determine whether there is a first entry that matches the source identifier. If a first entry matching the source identifier exists, the first entry matching the source identifier is determined as the target entry. If no first entry matching the source identifier exists, the target entry is determined from a plurality of second entries stored in the second storage space based on the second portion of bits.
10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.
12. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 6 through logic circuits or executing code instructions.