Communication system and device for energy storage converter and medium

Abstract

The invention provides a communication system and device for an energy storage converter and a medium. The system comprises a micro control unit (MCU), a field programmable gate array (FPGA) and a digital signal processor (DSP), the micro control unit MCU is connected with a data network Ethernet, processes and manufactures a message specification MMS protocol, and exchanges data with the field programmable gate array FPGA through a first communication interface; a field programmable gate array (FPGA) is connected with a control network Ethernet, analyzes an Ethernet MAC frame and sends a transformer substation event GOOSE message oriented to a general object to a digital signal processor (DSP) through a second communication interface; a digital signal processor (DSP) receives and analyzes a transformer substation event GOOSE message oriented to a general object from a field programmable gate array (FPGA), and generates a power control instruction for the energy storage converter according to an analysis result. The invention aims to realize high-reliability and low-cost collaborative optimization of the energy storage converter communication system.

Description

Technical Field

[0001] This invention relates to the field of new energy storage technology, and in particular to a communication system, device and medium for energy storage converters. Background Technology

[0002] The Power Conversion System (PCS) is the core device in an energy storage power station, enabling bidirectional AC / DC power conversion. Its performance directly affects the efficiency and stability of the entire power station. In modern power grid architectures, especially with the large-scale integration of new energy sources, the grid places extremely high demands on the response speed and control precision of energy storage power stations, making the PCS's communication system a critical component. Typical energy storage power stations usually require physical separation of the data network and control network to meet different communication needs and security standards.

[0003] Specifically, the data network is primarily responsible for transmitting equipment start / stop commands and operating status (such as grid connection status, temperature, voltage, current, and other non-real-time data). The communication protocol typically uses the Manufacturing Message Specification (MMS). This type of data does not require high transmission rates, but the protocol stack is relatively complex and requires strong processing capabilities. The control network is used to achieve rapid power dispatch, transmitting key control commands such as active and reactive power. The communication protocol uses Generic Object Oriented Substation Event (GOOSE). To achieve rapid power regulation of the power grid, the GOOSE message transmission cycle is extremely short, as low as 2ms, and even when active and reactive power commands are transmitted in frames, the interval between two frames is only tens of microseconds. According to the latest national standards, the entire process from the Energy Management System (EMS) issuing a power command to the PCS completing a response must be completed within 200ms. Therefore, the PCS must be able to receive and process GOOSE messages at high speed and reliably, ensuring no packet loss and low latency.

[0004] Furthermore, to improve system communication reliability, energy storage power stations generally require redundant structures in both the data network and control network, meaning the PCS needs to support four Ethernet interfaces. To meet these communication requirements, traditional solutions typically employ two processing paths: Firstly, due to the large size of the MMS protocol stack and relatively low real-time requirements, two network ports are usually connected to the Central Processing Unit (CPU). The CPU's powerful processing capabilities are used to parse MMS messages, and then instructions are sent to the Digital Signal Processor (DSP) responsible for core control via internal communication. However, this approach requires configuring the CPU with double data rate synchronous dynamic random access memory (DDR) and Flash memory, significantly increasing hardware costs. Secondly, to meet the extremely high real-time requirements of GOOSE communication, a microcontroller unit (MCU) is typically used to process GOOSE messages separately, and then instructions are forwarded to the DSP via buses such as the Controller Area Network (CAN). While this architecture provides some assurance in terms of real-time performance, there is still a risk of data packet loss when processing multiple frames of GOOSE messages with extremely short intervals (such as a few microseconds), which affects the accuracy of control and the reliability of the system.

[0005] Currently, market competition in the new energy sector is becoming increasingly fierce, and reducing costs and enhancing product competitiveness have become the focus of the industry. Traditional solutions, due to the high cost of CPU subsystems and potential reliability issues with GOOSE communication, are no longer fully adapted to the industry's development needs. Therefore, there is an urgent need to research a new PCS communication system solution that combines low cost, high reliability, and high-speed GOOSE communication capabilities.

[0006] In summary, the existing technology has the following main problems: 1. To achieve complex protocol stack processing and multi-port communication, traditional solutions rely on high-cost CPU systems, resulting in high overall hardware costs for PCS. 2. The method of using MCU to process GOOSE messages and forwarding them to DSP through secondary communication has the risk of packet loss when processing GOOSE frames with extremely high frequency and very small intervals, which affects the real-time performance and accuracy of power control. Summary of the Invention

[0007] The technical problem to be solved by this invention is: In view of the technical problems existing in the prior art, this invention provides a low-cost, high-reliability communication system, device and medium for energy storage converters. It aims to achieve four-port communication function without relying on expensive CPU subsystems, by optimizing hardware architecture and protocol processing flow, and ensure reliable, packet-loss-free transmission of GOOSE messages in a very short time interval, thereby significantly improving product competitiveness.

[0008] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows: A communication system for an energy storage converter includes: a microcontroller unit (MCU), a field-programmable gate array (FPGA), and a digital signal processor (DSP); The microcontroller unit (MCU) is connected to at least one Ethernet channel of the data network, performs communication processing of the Manufacturing Message Specification (MMS) protocol, and exchanges data with the field-programmable gate array (FPGA) through the first communication interface; The field-programmable gate array (FPGA) is connected to at least one Ethernet channel of the control network, receives and parses Ethernet MAC frames, and sends the acquired substation event GOOSE message for general objects to the digital signal processor (DSP) through the second communication interface. The digital signal processor (DSP) receives and parses the general-purpose substation event GOOSE message from the field programmable gate array (FPGA), and generates power control commands for the energy storage converter based on the parsing results.

[0009] As a further improvement to the method of the present invention: the second communication interface is an external memory interface EMIF; the field programmable gate array FPGA writes the received substation event GOOSE message for general objects into the storage space of the external memory interface EMIF, and after completing the writing, sends an interrupt signal to the digital signal processor DSP through general purpose input / output GPIO.

[0010] As a further improvement to the method of the present invention: the field-programmable gate array (FPGA) integrates a circular buffer; the FPGA first stores the substation event GOOSE message received from the Ethernet into the circular buffer, and then writes it sequentially into the storage space of the external memory interface EMIF.

[0011] As a further improvement to the method of the present invention: when the field-programmable gate array (FPGA) writes a substation event GOOSE message for a general object to the external memory interface (EMIF), it adds a packet sequence number and a checksum to each message; after the digital signal processor (DSP) reads the message from the external memory interface (EMIF), it verifies the continuity of the packet sequence number and the correctness of the checksum, and after successful parsing, it returns confirmation information containing the parsed packet sequence number to the FPGA through the external memory interface (EMIF).

[0012] As a further improvement to the method of the present invention: the field programmable gate array (FPGA) determines whether the digital signal processor (DSP) has lost or erroneous message parsing by monitoring the packet sequence number in the confirmation information; if the DSP has lost or erroneous message parsing, a communication anomaly recovery process for the DSP is triggered.

[0013] As a further improvement to the method of the present invention: the first communication interface is a serial peripheral interface (SPI); the microcontroller unit (MCU) is externally connected to a synchronous dynamic random access memory (SDRAM) and internally integrates a tightly coupled memory (TCM) and a static random access memory (SRAM); the MCU deploys the running tasks of the trimmed Manufacturing Message Specification (MMS) protocol stack to different memories for execution according to the priority of the MMS protocol; tasks that meet the first preset condition are deployed to the tightly coupled memory (TCM) for execution, tasks that meet the second preset condition are deployed to the static random access memory (SRAM) for execution, and tasks that meet the third preset condition are deployed to the synchronous dynamic random access memory (SDRAM) for execution.

[0014] As a further improvement to the method of the present invention: the microcontroller unit (MCU) further includes executing a platform-based configuration process, the platform-based configuration process including: Parse the configuration file to obtain multiple sets of configuration information, including one or more of the following: Manufacturing Message Specification (MMS) protocol parameters, GOOSE message protocol parameters for general-purpose substation events, and parameters required for Ethernet MAC filtering. Complete the configuration of the Manufacturing Message Specification (MMS) protocol stack based on the configuration information; The GOOSE message protocol parameters for general-purpose substation events are sent to the digital signal processor (DSP) via the third communication interface to configure the DSP's GOOSE message parsing function for general-purpose substation events. The Ethernet MAC filtering parameters are sent to the field-programmable gate array (FPGA) via the third communication interface to configure the FPGA's Ethernet MAC filtering module to listen for specified GOOSE multicast messages.

[0015] As a further improvement to the method of the present invention: the microcontroller unit (MCU) is connected to two Ethernet ports of the data network, and the two Ethernet ports of the data network are redundant backups of each other; the field programmable gate array (FPGA) is connected to two Ethernet ports of the control network, and the two Ethernet ports of the control network are redundant backups of each other.

[0016] The present invention also provides an energy storage converter, including the aforementioned communication system for the energy storage converter.

[0017] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a microcontroller unit (MCU), performs the platform-based configuration process in the communication system for the energy storage converter.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention replaces the traditional solution that relies on a high-performance CPU by employing a collaborative architecture of a microcontroller unit (MCU), a field-programmable gate array (FPGA), and a digital signal processor (DSP), significantly reducing hardware costs while ensuring communication performance. By utilizing the functional division of the FPGA for control network communication and the MCU for data network communication, the characteristics of each processor unit are fully utilized, achieving optimal resource allocation.

[0019] 2. This invention directly processes substation event GOOSE messages for general-purpose control networks through a field-programmable gate array (FPGA) and interacts with a DSP using a dedicated second communication interface, effectively avoiding the microsecond-level message loss problem caused by MCU forwarding in traditional solutions; furthermore, by combining a ring buffer, data verification, and anomaly recovery mechanisms, a highly reliable real-time communication link is constructed. Attached Figure Description

[0020] Figure 1 This is a communication block diagram of the energy storage converter in an embodiment of the present invention.

[0021] Figure 2 This is a screenshot of a GOOSE message for a substation event oriented towards general objects in an embodiment of the present invention.

[0022] Figure 3 This is a block diagram of the substation event GOOSE message collaborative ring buffer strategy for general objects in an embodiment of the present invention.

[0023] Figure 4 This is a flowchart of the message parsing confirmation and anomaly recovery mechanism in an embodiment of the present invention.

[0024] Figure 5 This is a block diagram of the hierarchical memory and task deployment of the microcontroller unit (MCU) in an embodiment of the present invention.

[0025] Figure 6 This is a flowchart illustrating the software platformization process in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] like Figure 1 As shown, this embodiment provides a communication system for an energy storage converter, including: a microcontroller unit (MCU), a field-programmable gate array (FPGA), and a digital signal processor (DSP); The microcontroller unit (MCU) is connected to at least one Ethernet channel of the data network, performs communication processing of the Manufacturing Message Specification (MMS) protocol, and exchanges data with the field-programmable gate array (FPGA) through the first communication interface. The field-programmable gate array (FPGA) connects to at least one Ethernet channel of the control network, receives and parses Ethernet MAC frames, and sends the acquired substation event GOOSE messages for general objects to the digital signal processor (DSP) through the second communication interface. The digital signal processor (DSP) receives and parses the GOOSE messages of general-purpose substation events from the field-programmable gate array (FPGA), and generates power control commands for the energy storage converter based on the parsing results.

[0028] In this embodiment, the microcontroller unit (MCU) is connected to two Ethernet ports of the data network, which are redundant backups of each other; the field-programmable gate array (FPGA) is connected to two Ethernet ports of the control network, which are also redundant backups of each other.

[0029] In existing technologies, to achieve four independent Ethernet communication functions for energy storage converters, the following two schemes are typically adopted: Scheme 1 uses a single CPU (central processing unit) to implement all four Ethernet channels, but it suffers from limited chip options, high cost, and poor system robustness due to single point of failure; Scheme 2 uses a CPU and a microcontroller unit (MCU) to handle data network and control network communication respectively. Although this achieves functional separation, it suffers from potential packet loss and large transmission delay when general-purpose substation event GOOSE messages are forwarded from the MCU to the digital signal processor (DSP) via the CAN bus, and the system requires the integration of a CPU, MCU, DSP, and FPGA, resulting in high hardware costs.

[0030] This embodiment eliminates the high-cost CPU and refactors and integrates the Manufacturing Message Specification (MMS) and GOOSE protocol processing functions into the DSP and FPGA required for the energy storage converter, supplemented by a low-cost MCU for collaborative scheduling. Specifically, the two Ethernet paths of the data network are implemented by the MCU, which also handles the MMS protocol. The data link is bidirectional: EMS data is parsed by the MCU and sent to the FPGA via SPI, then to the DSP's CPU1 core via EMIF; response data returns along the opposite path. The two Ethernet paths of the control network are implemented by the FPGA, which is responsible for parsing Ethernet MAC frames, while the GOOSE protocol is parsed and processed by the DSP's CPU1 core. The power regulation and start / stop commands of the energy storage converter are executed by the DSP's CPU2 core, while control commands are issued by the CPU1 core. To meet the memory requirements of the MMS protocol stack, the MCU uses external SDRAM to handle non-real-time functions.

[0031] This embodiment constructs a dedicated "FPGA-EMIF-DSP" processing link for GOOSE messages, utilizing the parallel processing capabilities of FPGA hardware and the high bandwidth characteristics of EMIF to fundamentally solve the problem of packet loss at microsecond-level message intervals; for the MMS protocol, it implements protocol processing that traditionally requires a CPU on a low-cost MCU by deeply tailoring the protocol stack and adopting a memory-level task scheduling strategy.

[0032] This embodiment, through systematic architecture reconstruction and functional integration, achieves a significant improvement in GOOSE communication reliability while substantially reducing hardware costs, successfully overcoming the long-standing technical bottleneck in the energy storage converter field where cost and performance cannot be simultaneously achieved. In this embodiment, GOOSE communication involves the FPGA parsing Ethernet packets and transmitting them to the DSP's CPU1, which then parses the GOOSE packets. Figure 2 As shown, in actual energy storage power station sites, when the co-control system sends active and reactive GOOSE messages in two frames, there are two-frame microsecond intervals, or even continuous arrivals without intervals.

[0033] In this embodiment, the second communication interface is the external memory interface EMIF. The field programmable gate array (FPGA) writes the received substation event GOOSE message for general objects into the storage space of the external memory interface EMIF, and after completing the writing, sends an interrupt signal to the digital signal processor (DSP) through general purpose input / output (GPIO).

[0034] In this embodiment, the FPGA integrates a circular buffer. The FPGA first stores the GOOSE messages of general-purpose substation events received from the Ethernet into the circular buffer, and then writes them sequentially into the storage space of the external memory interface EMIF.

[0035] In this embodiment, when the Field Programmable Gate Array (FPGA) writes a GOOSE message for a general-purpose substation event to the External Memory Interface (EMIF), it adds a packet sequence number and a checksum to each message. After reading the message from the EMIF, the Digital Signal Processor (DSP) verifies the continuity of the packet sequence number and the correctness of the checksum. Upon successful parsing, the DSP returns confirmation information containing the parsed packet sequence number to the FPGA via the EMIF.

[0036] In this embodiment, the Field Programmable Gate Array (FPGA) determines whether the Digital Signal Processor (DSP) has lost or erroneous message parsing by monitoring the packet sequence number in the confirmation information; if the DSP has lost or erroneous message parsing, a communication anomaly recovery process for the DSP is triggered.

[0037] In specific application embodiments, to ensure that microsecond-level packets are not lost and that the DSP CPU1 data response is real-time, the following solution is adopted: 1) Real-time reading of GOOSE data is achieved using an interrupt event response mechanism. After the FPGA receives a complete Ethernet packet and writes it to the EMIF storage space, it immediately notifies the DSP's CPU1 core via a GPIO interrupt signal. This interrupt-driven approach enables CPU1 to respond immediately and parse the packet, achieving real-time data reading. In contrast, the traditional polling method has inherent drawbacks: firstly, polling cannot guarantee a hit on the pending packet every time, resulting in a significant waste of system resources due to numerous invalid polling operations; secondly, the timed polling mechanism used to control polling overhead can cause packets to arrive in the buffer but not be processed in time due to the timer period not being reached, resulting in data processing delays. The interrupt response mechanism of this invention fundamentally eliminates these shortcomings, ensuring the efficiency and real-time performance of GOOSE packet processing. 2) Set up 8 Buff data buffers to ensure that GOOSE messages are not lost. For example... Figure 3As shown, during message reception, the FPGA in the right area of ​​the diagram stores the Ethernet data link layer message in the EMIF ring buffer after MAC filtering and triggers an interrupt. The DSP in the left area of ​​the diagram immediately parses the message in the ring buffer after entering interrupt handling and updates the GOOSE protocol's receive data unit. The received and transmitted data units are converted to an easily expandable format via the TLV data interface and interact with the upper-layer application software. During message transmission, the application layer updates the GOOSE protocol's transmit data unit via the TLV data interface. The message filling module converts the transmit data unit into a byte stream and writes it into the transmit buffer, which is then handed over to the FPGA to complete the link layer message transmission. Due to the potential microsecond-level message interval, even if an interrupt is used to notify DSPCPU1 to parse GOOSE messages, message loss may occur because GOOSE parsing takes time, and the message interval is too short. Therefore, the FPGA is used to perform a ring buffering of the data to ensure that no messages are lost. 3) Data Integrity. Packet sequence numbers and checksums are added to messages sent from the FPGA to DSP CPU1. DSP CPU1 will only parse the message if the received packet sequence number matches the number of messages and the checksum is correct. 4) Abnormal reset. For example... Figure 4 As shown, after DSP CPU1 successfully parses the message, it sends the received packet sequence number back to FPGA. FPGA then determines whether the DSP has packet loss or message errors. If it determines that the DSP has been experiencing packet loss for an extended period, it resets the DSP and continues the GOOSE communication, thus ensuring communication reliability and reducing the impact on the operation of the energy storage converter.

[0038] In this embodiment, the first communication interface is a Serial Peripheral Interface (SPI); the microcontroller unit (MCU) is externally connected to a synchronous dynamic random access memory (SDRAM) and internally integrates a tightly coupled memory (TCM) and a static random access memory (SRAM); the MCU deploys the tasks of the trimmed Manufacturing Message Specification (MMS) protocol stack to different memories for execution according to the priority of the MMS protocol; tasks that meet the first preset condition are deployed to the tightly coupled memory (TCM) for execution, tasks that meet the second preset condition are deployed to the static random access memory (SRAM) for execution, and tasks that meet the third preset condition are deployed to the synchronous dynamic random access memory (SDRAM) for execution.

[0039] In specific application embodiments, the Manufacturing Message Specification (MMS) protocol stack has high requirements for memory and computing power. While the central processing unit (CPU) has a high clock speed and can be configured with large amounts of memory, the microcontroller unit (MCU) has limited internal RAM and a low clock speed. Therefore, the mainstream industry solution implements the MMS protocol in the CPU. Porting MMS to the MCU presents extremely high challenges for software development. This embodiment adopts the following approach: 1) Deeply trim the MMS service, retaining only the four types of services required by the energy storage converter: remote signaling, remote adjustment, remote measurement, and remote control, in order to reduce the memory consumption of the MMS service; 2) such as Figure 5 As shown, based on the speed differences in MCU access to internal tightly coupled memory (TCM), static random access memory (SRAM), and external synchronous dynamic random access memory (SDRAM) (TCM access is the fastest, followed by SRAM, and SDRAM is the slowest), to improve system real-time performance, tasks of different priorities are deployed to different memories for execution. Specifically, this includes: a. Classify the tasks of the operating system, Ethernet protocol stack, and MMS service according to their urgency and criticality, and divide their importance according to the hierarchical structure of the software modules. The operating system, which is responsible for basic task scheduling, has the highest priority, followed by the driver tasks of the Ethernet protocol stack, and the MMS application layer tasks have the lowest priority. b. Divide the memory into TCM, SRAM and external SDRAM inside the MCU. Deploy urgent and critical tasks to TCM, urgent but non-critical tasks to SRAM, and other tasks to SDRAM.

[0040] In this embodiment, the microcontroller unit (MCU) further includes a platform-based configuration process, which includes: Parse the configuration file to obtain multiple sets of configuration information, including one or more of the following: MMS protocol parameters for manufacturing message specifications, GOOSE message protocol parameters for general-purpose substation events, and parameters required for Ethernet MAC filtering. Complete the configuration of the Manufacturing Message Specification (MMS) protocol stack based on the configuration information; The GOOSE message protocol parameters for general-purpose substation events are sent to the digital signal processor (DSP) via the third communication interface to configure the DSP's GOOSE message parsing function for general-purpose substation events. The Ethernet MAC filtering parameters are sent to the field-programmable gate array (FPGA) via the third communication interface to configure the FPGA's Ethernet MAC filtering module to listen for specified GOOSE multicast messages.

[0041] Specifically, in order to adapt to the different requirements of parameters such as MMS server IP address, IED device name, GOOSE multicast MAC address and communication APPID in different batch projects, and to achieve flexible adaptation with the energy management systems of various manufacturers, it is necessary to ensure that the key parameters of the IEC61850 protocol stack are configurable.

[0042] like Figure 6 As shown, based on the novel communication architecture of this embodiment, the protocol stack key parameter configuration function adopts a "single-point parsing, multi-point configuration" strategy. In specific implementation, the microcontroller unit (MCU), equipped with an operating system and file system, first completes the parsing of the XML configuration file, and then injects the parsed configuration information into the initialization processes of the following three components: (1) Complete the parameter configuration of the local MMS protocol stack of the microcontroller unit (MCU); (2) Configure the parameter information required for GOOSE communication to the digital signal processor DSP; (3) Configure the multicast MAC address required for GOOSE listening to the field programmable gate array (FPGA).

[0043] In this configuration process, the initialization configuration of the digital signal processor (DSP) and the field-programmable gate array (FPGA) is achieved through a simplified Universal Asynchronous Receiver / Transmitter (UART) protocol. The microcontroller unit (MCU), DSP, and FPGA all have adapted their respective transceiver protocol stacks to this custom platform-based configuration protocol, ensuring reliable transmission and execution of configuration commands.

[0044] This embodiment also provides an energy storage converter, including a communication system for the energy storage converter.

[0045] This embodiment also provides a computer-readable storage medium storing a computer program. When the program is executed by the microcontroller unit (MCU), it implements a platform-based configuration process in the communication system for the energy storage converter.

[0046] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes. The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A communication system for an energy storage converter, characterized in that, include: Microcontroller Units (MCUs), Field Programmable Gate Arrays (FPGAs), and Digital Signal Processors (DSPs); The microcontroller unit (MCU) is connected to two Ethernet networks of the data network, performs communication processing according to the Manufacturing Message Specification (MMS) protocol, and exchanges data with the field-programmable gate array (FPGA) through the first communication interface. The field-programmable gate array (FPGA) connects to two Ethernet ports of the control network, receives and parses Ethernet MAC frames, and sends the acquired substation event GOOSE messages for general objects to the digital signal processor (DSP) through the second communication interface. The digital signal processor (DSP) receives and parses the general-purpose substation event GOOSE message from the field programmable gate array (FPGA), and generates power control commands for the energy storage converter based on the parsing results.

2. The communication system for an energy storage converter according to claim 1, characterized in that, The second communication interface is the External Memory Interface (EMIF). The FPGA writes the received GOOSE messages of general-purpose substation events into the storage space of the EMIF and, after completing the writing, sends an interrupt signal to the Digital Signal Processor (DSP) through the General Purpose Input / Output (GPIO).

3. The communication system for an energy storage converter according to claim 2, characterized in that, The FPGA integrates a circular buffer; the FPGA first stores the GOOSE messages of general-purpose substation events received from Ethernet into the circular buffer, and then writes them sequentially into the storage space of the external memory interface EMIF.

4. The communication system for an energy storage converter according to claim 3, characterized in that, When the FPGA writes a GOOSE message for a general-purpose substation event to the external memory interface EMIF, it adds a packet sequence number and a checksum to each message. After reading the message from the external memory interface EMIF, the DSP verifies the continuity of the packet sequence number and the correctness of the checksum. Upon successful parsing, the DSP returns an acknowledgment message containing the parsed packet sequence number to the FPGA through the external memory interface EMIF.

5. The communication system for an energy storage converter according to claim 4, characterized in that, The field-programmable gate array (FPGA) determines whether the digital signal processor (DSP) has lost or erroneous message parsing by monitoring the packet sequence number in the confirmation information. If a message parsing error occurs in the digital signal processor (DSP), a communication anomaly recovery process for the DSP is triggered.

6. The communication system for an energy storage converter according to claim 1, characterized in that, The first communication interface is a Serial Peripheral Interface (SPI); the microcontroller unit (MCU) is externally connected to a Synchronous Dynamic Random Access Memory (SDRAM) and internally integrates a Tightly Coupled Memory (TCM) and a Static Random Access Memory (SRAM); the MCU deploys the tasks of the trimmed Manufacturing Message Specification (MMS) protocol stack to different memories for execution according to the priority of the MMS protocol; tasks that meet the first preset condition are deployed to the Tightly Coupled Memory (TCM) for execution, tasks that meet the second preset condition are deployed to the SRAM for execution, and tasks that meet the third preset condition are deployed to the SDRAM for execution.

7. The communication system for an energy storage converter according to claim 1, characterized in that, The microcontroller unit (MCU) also includes a platform-based configuration process, which includes: Parse the configuration file to obtain multiple sets of configuration information, including one or more of the following: Manufacturing Message Specification (MMS) protocol parameters, GOOSE message protocol parameters for general-purpose substation events, and parameters required for Ethernet MAC filtering. Complete the configuration of the Manufacturing Message Specification (MMS) protocol stack based on the configuration information; The GOOSE message protocol parameters for general-purpose substation events are sent to the digital signal processor (DSP) via the third communication interface to configure the DSP's GOOSE message parsing function for general-purpose substation events. The Ethernet MAC filtering parameters are sent to the field-programmable gate array (FPGA) via the third communication interface to configure the FPGA's Ethernet MAC filtering module to listen for specified GOOSE multicast messages.

8. The communication system for an energy storage converter according to claim 1, characterized in that, The microcontroller unit (MCU) is connected to two Ethernet ports of the data network, and the two Ethernet ports of the data network are redundant backups of each other; the field-programmable gate array (FPGA) is connected to two Ethernet ports of the control network, and the two Ethernet ports of the control network are redundant backups of each other.

9. An energy storage converter device, characterized in that, Includes the communication system for energy storage converters as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the program is executed by the microcontroller unit (MCU), the platform-based configuration process for the communication system of the energy storage converter as described in any one of claims 1 to 8 is executed.

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