Differential transmission line and printed circuit board

Abstract

The invention discloses a differential transmission line which comprises a first-layer differential plate, a first interlayer structure, a second-layer differential plate, a second interlayer structure and a bottom-layer structure. The first-layer differential plate and the second-layer differential plate are connected through a first interlayer structure, and the second-layer differential plate and the bottom-layer structure are connected through a second interlayer structure; the first-layer differential plate comprises a first-layer circuit, the second-layer differential plate comprises a second-layer circuit, and the first-layer circuit and the second-layer circuit are distributed in a staggered mode in the horizontal direction. According to the invention, through staggered distribution of the first-layer circuit and the second-layer circuit in the horizontal direction, the overlapping area of the first-layer differential plate and the second-layer differential plate is reduced, so that the interlayer parasitic capacitance of the first-layer differential plate and the second-layer differential plate is reduced; impedance matching is achieved while the mechanical performance of the printed circuit board body is guaranteed and process limitation is broken through, so that the signal transmission stability requirement is met.

Description

Technical Field

[0001] This invention relates to the field of transmission line structure technology, and in particular to a differential transmission line and a printed circuit board. Background Technology

[0002] As electronic systems develop towards high frequency, high speed, high density, and low power consumption, the design of printed circuit boards, especially packaging substrates, is becoming increasingly compact. Sometimes, transmission lines need to be designed with "turn-around heads." In the vertical direction of the stacked layers, some transmission lines overlap, which forms significant interlayer parasitic capacitance. This reduces the impedance of the transmission lines, making impedance mismatch impossible and causing signal loss.

[0003] Currently, the following two solutions are mostly used to achieve impedance matching: 1) Remove the reference layers, but the number of reference layers is limited, and the adjustment is greatly restricted. Even if all the reference layers that can be modified are removed, the impedance still cannot be matched, and removing too many reference layers will also affect the mechanical properties of the printed circuit board. 2) Reducing the linewidth can lower parasitic capacitance, but the room for adjustment of the linewidth is small due to the influence of the manufacturing process.

[0004] Therefore, the transmission line structures used in the prior art to achieve impedance matching are difficult to achieve effective impedance matching while ensuring the mechanical performance of the printed circuit board and overcoming process limitations, thus failing to meet the requirements for signal transmission stability. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a differential transmission line and a printed circuit board, which can achieve effective impedance matching while ensuring the mechanical properties of the printed circuit board and overcoming process limitations, thereby meeting the requirements for signal transmission stability.

[0006] This invention is implemented according to the following scheme: A differential transmission line is provided, comprising: a first differential board, a first interlayer structure, a second differential board, a second interlayer structure, and a bottom layer structure; the first differential board and the second differential board are connected through the first interlayer structure, and the second differential board and the bottom layer structure are connected through the second interlayer structure. The first differential board includes a first layer of circuitry, and the second differential board includes a second layer of circuitry. The first layer of circuitry and the second layer of circuitry are staggered in the horizontal direction.

[0007] Compared with the prior art, the differential transmission line has the following beneficial effects: by staggered distribution of the first layer line and the second layer line in the horizontal direction, the overlapping area of the first layer differential plate and the second layer differential plate is reduced, and the interlayer parasitic capacitance of the first layer differential plate and the second layer differential plate is reduced, so that impedance matching is realized while the mechanical properties of the printed circuit board are ensured and the process limit is broken through, so as to meet the signal transmission stability requirement.

[0008] Optionally, the first layer differential plate comprises a first layer differential structure arranged symmetrically, the first layer differential structure comprising the first layer line and a first layer hole disc; the first layer line is connected with the first layer hole disc and the first interlayer structure, and the first layer hole disc is connected with the second layer differential plate through the first interlayer structure.

[0009] Optionally, the second layer differential plate comprises a second layer differential structure arranged symmetrically, the second layer differential structure comprising a first reference ground provided with the second layer line and a second layer hole disc; the first reference ground is connected with the first layer line through the first interlayer structure, the second layer line is connected with the second layer hole disc, the first layer hole disc is connected with the second layer hole disc through the first interlayer structure, and the first reference ground is connected with the second interlayer structure.

[0010] Optionally, the bottom layer structure comprises a second reference ground; the first reference ground is connected with the second reference ground through the second interlayer structure.

[0011] Optionally, the first interlayer structure comprises an interlayer via and a first dielectric layer; the interlayer via penetrates through the first layer hole disc, the first dielectric layer and the second layer hole disc, and the first dielectric layer is connected with the second layer differential plate.

[0012] Optionally, the second interlayer structure comprises a second dielectric layer and a shielding hole, and the second layer differential plate is connected with the bottom layer structure through the second dielectric layer.

[0013] Optionally, the hole disc diameter of the first layer hole disc is greater than the hole disc diameter of the second layer hole disc.

[0014] Optionally, the first reference ground and the second reference ground are both pure copper foil materials.

[0015] Optionally, the hole disc diameter of the second layer hole disc is greater than the via diameter of the interlayer via.

[0016] Also provided is a printed circuit board comprising one or more differential transmission lines. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a structural diagram of the differential transmission line of the present application. Figure 2 Part structure diagram of differential transmission line of the present application; Figure 3 Sectional view of differential transmission line of the present application; Figure 4 Structure diagram of differential transmission line of prior art; Figure 5 Part structure diagram of differential transmission line of prior art; Figure 6 Simulation structure schematic diagram of differential transmission line of the present application and differential transmission line of prior art; The figure mark explanation, 1, first layer differential board; 101, first layer circuit; 102, first layer hole disc; 2, interlayer structure; 201, interlayer via; 202, first dielectric layer; 3, second layer differential board; 301, first reference ground; 302, second layer circuit; 3021, rotation structure; 303, second layer hole disc; 4, second interlayer structure; 401, second dielectric layer; 402, shielding hole; 5, bottom layer structure. DETAILED DESCRIPTION

[0018] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings, it should be understood that the preferred embodiments described here are only used to illustrate and explain the present application, and are not used to limit the present application.

[0019] The following description refers to the accompanying drawings. Unless otherwise noted, like elements in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not necessarily mean to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0020] Referring to Figures 1-3 As shown, a differential transmission line of the present application includes: a first layer differential board 1, a first interlayer structure 2, a second layer differential board 3, a second interlayer structure 4 and a bottom layer structure 5; the first layer differential board 1 and the second layer differential board 3 are connected through the first interlayer structure 2, and the second layer differential board 3 and the bottom layer structure 5 are connected through the second interlayer structure 4; the first layer differential board 1 includes a first layer circuit 101, and the second layer differential board 3 includes a second layer circuit 302, and the first layer circuit 101 and the second layer circuit 302 are distributed in horizontal direction staggered.

[0021] The present application realizes the reduction of the overlap area of the first layer differential plate 1 and the second layer differential plate 3 by the staggered distribution of the first layer line 101 and the second layer line 302 in the horizontal direction, thereby reducing the interlayer parasitic capacitance between the first layer differential plate 1 and the second layer differential plate 3, and realizing impedance matching while guaranteeing the mechanical properties of the printed circuit board and breaking through the process limit, so as to meet the signal transmission stability requirement.

[0022] In an embodiment of the present application, the first layer differential plate 1 comprises a symmetrically arranged first layer differential structure, the first layer differential structure comprising a first layer line 101 and a first layer hole disc 102; the first layer line 101 is connected with the first layer hole disc 102 and the first interlayer structure 2, and the first layer hole disc 102 is connected with the second layer differential plate 3 through the first interlayer structure 2.

[0023] In an embodiment of the present application, the second layer differential plate 3 comprises a symmetrically arranged second layer differential structure, the second layer differential structure comprising a first reference ground 301 provided with a second layer line 302 and a second layer hole disc 303; the first reference ground 301 is connected with the first layer line 101 through the first interlayer structure 2, the second layer line 302 is connected with the second layer hole disc 303, the first layer hole disc 102 is connected with the second layer hole disc 303 through the first interlayer structure 2, and the second reference ground 301 is connected with the second interlayer structure 4.

[0024] In an embodiment of the present application, the second layer line 302 comprises a rotation structure 3021 to realize the staggered distribution of the second layer line 302 and the first layer line 101 in the horizontal direction, as shown in FIG. 2, which is a structure schematic diagram after hiding the first medium layer 202 for clear display. Figure 2 As shown in FIG. 2, the second layer line 302 leads out a line parallel to the first layer line 101, bypasses the first layer line 101 outward through the rotation structure 3021 at the first layer line 101, continues to lead out a line not overlapping with the first layer line 101 in the parallel direction of the first layer line 101 to connect the second layer hole disc 303, so as to reduce the overlap area of the first layer line 101 and the second layer line 302, and further reduce the interlayer parasitic capacitance between the first layer differential plate 1 and the second layer differential plate 3.

[0025] In an embodiment of the present application, the bottom layer structure 5 comprises a second reference ground; the first reference ground 301 is connected with the second reference ground through the second interlayer structure 4, and the second reference ground is used to provide a path for returning current, and its existence or nonexistence affects the line impedance.

[0026] In one embodiment of the present invention, the first interlayer structure 2 includes an interlayer via 201 and a first dielectric layer 202; the interlayer via 201 passes through the first layer via 102, the first dielectric layer 202 and the second layer via 303, the first dielectric layer 202 is connected to the second layer differential plate 3, and the electrical connection between the first layer line 101 and the second layer line 302 is realized through the interlayer via 201. The first dielectric layer 202 is used to realize electrical insulation to prevent short circuits between different layers of lines. Its insulation performance and thickness will affect the line impedance.

[0027] In one embodiment of the present invention, the second interlayer structure 4 includes a second dielectric layer 401 and a shielding hole 402. The second differential plate 3 is connected to the bottom layer structure 5 through the second dielectric layer 401. The second dielectric layer 401 is used to achieve electrical insulation to prevent short circuits between different layers of lines. Its insulation performance and thickness will affect the line impedance. The shielding hole 402 is used to connect the first reference ground and the second reference ground to form a shielding space that approximates a Faraday cage to prevent crosstalk caused by external signals.

[0028] In one embodiment of the present invention, the diameter of the first layer hole disk 102 is larger than the diameter of the second layer hole disk 303; both the first reference ground 301 and the second reference ground are made of pure copper foil; the diameter of the second layer hole disk 303 is larger than the diameter of the interlayer via 201.

[0029] In one embodiment of the present invention, the horizontal spacing between the first layer line 101 and the second layer line 302 is maintained at least 90 μm to reduce the coupling capacitance in the horizontal direction. In practical applications, the horizontal spacing between the first layer line 101 and the second layer line 302 is equivalent to the distance between the two layers of lines. Therefore, the greater the horizontal distance of the lines, the smaller the coupling capacitance. In this embodiment, the horizontal spacing between the first layer line 101 and the second layer line 302 is maintained at 90 μm, and the coupling capacitance is at a relatively small level. The greater the horizontal spacing between the first layer line 101 and the second layer line 302, the smaller the coupling capacitance. However, considering the overall wiring space, the present invention only needs to maintain the horizontal spacing between the first layer line 101 and the second layer line 302 at 90 μm to meet the requirements.

[0030] Next, specific parameters will be substituted into different structures of the differential transmission line of the present invention to explain in detail how the present invention achieves impedance balance: In the present application, the first dielectric layer 202 and the second dielectric layer 401 are conventional PI layers, each having a thickness of 0.025 mm, a dielectric constant Dk value of 2.8, and a dielectric loss factor Df value of 0.008; the first reference ground 301 and the second reference ground each have a thickness of 0.012 mm; the first layer via hole pad 102 has a via hole pad diameter of 0.2 mm and a reverse pad width of about 0.11 mm; the second layer via hole pad 303 has a via hole pad diameter of 0.13 mm and a reverse pad width of about 0.11 mm; the interlayer via hole 201 has a via hole diameter of 0.05 mm; the first layer circuit 101 has a line length of 0.4 mm, a line width of 0.095 mm, and a line spacing of 0.05 mm; the second layer circuit 302 has a line length of 5 mm, a line width of 0.043 mm, and a line spacing of 0.05 mm; and the shielding hole 402 has a hole diameter of 0.07 mm and a hole spacing of 0.2 mm between the plurality of shielding holes 402.

[0031] In actual application, the impedance calculation formula of the differential transmission line is as follows:

[0032]

[0033]

[0034] wherein Z is the impedance of the differential transmission line, L is the parasitic inductance of the via hole, h is the interlayer thickness corresponding to the thickness of the first dielectric layer 202 and the second dielectric layer 401, D is the via hole diameter corresponding to the via hole diameter of the interlayer via hole 201, C is the interlayer parasitic capacitance, is the vacuum dielectric constant, used to measure the energy storage capacity of vacuum, is a physical constant, and has a value of about 8.854*10e-12 F / m; is the relative dielectric constant, used to describe the energy storage capacity of a medium relative to vacuum, and is the ratio of its actual value to the vacuum dielectric constant The relative dielectric constant of a circuit board medium material is usually between 2 and 4, the product of the vacuum dielectric constant and the relative dielectric constant is used to represent the actual energy storage capacity of the medium, and A is the overlapping area corresponding to the overlapping area of the first layer differential board 1 and the second layer differential board 3, including the overlapping area of the first layer via hole pad 102 and the second layer via hole pad 303.

[0035] As can be seen from the impedance calculation formula, this scheme reduces the overlapping area of ​​the first layer differential board 1 and the second layer differential board 3 by staggering the distribution of the first layer line 101 and the second layer line 302, thereby reducing the interlayer parasitic capacitance between the first layer differential board 1 and the second layer differential board 3. Without changing the parasitic inductance of the via, it can effectively increase the impedance of the differential transmission line, thereby narrowing the gap between the actual impedance and the ideal impedance.

[0036] See Figures 4-5 As shown, a differential transmission line structure in the prior art is illustrated, wherein... Figure 5 This is a schematic diagram of a differential transmission line structure in the prior art that hides the first dielectric layer. The first differential layer structure and the second differential layer structure overlap in the horizontal direction. This relates to the differential transmission line and... Figures 4-5 The differential transmission lines were all simulated using a frequency of 50 GHz.

[0037] See Figure 6 As shown in the figure, the simulation results of the differential transmission line of the present invention and the prior art differential transmission line are illustrated. As can be seen from the figure, the maximum impedance value of the differential transmission line of the present invention is 92.16Ω (corresponding to...). Figure 6 The improved impedance (in the original text) deviates from the target value of 90Ω by less than 5%, while the minimum impedance of existing differential transmission lines is 81.95Ω (corresponding to...). Figure 6 The original impedance of the differential transmission line of this invention deviates from the target value of 90Ω by more than 5%. Compared with the differential transmission line of the prior art, the differential transmission line of this invention achieves better impedance matching effect. Moreover, this invention does not require the removal of the reference layer or the reduction of the line width to achieve impedance matching. It can achieve impedance matching while ensuring the mechanical performance of the printed circuit board and overcoming process limitations, so as to meet the requirements of signal transmission stability.

[0038] The present invention provides a printed circuit board including one or more of the above-mentioned differential transmission lines, wherein the differential transmission lines can achieve impedance matching without the need to hollow out the reference layer, thereby ensuring that the mechanical properties of the printed circuit board are not affected.

[0039] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A differential transmission line, characterized in that, include: First layer differential plate, first layer interlayer structure, second layer differential plate, second layer interlayer structure and bottom layer structure; The first differential plate and the second differential plate are connected through the first interlayer structure, and the second differential plate and the bottom layer structure are connected through the second interlayer structure. The first differential board includes a first layer of circuitry, and the second differential board includes a second layer of circuitry. The first layer of circuitry and the second layer of circuitry are staggered in the horizontal direction.

2. A differential transmission line according to claim 1, characterized in that, The first differential board includes a symmetrically arranged first differential structure, the first differential structure including a first layer of circuitry and a first layer of vias; the first layer of circuitry is connected to the first layer of vias and the first interlayer structure, and the first layer of vias is connected to the second differential board through the first interlayer structure.

3. A differential transmission line according to claim 2, characterized in that, The second differential board includes a symmetrically arranged second differential structure. The second differential structure includes a first reference ground with a second layer of circuitry and a second layer of vias. The second layer of circuitry is connected to the second layer of vias. The first layer of vias is connected to the second layer of vias through a first interlayer structure. The first reference ground is connected to the second interlayer structure.

4. A differential transmission line according to claim 3, characterized in that, The underlying structure includes a second reference ground; the first reference ground is connected to the second reference ground through the second interlayer structure.

5. A differential transmission line according to claim 3, characterized in that, The first interlayer structure includes an interlayer via and a first dielectric layer; the interlayer via passes through the first layer via, the first dielectric layer and the second layer via, and the first dielectric layer is connected to the second layer differential plate.

6. A differential transmission line according to claim 5, characterized in that, The second interlayer structure includes a second dielectric layer and shielding holes, and the second differential plate is connected to the bottom layer structure through the second dielectric layer.

7. A differential transmission line according to claim 3, characterized in that, The diameter of the first layer of perforated plates is larger than the diameter of the second layer of perforated plates.

8. A differential transmission line according to claim 4, characterized in that, Both the first reference ground and the second reference ground are made of pure copper foil.

9. A differential transmission line according to claim 5, characterized in that, The diameter of the second layer of perforated plate is larger than the diameter of the interlayer via.

10. A printed circuit board, characterized in that, It includes one or more differential transmission lines as described in any one of claims 1-9 above.

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