Wafer processing method and device, equipment and storage medium
By acquiring etching equipment status data, dynamically selecting the target etching reaction chamber and lithography machine, and using target compensation parameters for reverse compensation, the problem of uneven wafer pattern size after etching was solved, achieving uniformity control and improved processing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-13
- Publication Date
- 2026-04-10
AI Technical Summary
In existing technologies, the non-uniformity of the cavity of the etching machine results in non-uniform wafer pattern size after etching. Traditional compensation methods rely on manual binding of the machine, which cannot effectively solve the non-uniformity problem caused by cavity differences.
By acquiring the status data of the etching equipment, the target etching reaction chamber and lithography machine are determined, the target compensation parameters are dynamically selected, and reverse compensation is performed using the target lithography machine. Combined with the processing of the target etching reaction chamber, the uniformity of the pattern size is ensured.
This technology enables uniform control of wafer pattern size after etching, improves wafer quality after etching, and enhances processing efficiency and throughput.
Smart Images
Figure CN121843501A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a wafer processing method, apparatus, device, and storage medium. Background Technology
[0002] The uniformity of wafer pattern dimensions (or critical dimensions, CD) is affected by multiple factors, including the manufacturing quality of the photomask, the stability and accuracy of exposure parameters during photolithography (spatial image process window), optical proximity effect (optical interference phenomena during photolithography), photolithography machine hardware performance, the uniformity and sensitivity of photolithography materials (such as photoresist), and the surface quality of the silicon substrate. In the etching process, due to uneven plasma distribution within the etching machine cavity, the pattern dimensions measured after etching will show an uneven distribution with larger outer edges and smaller inner edges.
[0003] Traditionally, deviation compensation is tied to the etching equipment, i.e., it is done manually using the DOMA (DeviationOffset Matching Approach). However, this requires that the different cavities of the etching equipment be highly consistent. When there are differences between cavities, it can still lead to uneven pattern size after etching. Summary of the Invention
[0004] The purpose of this application is to provide a wafer processing method, apparatus, device, and storage medium to address the shortcomings of the prior art and solve the technical problems existing in the related technologies.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a wafer processing method, the method comprising: Obtain the equipment status data of the etching machine; Based on the machine status data, the target etching reaction chamber and target lithography machine to be worked are determined; Based on the target etching reaction cavity and the target lithography machine, the target compensation parameter is determined from multiple preset compensation parameters; Receive wafers to be processed; The target lithography machine is used to perform lithography on the wafer to be processed. The target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer to be processed during the lithography process. The target etching reaction chamber is used to etch the photolithographically etched wafer to obtain the etched wafer.
[0006] Optionally, determining the target etching reaction chamber and target lithography machine to be operated based on the machine status data includes: Based on the machine status data, the cavity status of multiple etching reaction chambers on the etching machine is determined, and the etching reaction chamber in the idle state is identified as the target etching reaction chamber. Based on the status of multiple lithography machines, the lithography machine in an idle state is identified as the target lithography machine.
[0007] Optionally, determining the target compensation parameter from a plurality of preset compensation parameters based on the target etching reaction cavity and the target lithography machine includes: From a plurality of preset pattern size correction paths, select the target pattern size correction path corresponding to the target etching reaction cavity and the target lithography machine, wherein the plurality of preset pattern size correction paths correspond to the plurality of preset compensation parameters respectively; Based on the target graphic size correction path, the corresponding target compensation parameters are obtained.
[0008] Optionally, obtaining the corresponding target compensation parameters based on the target graphic size correction path includes: Invoke the equipment automation program; The equipment's automated program invokes the lithography task; Using the aforementioned lithography task, the preset compensation parameters corresponding to the target pattern size correction path are retrieved from the preset shared storage space as target compensation parameters; The preset shared storage space stores multiple preset compensation parameters corresponding to multiple preset graphic size correction paths.
[0009] Optionally, each compensation parameter corresponds to a combination of an etching reaction chamber, a lithography machine, a wafer product, a device layer of the wafer product, and a mask for processing the device layer; Each preset pattern size correction path includes: preset lithography machine, preset mask, preset device layer, preset etching reaction chamber, and wafer product.
[0010] Optionally, the step of using the target lithography machine to perform lithography on the wafer to be processed includes: Obtain the photolithography process parameters for photolithography processing of the wafer to be processed; Using the target lithography machine, the wafer to be processed is subjected to lithography according to the lithography process parameters and the target compensation parameters to obtain the lithographic wafer.
[0011] Optionally, receiving the wafer to be processed includes: Based on the target etching reaction chamber and the target lithography machine, a work request is generated; Receive the wafer to be processed corresponding to the dispatch request.
[0012] Secondly, embodiments of this application also provide a wafer processing apparatus, the apparatus comprising: The acquisition module is used to acquire the machine status data of the etching machine. The determination module is used to determine the target etching reaction cavity and the target lithography machine to be operated based on the machine status data; and to determine the target compensation parameter from multiple preset compensation parameters according to the target etching reaction cavity and the target lithography machine. The receiving module is used to receive the wafers to be processed; The processing module is used to perform photolithography on the wafer to be processed using the target photolithography machine. The target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer to be processed during the photolithography process. The target etching reaction chamber is used to perform etching on the photolithographic wafer to obtain an etched wafer.
[0013] Thirdly, embodiments of this application also provide a wafer processing apparatus, including: a memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the wafer processing method described in any of the first aspects above.
[0014] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when read and executed, implements the wafer processing method described in any of the first aspects above.
[0015] The beneficial effects of this application are as follows: This application provides a wafer processing method, which includes: acquiring equipment status data of an etching machine; determining a target etching reaction chamber and a target lithography machine based on the equipment status data; determining a target compensation parameter from multiple preset compensation parameters according to the target etching reaction chamber and the target lithography machine; receiving a wafer to be processed; performing lithography on the wafer using the target lithography machine, wherein the target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer during the lithography process; and performing etching on the lithographically processed wafer using the target etching reaction chamber to obtain an etched wafer. The target compensation parameter is determined from multiple preset compensation parameters. This target compensation parameter is specifically designed for the target etching reaction chamber and the target lithography machine. By using the target lithography machine to perform lithography based on the target compensation parameter, accurate reverse compensation can be performed to address the uneven pattern size caused by the target etching reaction chamber, ensuring that the pattern size in the etched wafer is uniform. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 1 ; Figure 2 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 2 ; Figure 3 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 3 ; Figure 4 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 4 ; Figure 5 A schematic diagram illustrating the correspondence between a lithography machine and an etching reaction chamber, provided as an embodiment of this application; Figure 6 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 5 ; Figure 7 This is a schematic diagram of the structure of a wafer processing apparatus provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a wafer processing device provided in an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0021] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0023] This application provides a wafer processing method applied to a wafer processing device, which can be a computing device or a server.
[0024] The following is an explanation of a wafer processing method provided in the embodiments of this application.
[0025] Figure 1 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method may include: S101. Obtain the machine status data of the etching machine.
[0026] A single etching machine may include multiple etching reaction chambers, and the machine status data of the etching machine may include the status data of the multiple etching reaction chambers on the etching machine, specifically including the working status and estimated idle time of each etching reaction chamber.
[0027] S102. Based on the machine status data, determine the target etching reaction chamber and the target lithography machine to be worked.
[0028] In some implementations, the target etching reaction cavity to be worked is determined from the multiple etching reaction cavities on the etching machine based on the status of the multiple etching reaction cavities on the machine status data; the target lithography machine to be worked is determined from the multiple lithography machines based on the status of the multiple lithography machines.
[0029] It should be noted that the target etching reaction chamber and the target lithography machine can process the wafer at any given moment, that is, the etching reaction chamber and the lithography machine can be in an idle state.
[0030] S103. Determine the target compensation parameter from multiple preset compensation parameters based on the target etching reaction chamber and the target lithography machine.
[0031] The target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer during the photolithography process. Specifically, the target compensation parameter can be a subroutine, or sub-recipe, in the processing. Here, the pattern size refers to the critical dimensions of the circuit pattern on the wafer.
[0032] It should be noted that different preset compensation parameters correspond to different etching cavities and lithography machines. In other words, these preset compensation parameters are specifically customized for different etching cavities and lithography machines. The formulation of these preset compensation parameters considers not only the primary influence of the etching cavity on the uniformity of the device pattern size but also the secondary influence of the target lithography machine on the uniformity of the device pattern size. The preset compensation parameters provide better reverse compensation for the pattern size of the device to be formed on the wafer.
[0033] In practical applications, after photolithography is performed on the wafer, the size of the pattern on the wafer is measured. At this time, the measured size of the pattern is uniform. Then, an etching reaction chamber is used for etching. Due to the uneven distribution of plasma in the etching chamber, the measured size of the pattern after etching will show an uneven distribution with a larger outer circle and a smaller inner circle. Different etching chambers will produce different unevenness.
[0034] In this embodiment, custom preset compensation parameters are designed for the paired etching reaction chamber a and lithography machine a. The lithography machine a performs lithography based on the preset compensation parameters. These preset compensation parameters are reverse compensations specifically designed for the non-uniformity in the etching reaction chamber a, so that the pattern size after etching in the etching reaction chamber a is just uniform.
[0035] S104, Receive the wafer to be processed.
[0036] Among them, the wafer to be processed is the wafer that can be processed by the target etching reaction chamber and the target lithography machine.
[0037] In this embodiment, when the target etching reaction chamber and the target lithography machine are determined, that is, when it is determined that there is an idle etching reaction chamber and an idle lithography machine on the etching machine, a work order can be requested and the corresponding wafer to be processed can be received.
[0038] S105. A target lithography machine is used to perform lithography on the wafer. The target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer during the lithography process.
[0039] In some implementations, a target lithography machine is used to form circuit patterns on the photoresist of the wafer to be processed through exposure and development steps according to target compensation parameters, resulting in a lithographically lithographic wafer. Because of the added target compensation parameters, the pattern size of the lithographically lithographic wafer is measured, and the result shows that the outer edge is smaller and the inner edge is larger. This reverse compensation is specifically designed to address the non-uniformity caused by the target etching reaction chamber.
[0040] In the process of photolithography and before etching, the dimensions of the pattern on the photoresist need to be measured; this measurement process is called Analog Devices (ADI). The photolithography process is called Litho.
[0041] S106. Using the target etching reaction chamber, the photolithographically etched wafer is etched to obtain the etched wafer.
[0042] In this embodiment, a target etching reaction chamber is used, and plasma is used to transfer the circuit pattern on the photoresist in the photolithographic wafer to the material on the bottom of the wafer, completing the etching process and obtaining the etched wafer. Since the non-uniformity caused by the target etching reaction chamber during the photolithography stage has been accurately compensated in reverse, the etched wafer here is uniform.
[0043] The process of measuring the dimensions of the pattern after etching is called AEI (Advanced Image Interference). The etching process itself is called Etch.
[0044] It should be noted that in this embodiment, both the target etching reaction chamber and the target lithography machine are determined. Both the target etching reaction chamber and the target lithography machine can process the wafer at the current moment. This not only ensures that the target lithography machine can accurately reverse compensate the pattern size on the wafer in the lithography process based on the target compensation parameters, but also ensures that the target etching reaction chamber can perform etching processing on the wafer after lithography in a timely manner, thereby improving the wafer processing efficiency.
[0045] In summary, this application provides a wafer processing method, which includes: acquiring the equipment status data of an etching machine; determining the target etching reaction cavity and target lithography machine based on the equipment status data; determining a target compensation parameter from multiple preset compensation parameters according to the target etching reaction cavity and target lithography machine; receiving the wafer to be processed; performing photolithography on the wafer to be processed using the target lithography machine, wherein the target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer to be processed during the photolithography process; and performing etching on the photolithographically processed wafer using the target etching reaction cavity to obtain an etched wafer. The target compensation parameter is determined from multiple preset compensation parameters; the target compensation parameter is a compensation parameter specifically for the target etching reaction cavity and target lithography machine. By using the target lithography machine to perform photolithography based on the target compensation parameter, accurate reverse compensation can be performed to address the uneven pattern size caused by the target etching reaction cavity, ensuring that the circuit size in the etched wafer is uniform.
[0046] Moreover, the target compensation parameters are determined jointly by the target etching reaction cavity and the target lithography machine. They not only take into account the main influence of the etching reaction cavity on the uniformity of pattern size, but also the secondary influence of the target lithography machine on the uniformity of pattern size. The target compensation parameters have a better reverse compensation effect on the pattern size on the wafer.
[0047] Optionally, Figure 2 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, the process of determining the target etching reaction cavity and the target lithography machine based on the machine status data in S102 above may include: S201. Based on the machine status data, determine the cavity status of multiple etching reaction chambers on the etching machine, and identify the etching reaction chamber in the idle state as the target etching reaction chamber.
[0048] S202. Based on the status of multiple lithography machines, determine the lithography machine that is in an idle state and use it as the target lithography machine.
[0049] In the embodiments of this application, the target etching reaction chamber and the target lithography machine are identified as being in an idle state. This allows both the target etching reaction chamber and the target lithography machine to process the wafer in a timely manner, thereby improving wafer processing efficiency and increasing production capacity.
[0050] It should be noted that, as Figure 2 As shown, the process of S201 can be executed first and then the process of S202 can be executed. Of course, the process of S202 can be executed first and then the process of S201 can be executed. The processes of S201 and S202 can also be executed simultaneously. This application embodiment does not impose specific restrictions on this.
[0051] Optionally, Figure 3 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 3 ,like Figure 3 As shown, the process of determining the target compensation parameter from multiple preset compensation parameters based on the target etching reaction cavity and the target lithography machine in S103 above may include: S301. Select the target pattern size correction path corresponding to the target etching reaction cavity and the target lithography machine from multiple preset pattern size correction paths.
[0052] Among them, multiple preset pattern size correction paths correspond to multiple preset compensation parameters. Different preset compensation parameters are used to perform different reverse compensations on the pattern size of the device to be formed on the wafer to be processed during the photolithography process.
[0053] It is worth noting that in the embodiments of this application, different combinations of preset etching reaction cavities and preset lithography machines form different preset pattern size correction paths, and different preset pattern size correction paths correspond to different preset compensation parameters. This enables the deployment of different preset compensation parameters for different combinations of preset etching reaction cavities and preset lithography machines. Since the preset compensation parameters are customized for specific preset etching reaction cavities and preset lithography machines, the reverse compensation effect of the preset compensation parameters on the pattern size is better.
[0054] In addition, the preset compensation parameters corresponding to each preset graphic size correction path are unique.
[0055] S302. Based on the target graphic size correction path, obtain the corresponding target compensation parameters.
[0056] In some implementations, the target etching reaction cavity and the target lithography machine are matched with the preset etching reaction cavity and the preset lithography machine in each preset pattern size correction path to obtain the target pattern size correction path where the target etching reaction cavity and the target lithography machine are located; the preset compensation parameter corresponding to the target pattern size correction path is found from the multiple preset compensation parameters corresponding to the multiple preset pattern size correction paths to obtain the target compensation parameter.
[0057] It is worth noting that the preset pattern size correction path includes at least a preset etching reaction chamber and a preset lithography machine; different preset lithography machines with the same preset etching reaction chamber will form different preset pattern size correction paths; different preset etching reaction chambers with the same preset lithography machine will also form different preset pattern size correction paths.
[0058] Optionally, Figure 4 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 4 ,like Figure 4As shown, the process of obtaining the corresponding target compensation parameters based on the target graphic size correction path in S302 above may include: S401, Invoke the equipment automation program.
[0059] Among them, RTD (Real-Time Disposition) is used to call EAP (Equipment Automation Program).
[0060] S402, The equipment uses an automated program to call up the lithography task.
[0061] Among them, EAP is used to call the lithography exposure task (scanner job).
[0062] S403. Using the photolithography task, the preset compensation parameters corresponding to the target graphic size correction path are called from the preset shared storage space as the target compensation parameters.
[0063] The preset shared storage space stores multiple preset graphic size correction paths and corresponding preset compensation parameters. A preset graphic size correction path can be called a DOMA path.
[0064] In some implementations, the preset shared storage space can be a preset shared folder. The photolithography exposure task calls the preset compensation parameters corresponding to the target pattern size correction path in the preset shared folder to obtain the target compensation parameters.
[0065] In addition, shared folders can be stored in the cloud via HTTP (Hypertext Transfer Protocol).
[0066] In practical applications, if each etching chamber is paired with a specific lithography machine at the equipment end, and the compensation parameters on that lithography machine are tailored to that particular etching chamber, then the lithographically processed wafers can only be processed within the etching chamber associated with that machine. If the etching chamber is occupied, it will cause wafer accumulation, resulting in reduced production capacity. For example, if etching chamber A is paired with lithography machine A and etching chamber B is paired with lithography machine B, meaning there are only two pattern size correction paths, then if etching chamber A is occupied and etching chamber B is idle, the lithographically processed wafers produced by lithography machine A can only be processed by etching chamber A and cannot be processed by etching chamber B.
[0067] Compared to the methods described above, in this embodiment, the target etching reaction cavity and target lithography machine are identified as being in an idle state. For the target pattern size correction path where the target etching reaction cavity and target lithography machine are located, target compensation parameters are dynamically retrieved from a preset shared storage space. This achieves dynamic determination of the target pattern size correction path that can be processed on the wafer, dynamically configuring target compensation parameters for the target lithography machine from the cloud for this path, and then the target lithography machine performs lithography and etching based on the target compensation parameters. This improves the utilization rate of the target etching reaction cavity and target lithography machine in an idle state. It not only ensures uniform pattern size in the etched wafer but also improves wafer processing efficiency.
[0068] Figure 5 A schematic diagram illustrating the correspondence between a lithography machine and an etching reaction chamber is provided for an embodiment of this application, as shown below. Figure 5 As shown, lithography machine A can correspond to etching reaction chambers A, B, C, and D respectively, with four pattern size correction paths; lithography machine B can correspond to etching reaction chambers A, B, C, and D respectively, with three or four pattern size correction paths; lithography machine C can also correspond to etching reaction chambers A, B, C, and D respectively, with three or four pattern size correction paths. That is, the number of pattern size correction paths reaches 12, a significant increase.
[0069] like Figure 5 As shown, each of the etching reaction chambers A, B, C, and D can process the wafers after photolithography from lithography machines A, B, and C. By dynamically selecting the preset compensation parameters corresponding to the pattern size correction path, the utilization rate of the etching reaction chambers is greatly improved, the wafer processing efficiency is increased, and the production capacity is significantly improved.
[0070] Optionally, Figure 6 A schematic flowchart of a wafer processing method provided in this application embodiment. Figure 5 ,like Figure 6 As shown, the process of using a target lithography machine to perform lithography on the wafer to be processed in S103 above may include: S501. Obtain the photolithography process parameters for the wafer to be processed.
[0071] S502. Using a target lithography machine, the wafer to be processed is subjected to lithography according to the lithography process parameters and target compensation parameters to obtain the lithographic wafer.
[0072] Among them, photolithography process parameters are used to constrain the basic dimensions of the circuit pattern. The basic dimensions refer to the processing dimensions in wafer fabrication before offset matching is performed.
[0073] It should be noted that photolithography process parameters can include: parameters related to the photoresist, core parameters related to the photolithography machine exposure, information related to the photomask, and interface parameters with subsequent processes. Photolithography process parameters are the standard operating procedures set at the baseline, covering the entire wafer or batch, establishing a standardized process foundation for wafer photolithography. If photolithography is performed solely based on these parameters, the resulting wafer will have uniform pattern dimensions.
[0074] In addition, the target compensation parameter is a fine-tuning of the photolithography process parameters. The target compensation parameter depends on the existence of the main program (or main recipe). The target compensation parameter performs reverse compensation on the pattern size formed based on the photolithography process parameters, so that the pattern size in the wafer after photolithography is distributed with a smaller outer circle and a larger inner circle.
[0075] Optionally, each compensation parameter corresponds to a combination of an etching reaction chamber, a lithography machine, a wafer product, a device layer of the wafer product, and a mask for processing the device layer; each preset pattern size correction path includes: a preset lithography machine, a preset mask, a preset layer, a preset etching reaction chamber, and a wafer product.
[0076] Among them, wafer products can also be called PROD; preset lithography machine can be called Litho scanner; preset mask can be called Reticle, or photomask; preset layer can be called Layer, which refers to the device layer of semiconductor device; preset etching chamber can be called Etch Chamber.
[0077] It is worth noting that the preset lithography machine determines the uniformity of the measured circuit size after lithography, and there will be differences between different lithography machines; there will also be differences between different products, among which frame cell (scribing groove) and design differences will affect the difference in pattern size; the reason for specifying preset layers is that not every layer needs DOMA, so the layers that require DOMA are preset layers; the etching equipment determines the uniformity of the pattern size after etching, and there are machine differences between different preset etching reaction chambers, so it is necessary to specify a specific preset etching reaction chamber.
[0078] In summary, based on multiple parameters such as preset lithography machine, preset mask, preset layer, preset etching reaction chamber, and wafer product, a detailed and accurate preset pattern size correction path is constructed. Corresponding preset compensation parameters are deployed for each preset pattern size correction path, thereby achieving refined circuit size reverse compensation.
[0079] Optionally, before selecting the target pattern size correction path corresponding to the target etching reaction cavity and the target lithography machine from multiple preset pattern size correction paths in the above S301, the method may further include: responding to the input configuration information and determining multiple preset pattern size correction paths and corresponding multiple preset compensation parameters.
[0080] In some implementations, in response to configuration operations input by the user in the graphical interface, multiple preset graphic size correction paths and multiple preset compensation parameters corresponding to each preset graphic size correction path are established.
[0081] In practical applications, the number of Litho scanners * the number of Etch tool chambers represents the number of multiple preset pattern size correction paths.
[0082] Optionally, the process of receiving the wafer to be processed in S104 above may include: generating a dispatch request based on the target etching reaction chamber and the target lithography machine; and receiving the wafer to be processed corresponding to the dispatch request.
[0083] Specifically, a dispatch request is generated for the target etching reaction chamber and the target lithography machine; based on the dispatch request, wafers to be processed are allocated to the target etching reaction chamber and the target lithography machine.
[0084] In summary, the embodiments of this application can dynamically determine the target pattern size correction path that can be processed on wafers, deploy multiple preset pattern size correction paths and corresponding preset compensation parameters in the cloud, and dynamically configure target compensation parameters for the target lithography machine from the cloud for the target pattern size correction path. This can improve the utilization rate of the target etching reaction chamber and the target lithography machine in the idle state, realize automatic dispatch, and maximize production capacity.
[0085] The following describes the wafer processing apparatus, wafer processing equipment, and storage medium used to execute the wafer processing method provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the above-mentioned wafer processing method, which will not be repeated below.
[0086] Figure 7 This is a schematic diagram of the structure of a wafer processing apparatus provided in an embodiment of this application, as shown below. Figure 7 As shown, the device includes: The acquisition module 101 is used to acquire the machine status data of the etching machine.
[0087] The determination module 102 is used to determine the target etching reaction cavity and the target lithography machine to be operated based on the machine status data; and to determine the target compensation parameter from multiple preset compensation parameters according to the target etching reaction cavity and the target lithography machine.
[0088] The receiving module 103 is used to receive the wafer to be processed.
[0089] The processing module 104 is used to perform photolithography on the wafer to be processed using the target photolithography machine. The target compensation parameter is used to perform reverse compensation on the pattern size of the device to be formed on the wafer to be processed during the photolithography process. The target etching reaction chamber is used to perform etching on the photolithographic wafer to obtain an etched wafer.
[0090] Optionally, the determining module 102 is specifically used to determine the cavity status of multiple etching reaction cavities on the etching machine based on the machine status data, and to determine the etching reaction cavity in the idle state as the target etching reaction cavity; and to determine the lithography machine in the idle state as the target lithography machine based on the lithography machine status of multiple lithography machines.
[0091] Optionally, the determining module 102 is specifically used to select, from a plurality of preset pattern size correction paths, the target pattern size correction path corresponding to the target etching reaction cavity and the target lithography machine, wherein the plurality of preset pattern size correction paths respectively correspond to the plurality of preset compensation parameters; and to obtain the corresponding target compensation parameters based on the target pattern size correction path.
[0092] Optionally, the determining module 102 is specifically used to call the equipment automation program; use the equipment automation program to call the lithography task; use the lithography task to call the preset compensation parameters corresponding to the target pattern size correction path from the preset shared storage space as the target compensation parameters; The preset shared storage space stores multiple preset compensation parameters corresponding to multiple preset graphic size correction paths.
[0093] Optionally, each compensation parameter corresponds to a combination of an etching reaction chamber, a lithography machine, a wafer product, a device layer of the wafer product, and a mask for processing the device layer; Each preset pattern size correction path includes: preset lithography machine, preset mask, preset device layer, preset etching reaction chamber, and wafer product.
[0094] Optionally, the processing module 104 is specifically used to obtain the photolithography process parameters for photolithography processing of the wafer to be processed; and to perform photolithography processing on the wafer to be processed using the target photolithography machine according to the photolithography process parameters and the target compensation parameters to obtain the photolithographically processed wafer.
[0095] Optionally, the receiving module 103 is specifically used to generate a dispatch request based on the target etching reaction chamber and the target lithography machine; and to receive the wafer to be processed corresponding to the dispatch request.
[0096] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0097] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0098] Figure 8 This is a schematic diagram of the structure of a wafer processing device provided in an embodiment of this application, as shown below. Figure 8 As shown, the wafer processing device includes: a processor 201 and a memory 202.
[0099] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiments. The specific implementation and technical effects are similar, and will not be described in detail here.
[0100] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.
[0101] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0102] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0103] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0104] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0105] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A wafer processing method, characterized by, The method comprises: acquiring machine state data of an etching machine; based on the machine state data, determining a target etching reaction chamber and a target photolithography machine to be worked; determining a target compensation parameter from a plurality of preset compensation parameters according to the target etching reaction chamber and the target photolithography machine; receiving a wafer to be processed; using the target photolithography machine to perform photolithography processing on the wafer to be processed, and the target compensation parameter is used to perform reverse compensation on the pattern size of a device to be formed on the wafer to be processed during photolithography processing; using the target etching reaction chamber to perform etching processing on the wafer after photolithography to obtain an etched wafer.
2. The method of claim 1, wherein, The method comprises: determining the chamber state of a plurality of etching reaction chambers on the etching machine according to the machine state data, and determining an etching reaction chamber in an idle state as a target etching reaction chamber; determining a photolithography machine in an idle state as a target photolithography machine according to the photolithography machine state of a plurality of photolithography machines.
3. The method of claim 1, wherein, The method comprises: selecting a target pattern size correction path corresponding to the target etching reaction chamber and the target photolithography machine from a plurality of preset pattern size correction paths, wherein the plurality of preset pattern size correction paths correspond to the plurality of preset compensation parameters respectively; obtaining a target compensation parameter corresponding to the target pattern size correction path.
4. The method of claim 3, wherein, The method comprises: calling a device automation program; using the device automation program to call a photolithography task; using the photolithography task to call a preset compensation parameter corresponding to the target pattern size correction path from a preset shared storage space as a target compensation parameter; wherein the preset shared storage space stores a plurality of preset compensation parameters corresponding to a plurality of preset pattern size correction paths.
5. The method of claim 3, wherein, Each compensation parameter corresponds to a combination of an etching reaction chamber, a photolithography machine, a wafer product, a device layer of the wafer product, and a mask for processing the device layer. Each preset pattern size correction path comprises a preset photolithography machine, a preset mask, a preset device layer, a preset etching reaction chamber, and a wafer product.
6. The method of claim 1, wherein, The method comprises: obtaining photolithography process parameters for performing photolithography processing on the wafer to be processed; using the target photolithography machine to perform photolithography processing on the wafer to be processed according to the photolithography process parameters and the target compensation parameter to obtain a wafer after photolithography.
7. The method of claim 1, wherein, The method comprises: generating a dispatch request based on the target etching reaction chamber and the target photolithography machine; receiving a wafer to be processed corresponding to the dispatch request.
8. A wafer processing apparatus, characterized by comprising: The device comprises: an acquisition module configured to acquire machine state data of an etching machine; A determining module is configured to determine a target etching reaction chamber and a target photolithography machine to be operated based on the machine state data, and determine a target compensation parameter from a plurality of preset compensation parameters according to the target etching reaction chamber and the target photolithography machine. A receiving module is configured to receive a wafer to be processed. A processing module is configured to perform photolithography processing on the wafer to be processed by using the target photolithography machine, and the target compensation parameter is used to perform reverse compensation on a pattern size of a device to be formed on the wafer to be processed in the photolithography process; and perform etching processing on the wafer after the photolithography by using the target etching reaction chamber to obtain a wafer after etching.
9. A wafer processing apparatus, characterized by comprising: Comprise: A memory and a processor, the memory stores a computer program executable by the processor, and the processor implements the wafer processing method in any one of claims 1-7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is read and executed to implement the wafer processing method in any one of claims 1-7.