Laminated packaging module

Abstract

A laminated packaging module comprises a circuit board frame, an upper-layer circuit board and a lower-layer circuit board, and all the board layers are welded into a whole through bonding pads. The circuit board further comprises two or more than two wafers in one group, and bottom surface bonding pads of the two or more than two wafers are welded on the top circuit layer of the lower circuit board, correspondingly connected with one group of bonding pads on the top circuit layer of the lower circuit board and located in a space defined by the circuit board frame, the upper circuit board and the lower circuit board. By adopting the circuit board frame, the wafer is packaged in the laminated module by using the laminated circuit board, and various wafer combinations can be flexibly packaged; the heat dissipation efficiency is improved; and meanwhile, the chip bonding process is reduced, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a smart module package for electronic products. A circuit board frame is used; a plurality of circuit boards are welded to form a laminated module. It relates to a circuit board process. BACKGROUND

[0002] With the progress of science and technology, circuit boards are widely used in electronic products. The circuit board is an important electronic component, which is the support of electronic components and the carrier of electrical interconnection of electronic components.

[0003] The circuit board is composed of a circuit layer and a substrate layer; different types are produced by different substrate layer materials and different numbers of layers.

[0004] One of the main components of electronic products is a chip; the chip is packaged from a wafer. The existing chip packaging process mainly uses a bonding process to weld the pads on the wafer and the chip pins with metal wires.

[0005] In the product, due to the volume, heat dissipation and testing, etc., a group of wafers will be sealed into a module for use; but the module requires various combinations of wafers, and various sizes of molds are needed to adapt, which is costly; due to the different requirements of current size, especially some large current products, the existing metal wire bonding process is difficult to adapt to the various requirements of different modules. SUMMARY

[0006] In view of the above problems, the present application aims to provide a laminated package module, which can realize various combinations of wafers by using mature process, and increase production efficiency.

[0007] To achieve the technical purpose, the scheme of the present application is: a laminated packaging module, comprising a circuit board frame, the circuit board frame is composed of a circuit board frame top layer circuit layer, a circuit board frame substrate layer and a circuit board frame bottom layer circuit layer, the circuit board frame top layer circuit layer and the circuit board frame bottom layer circuit layer are both arranged with two or more than two groups of pads, the two groups of pads of the top layer circuit layer and the two groups of pads of the bottom layer circuit layer are respectively corresponding to each other in pairs, and each pair of pads is connected through a through hole; further comprising an upper layer circuit board, the upper layer circuit board is composed of an upper layer circuit board circuit layer and an upper layer circuit board substrate layer, two or more than two groups of pads are arranged on the circuit layer of the upper layer circuit board, the two or more than two groups of pads on the top layer circuit layer of the circuit board frame are welded with the corresponding pads in the group of pads on the circuit layer of the upper layer circuit board, and the upper layer circuit board and the circuit board frame are welded into an integrated whole; further comprising a lower layer circuit board, the lower layer circuit board is composed of a lower layer circuit board top layer circuit layer, a lower layer circuit board substrate layer and a lower layer circuit board bottom layer circuit layer, two or more than two groups of pads are arranged on the top layer circuit layer and the bottom layer circuit layer of the lower layer circuit board, the two groups of pads arranged on the bottom layer circuit layer of the lower layer circuit board are connected through a through hole with the corresponding pads in the two groups of pads arranged on the top layer circuit layer of the lower layer circuit board, the two groups of pads on the bottom layer circuit layer of the circuit board frame are welded with the corresponding pads in the two groups of pads on the top layer circuit layer of the lower layer circuit board, and the lower layer circuit board and the circuit board frame are welded into an integrated whole; further comprising two or more than two groups of wafers, the bottom pads of the two or more than two groups of wafers are welded on the top layer circuit layer of the lower layer circuit board and welded with the corresponding pads in the two groups of pads on the top layer circuit layer of the lower layer circuit board, and are located in the space surrounded by the circuit board frame, the upper layer circuit board and the lower layer circuit board.

[0008] As a preferred, the top surface of the two or more than two groups of wafers is arranged with pads, and the pads on the top surface are welded on the circuit layer of the upper layer circuit board and welded with the corresponding pads in the two groups of pads arranged on the circuit layer of the upper layer circuit board.

[0009] The beneficial effects of the technical scheme are: mature and low-cost process can be used to adapt to the requirements of various module sizes; the requirements of production process are reduced; the preparation of the module is facilitated, and the cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 It is a cross-sectional schematic view of the laminated packaging module of the first embodiment of the present application.

[0011] Figure 2 It is a top view of the laminated packaging module of the first embodiment of the present application without the upper layer circuit board. Schematic view.

[0012] Figure 3 It is a bottom surface schematic view of the upper layer circuit board of the first embodiment.

[0013] Figure 4 This is a bottom view of a specific embodiment with the lower circuit board removed.

[0014] Figure 5 This is a schematic diagram of the top layer of the lower layer circuit in a specific embodiment.

[0015] Figure 6 This is a schematic diagram of the bottom layer of the circuit board in a specific embodiment. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0017] like Figure 1 The diagram shown is a cross-sectional view of a stacked packaging module according to a specific embodiment of the present invention. It includes a circuit board frame 1, which consists of a top circuit layer 11, a substrate layer 12, and a bottom circuit layer 13. Both the top and bottom circuit layers 11 and 13 have two or more sets of pads. The pads on the top and bottom circuit layers correspond to each other, and each pair of pads is connected via vias 14. The module also includes an upper circuit board 2, which consists of an upper circuit layer 21 and a substrate layer 22. The upper circuit board 2 has two or more sets of pads on its circuit layer 21. The two or more sets of pads on the top circuit layer 11 of the circuit board frame 1 are soldered to the corresponding pads on the upper circuit layer 21, thus soldering the upper circuit board 2 and the circuit board frame 1 together. Finally, it includes a lower circuit board 3. The lower circuit board 3 consists of a top circuit layer 31, a substrate layer 32, and a bottom circuit layer 33. Two or more sets of pads are arranged on both the top circuit layer 31 and the bottom circuit layer 33. The pads on the bottom circuit layer 33 are connected to the corresponding pads on the top circuit layer 31 via vias. The pads on the bottom circuit layer 13 of the circuit board frame 1 are soldered to the corresponding pads on the top circuit layer 31 of the lower circuit board, thus soldering the lower circuit board 3 and the circuit board frame 1 together. It also includes two or more sets of wafers 4, whose bottom pads are soldered to the top circuit layer 31 of the lower circuit board and to the corresponding pads on the top circuit layer 31, residing within the space enclosed by the circuit board frame 1, the upper circuit board 2, and the lower circuit board 3.

[0018] like Figure 2The diagram shown is a top view of a specific embodiment of the present invention with the upper circuit board removed. A set of pads 111-116 are arranged on the top circuit layer 11 of the circuit board frame 1. These pads have through-holes that are electrically connected to corresponding pads in a set of pads on the bottom circuit layer 13 of the circuit board frame. A set of wafers 41 and 42 resides in the space enclosed by the circuit board frame 1 and the lower circuit board 3. Pads 411 and 421 are arranged on their top surfaces, and these top pads are soldered to corresponding pads on the circuit layer 21 of the upper circuit board 2.

[0019] like Figure 3 The diagram shown is a bottom view of the upper circuit board in a specific embodiment. On the circuit layer 21 of the upper circuit board 2, a set of pads 211-218 are arranged, wherein pads 211-216 are soldered to pads 111-116 on the top circuit layer 11 of the circuit board frame 1, and pads 217 and 218 are soldered to pads 411 and 421 arranged on the top surface of wafers 41 and 42.

[0020] like Figure 4 The diagram shown is a bottom view of a specific embodiment with the lower circuit board removed. A set of pads 131-136 are arranged on the bottom circuit layer 13 of the circuit board frame 1. These pads have through-holes that are electrically connected to corresponding pads in a set of pads on the top circuit layer 11 of the circuit board frame. A set of wafers 41 and 42 resides within the space enclosed by the circuit board frame 1 and the upper circuit board 2. Pads 412 and 413 are arranged on the bottom surface of wafer 41, and pads 422 and 423 are arranged on the bottom surface of wafer 42. The pads on the bottom surfaces of wafers 41 and 42 are soldered to corresponding pads on the top circuit layer 31 of the lower circuit board 3.

[0021] like Figure 5 The diagram shown is a schematic diagram of the top layer of the lower circuit in a specific embodiment. On the top layer 31 of the lower circuit board, a set of pads 311-320 are arranged, wherein pads 311-316 are correspondingly soldered to a set of pads 131-136 arranged on the bottom layer 13 of the circuit board frame 1; wherein pads 317 and 318 are correspondingly soldered to pads 412 and 413 arranged on the bottom surface of wafer 41, and wherein pads 319 and 320 are correspondingly soldered to pads 422 and 423 arranged on the bottom surface of wafer 42.

[0022] like Figure 6 The diagram shown is a schematic of the bottom layer of a lower circuit board in a specific embodiment. On the bottom circuit layer 33 of the lower circuit board, a set of pads 331-336 are arranged. The pads are equipped with through holes, which are electrically connected to the corresponding pads 311-316 in the set of pads arranged on the top circuit layer 31 of the lower circuit board.

[0023] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent substitutions, and improvements made to the above embodiments based on the technical essence of the present invention should be included within the protection scope of the present invention.

Claims

1. A stacked package module, characterized by: The application relates to a circuit board frame, an upper-layer circuit board and a lower-layer circuit board.

2. The PCB laminate module of claim 1, wherein: The application relates to a circuit board frame, an upper-layer circuit board and a lower-layer circuit board.

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