Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the preparation method comprises the steps: applying a conductive adhesive to the top ends of a plurality of first conductive columns of a chip, so as to form corresponding first bumps on the plurality of first conductive columns; drying the first salient points on the plurality of first conductive columns so as to cure the first salient points; applying conductive adhesive to the top ends of a plurality of second conductive columns of the carrier plate so as to form corresponding second salient points on the plurality of second conductive columns; inverting the chip with the cured first salient points so as to enable the cured first salient points to be aligned with the second salient points; and pressing and heating the chip and the carrier plate so as to bond and cure the second salient points and the cured first salient points. According to the preparation method, the technological process of the semiconductor device can be simplified, the production period of the semiconductor device can be shortened, and the packaging cost of the semiconductor device can be greatly reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the field of advanced electronics packaging, especially in the interconnection process between chips and carrier boards (such as PCBs, ceramic carrier boards, or silicon interposers), solder paste is generally used for connection. Applying solder paste by dispensing and reflow soldering is the widely adopted technical approach.

[0003] However, in related technologies, the solder paste dispensing process relies on a complex UBM (Under-Bump Metallization) structure, which means that a special structure called "Under-Bump Metallization (UBM)" must be pre-fabricated on the pads of the chip and the carrier board. Due to the complexity and numerous steps in the UBM fabrication process, production time and manufacturing costs are significantly increased. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method to solve the technical problems in the related art, where the UBM fabrication process is complex and involves many steps, resulting in long production time and high fabrication cost of semiconductor devices.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for fabricating a semiconductor device, the method comprising: applying conductive adhesive to the top of a plurality of first conductive pillars of a chip to form corresponding first bumps on the plurality of first conductive pillars; curing the first bumps on the plurality of first conductive pillars; applying conductive adhesive to the top of a plurality of second conductive pillars of a carrier plate to form corresponding second bumps on the plurality of second conductive pillars; inverting the chip with the cured first bumps to align the cured first bumps with the second bumps; pressing and heating the chip and the carrier plate to bond and cure each second bump with the corresponding cured first bump.

[0006] In some embodiments, the conductive adhesive includes a base resin and a conductive filler, wherein the base resin includes at least one of epoxy resin, polyurethane, acrylate and silicone; and the metallic filler includes at least one of silver, copper and nickel.

[0007] In some embodiments, applying conductive adhesive to the tops of a plurality of first conductive pillars of a chip includes mounting the chip on the dispensing platform of a dispensing machine and positioning it; controlling the dispensing machine to apply conductive adhesive to the tops of the plurality of first conductive pillars according to a first preset program to form corresponding first bumps on the plurality of first conductive pillars; applying conductive adhesive to the tops of a plurality of second conductive pillars of a carrier plate includes mounting the carrier plate on the dispensing platform of a dispensing machine and positioning it; controlling the dispensing machine to apply conductive adhesive to the tops of the plurality of second conductive pillars according to a second preset program to form corresponding second bumps on the plurality of second conductive pillars.

[0008] In some embodiments, applying conductive adhesive to the tops of a plurality of first conductive pillars of a chip includes placing the chip on the printing platform of a screen printing machine and positioning it; the screen printing machine applies conductive adhesive to the tops of the plurality of first conductive pillars through a stencil to form corresponding first bumps on the plurality of first conductive pillars; applying conductive adhesive to the tops of a plurality of second conductive pillars of a carrier plate includes placing the carrier plate on the printing platform of a screen printing machine and positioning it; the screen printing machine applies conductive adhesive to the tops of the plurality of second conductive pillars through a stencil to form corresponding second bumps on the plurality of second conductive pillars.

[0009] In some embodiments, after the step of forming corresponding first bumps on multiple first conductive pillars, the fabrication method further includes: performing microscopic inspection on the first bumps on multiple first conductive pillars; if it is confirmed that the height and connection state of the multiple first bumps meet a preset first qualification condition, then performing a step of curing the first bumps on multiple first conductive pillars; if it is confirmed that the height and connection state of the multiple first bumps do not meet the preset first qualification condition, then cleaning the chip; after the step of forming corresponding second bumps on multiple second conductive pillars, the fabrication method further includes: performing microscopic inspection on the second bumps on multiple second conductive pillars; if it is confirmed that the height and connection state of the multiple second bumps meet a preset second qualification condition, then performing a step of inverting the chip with the cured first bumps; if it is confirmed that the height and connection state of the multiple second bumps do not meet the preset second qualification condition, then cleaning the carrier board.

[0010] In some embodiments, inverting a chip with a cured first bump to align a second bump with the cured first bump includes: placing a carrier plate on an alignment stage, inverting the chip on a suction head opposite the alignment stage, and marking positions to align the second bump on the carrier plate with the corresponding first bump on the chip.

[0011] In some embodiments, different first protrusions have the same height relative to the first conductive post, and different second protrusions have the same height relative to the second conductive post.

[0012] In some embodiments, the curing temperature of the first bump and the second bump is 100-150 degrees Celsius.

[0013] In some embodiments, the first convex point and the second convex point are cylindrical or hemispherical in shape.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a semiconductor device, which is prepared by the preparation method of any of the above embodiments.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the semiconductor device fabrication method of this application includes: applying conductive adhesive to the tops of multiple first conductive pillars of a chip to form corresponding first bumps on the multiple first conductive pillars; curing the first bumps on the multiple first conductive pillars; applying conductive adhesive to the tops of multiple second conductive pillars of a carrier plate to form corresponding second bumps on the multiple second conductive pillars; inverting the chip with the cured first bumps to align the cured first bumps with the second bumps; and pressing and heating the chip and the carrier plate to bond and cure each second bump with its corresponding cured first bump. In this application, conductive adhesive is used as the interconnect material to directly form bumps on the first conductive pillars of the chip and the second conductive pillars of the carrier plate, eliminating the indispensable and complex under-bump metallization (UBM) structure in traditional soldering processes. This greatly simplifies the semiconductor device fabrication process, shortens the semiconductor device production cycle, and reduces packaging costs. Furthermore, the use of conductive adhesive enables low-temperature processes, thus solving the problem of photonic crystal failure at high temperatures. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure of a semiconductor device chip and a first bump before curing provided in some embodiments of this application; Figure 3 yes Figure 1 A flowchart illustrating an embodiment of step S11; Figure 4 yes Figure 1 A flowchart illustrating another embodiment of step S11; Figure 5 yes Figure 2A schematic diagram of the structure of a semiconductor device chip and its first bump after curing; Figure 6 This is a schematic diagram of the structure of the carrier plate and the second bump of the semiconductor device provided in some embodiments of this application; Figure 7 yes Figure 1 A flowchart illustrating an embodiment of step S13; Figure 8 yes Figure 1 A flowchart illustrating another embodiment of step S13; Figure 9 These are schematic diagrams of the aligned chip and carrier board provided in some embodiments of this application; Figure 10 yes Figure 9 The diagram shows the structure after the chip and carrier board are bonded together. Figure 11 This application provides schematic diagrams of the structure of semiconductor devices comprising multi-layer chip structures in some embodiments. Detailed Implementation

[0018] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] With the rapid development of semiconductor technology, chip integration is constantly increasing, and the number of input / output ports is continuously growing, posing increasingly severe challenges to packaging technology. Currently, in the interconnection process between chips and carrier boards, flip-chip technology has become the mainstream due to its advantages such as high density, short interconnects, and high performance.

[0022] Flip-chip packaging technology, as an advanced packaging method, is of great significance in the field of electronic component manufacturing. It not only improves product performance but also promotes the miniaturization, weight reduction, and multifunctionality of electronic products. With continuous technological advancements and innovation, flip-chip packaging technology will continue to improve and develop, bringing more opportunities and challenges to the electronics industry.

[0023] This application provides a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device provided in this application has the advantages of simplified process, short process cycle and low cost. The method for fabricating the semiconductor device provided in this application will be described in detail below.

[0024] Please see Figure 1 As shown, Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to some embodiments of this application. Specifically, the fabrication method includes the following steps: S11: Apply conductive adhesive to the top of the plurality of first conductive pillars of the chip to form corresponding first bumps on the plurality of first conductive pillars.

[0025] After obtaining a clean chip, conductive adhesive is applied to the top of multiple first conductive pillars of the chip, thereby forming corresponding first bumps on the multiple first conductive pillars, so as to create the initial physical structure for the electrical and mechanical connection between the chip and the carrier board.

[0026] like Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a semiconductor device chip and a first bump before curing provided in some embodiments of this application. After dispensing, a plurality of first bumps 31 are provided on the first conductive pillar 22 of the chip 21.

[0027] Furthermore, before applying adhesive to chip 21, chip 21 can be cleaned, and then adhesive can be applied to the cleaned chip 21.

[0028] Conductive adhesives possess both conductive and adhesive properties. The materials of conductive adhesives may include a base resin and conductive fillers. The base resin may include at least one of epoxy resin, polyurethane, acrylate, and silicone; the metallic filler may include at least one of silver, copper, and nickel.

[0029] Metal fillers are components that provide electrical conductivity and are typically composed of highly conductive metal particles. Fillers can take various forms, such as spherical, sheet-like, or dendritic shapes.

[0030] Silver possesses extremely high electrical conductivity and chemical stability, is not easily oxidized, and ensures low resistance at interconnect points. Metal fillers can utilize micron-sized silver flakes, nano-silver particles, etc. During hot pressing and curing, nano-silver particles may also undergo a sintering effect, forming metallurgical connections with even better conductivity. Copper is less expensive, but copper powder is prone to oxidation and typically requires an anti-oxidation coating (such as silver-plated copper) or the use of antioxidants. Nickel can be used in specific applications where conductivity requirements are not as high.

[0031] The base resin is the component that forms the bond strength and mechanical framework, and also serves as the carrier for the conductive filler. Epoxy resin is a preferred material because it has good adhesion, excellent chemical resistance, high mechanical strength after curing, and a wide range of adjustable curing conditions (temperature, time).

[0032] In some embodiments, such as Figure 3 As shown, Figure 3 yes Figure 1 A schematic flowchart of one embodiment of step S11 shows that conductive adhesive is applied to the tops of a plurality of first conductive pillars 22 of chip 21, including: S111: Install the chip on the dispensing platform of the dispensing machine and position it.

[0033] S112: Control the dispensing machine to dispense conductive adhesive onto the tops of multiple first conductive pillars according to a first preset program, so as to form corresponding first protrusions on the multiple first conductive pillars.

[0034] Chip 21 is mounted on the dispensing platform of the dispensing machine for positioning and alignment. The dispensing machine marks and records the reference point position and then performs programmed processing. The dispensing machine applies conductive adhesive to the tops of multiple first conductive pillars 22 according to a first preset program to form corresponding first protrusions 31 on the multiple first conductive pillars 22.

[0035] The different first protrusions 31 have the same height relative to the first conductive post 22. That is, the height of each first protrusion 31 is as consistent as possible so that its height consistency is within an acceptable range.

[0036] The above embodiment uses a dispensing machine for dispensing, which is simple and allows for precise control of the size of the first protrusion 31.

[0037] In other embodiments, such as Figure 4 As shown, Figure 4 yes Figure 1 A schematic flowchart of another embodiment of step S11 shows that conductive adhesive is applied to the tops of a plurality of first conductive pillars on the chip, including: S101: Place the chip on the printing platform of the screen printing machine and position it.

[0038] S102: The screen printing machine applies conductive adhesive to the top of multiple first conductive pillars through a screen to form corresponding first protrusions on the multiple first conductive pillars.

[0039] Chip 21 is mounted on the printing platform of a screen printing machine. Typically, the screen printing machine needs to align the stencil markings and chip 21 markings by rotating it forward, backward, left, right, up, and down. Then, it executes a pre-set dispensing program to dispense adhesive based on the spatial position of chip 21. Since adhesive may overflow from the back of the stencil after dispensing, the stencil can be replaced as needed. The above embodiment uses a screen printing machine for dispensing, resulting in a relatively fast dispensing speed.

[0040] Optionally, after applying adhesive to the chip 21, the first bumps 31 on the plurality of first conductive posts 22 can be inspected under a microscope. If it is confirmed that the height and connection status of the plurality of first bumps 31 meet the preset first qualification conditions, then the step of curing the first bumps 31 on the plurality of first conductive posts 22 is performed; if it is confirmed that the height and connection status of the plurality of first bumps 31 do not meet the preset first qualification conditions, then the chip 21 is cleaned.

[0041] Specifically, after the adhesive is applied to the chip 21, it can be inspected under a microscope. If the multiple first bumps 31 have no height difference or the height difference is within an acceptable range, and there is no connection between different first bumps 31 to avoid short circuits, then the adhesive application of the chip 21 can be confirmed as qualified, and subsequent curing operations can proceed. Otherwise, cleaning and re-application are required. This can improve the yield of the finished product.

[0042] S12: Curing the first bumps on multiple first conductive pillars.

[0043] After the adhesive is applied to the chip 21, the first bump 31 can be dried using a drying device to cure it.

[0044] When using conductive adhesive, the curing temperature can be selected from 100-150 degrees Celsius. In this embodiment, the heating temperature can be significantly reduced from over 240°C in traditional solder paste reflow soldering to around 100 degrees Celsius, the curing temperature of the conductive adhesive. This low-temperature process can effectively reduce the impact of the chip 21 and carrier board 23 ( Figure 6 The significant thermal stress caused by the mismatch in thermal expansion coefficients between the photonic crystal and the interconnect material reduces the risk of chip warpage, cracking, or interface delamination, thus significantly improving the long-term reliability of the packaging structure. Simultaneously, the low-temperature characteristics address the issue of high-temperature failure in photonic crystals, improving yield.

[0045] Furthermore, the "pre-curing" strategy employed in this application involves drying and curing the first bumps 31 before final bonding, transforming them from a semi-liquid state into a fixed solid structure. During flip-chip hot pressing, these pre-cured first bumps 31 do not flow or collapse like molten solder, thus essentially eliminating the possibility of bridging short circuits between adjacent first bumps 31 from a physical mechanism perspective. This is crucial for micro-pitch, high-density input / output interconnects and can significantly improve the packaging yield of semiconductor devices.

[0046] S13: Apply conductive adhesive to the top of the plurality of second conductive pillars on the carrier plate to form corresponding second protrusions on the plurality of second conductive pillars.

[0047] The substrate is also coated with conductive adhesive. Specifically, for example... Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a carrier plate and a second bump of a semiconductor device provided in some embodiments of this application. Conductive adhesive is applied to the top of the second conductive post 24 of the carrier plate 23, thereby forming a plurality of second bumps 32 on the carrier plate 23.

[0048] The carrier plate 23 can be a substrate or other chip 21. That is, the preparation method of this application can be used for the connection between chip 21 and substrate, or for the connection between chip 21 and chip 21.

[0049] In some embodiments, such as Figure 7 As shown, Figure 7 yes Figure 1 A schematic flowchart of an embodiment of step S13, in which conductive adhesive is applied to the tops of a plurality of second conductive pillars on a carrier plate, including: S131: Install the carrier plate on the dispensing platform of the dispensing machine and position it.

[0050] S132: Control the dispensing machine to dispense conductive adhesive onto the tops of multiple second conductive pillars according to a second preset program, so as to form corresponding second protrusions on the multiple second conductive pillars.

[0051] First, the carrier plate 23 is installed on the dispensing platform of the dispensing machine and positioned and aligned. After the dispensing machine marks and records the position of the reference point, it performs programmed processing. The dispensing machine applies conductive adhesive to the tops of multiple second conductive pillars 24 according to the second preset program, so as to form corresponding second protrusions 32 on the multiple second conductive pillars 24.

[0052] Different second protrusions 32 have the same height relative to the second conductive post 24; that is, the height of each second protrusion 32 is as consistent as possible to ensure that the height consistency is within an acceptable error range. In the above embodiment, adhesive is dispensed onto the carrier plate 23 using a dispensing machine, allowing for controllable conductive adhesive size and achieving a good dispensing effect.

[0053] In other embodiments, such as Figure 8 As shown, Figure 8 yes Figure 1 A schematic flowchart of another embodiment of step S13 is shown. In this embodiment, conductive adhesive is applied to the tops of a plurality of second conductive pillars on the carrier plate, including: S301: Place the carrier plate on the printing platform of the screen printing machine and position it.

[0054] S302: The screen printing machine applies conductive adhesive to the top of multiple second conductive posts through a screen to form corresponding second protrusions on the multiple second conductive posts.

[0055] The carrier plate 23 is mounted on the printing platform of the screen printing machine. Typically, the screen printing machine needs to align the markings on the stencil and the carrier plate 23 by rotating it forward, backward, left, right, up, and down. A pre-set dispensing program is then executed based on the spatial position of the carrier plate 23. Since there is a problem of glue overflowing from the back of the stencil after dispensing, the stencil can be replaced as needed. In the above embodiment, the carrier plate 23 is dispensed using a screen printing machine, resulting in a relatively fast dispensing speed.

[0056] Optionally, after applying adhesive to the carrier plate 23, the second bumps 32 on the multiple second conductive posts 24 can be inspected under a microscope. If it is confirmed that the height and connection status of the multiple second bumps 32 meet the preset second qualification conditions, the step of inverting the chip 21 with the cured first bumps 31 is performed. If it is confirmed that the height and connection status of the multiple second bumps 32 do not meet the preset second qualification conditions, the carrier plate 23 is cleaned.

[0057] Specifically, after the adhesive is applied to the carrier plate 23, it can be inspected under a microscope. If the multiple second protrusions 32 have no height difference or the height difference is within an acceptable range, and there is no connection between different second protrusions 32 to avoid short circuits, then the adhesive application on the carrier plate 23 can be confirmed as qualified, and subsequent bonding operations can proceed. Otherwise, the carrier plate 23 needs to be cleaned and the adhesive application repeated. This can improve the yield of the finished product.

[0058] S14: Invert the chip with the cured first bump so that the cured first bump is aligned with the second bump.

[0059] Please refer to Figure 9 As shown, Figure 9 This is a schematic diagram of the aligned chip and carrier plate provided in some embodiments of this application. After the chip 21 and carrier plate 23 are coated with adhesive, the first bump 31 on the chip 21 is the cured conductive adhesive, and the second bump 32 on the carrier plate 23 is the uncured conductive adhesive. When the chip 21 is inverted, it will not deform because the first bump 31 has been cured.

[0060] In some embodiments, the alignment process between the chip 21 and the carrier plate 23 includes: placing the carrier plate 23 on an alignment stage, inverting the chip 21 onto a suction head on the opposite side of the alignment stage, and marking the position so that the second protrusion 32 on the carrier plate 23 aligns with the first protrusion 31 on the chip 21. This method simplifies the alignment process between the chip 21 and the carrier plate 23 and improves alignment accuracy.

[0061] S15: Press and heat the chip and the carrier board to bond and cure the second bump and the cured first bump.

[0062] Please refer to Figure 10 As shown, Figure 10 yes Figure 9 The diagram shows the structure after the chip and carrier plate are bonded. The inverted chip 21 is aligned with the carrier plate 23 and then installed upside down. A hot press can be used to press and heat the chip 21 and carrier plate 23 to bond and cure the second bump 32 and the cured first bump 31. During bonding, the uncured second bump 32 can be used for bonding, while the cured first bump 31 provides support for the chip 21.

[0063] The conductive adhesive exhibits compressibility and viscoelasticity during hot pressing, effectively absorbing and compensating for microscopic coplanarity deviations between the chip 21 and the carrier plate 23. This ensures uniform and reliable contact at all interconnect points, reducing solder joint defects caused by insufficient local pressure. Furthermore, the cured conductive adhesive forms a high-molecular-weight three-dimensional network structure, providing bonding strength and mechanical toughness far exceeding that of solder joints. Therefore, it enables semiconductor devices to possess excellent impact resistance, vibration resistance, and fatigue resistance.

[0064] After the first protrusion 31 and the second protrusion 32 are bonded and cured, the bonded chip 21 and carrier board 23 can be inspected to confirm that the connection is good and meets the requirements.

[0065] If multiple layers of chips 21 need to be stacked, the stacking and packaging of the multiple layers of chips 21 can be carried out using the above process. For example, Figure 11 As shown, Figure 11 This application provides schematic diagrams of semiconductor devices with multi-layer chip structures in some embodiments. The fabrication method provided in this application can be used to stack two-layer chips 21.

[0066] In the above embodiments, the first protrusion 31 and the second protrusion 32 can be columnar or hemispherical in shape to maximize the contact area between the first protrusion 31 and the second protrusion 32 and improve the bonding effect.

[0067] In summary, the above embodiments employ conductive adhesive as the interconnect material between chip 21 and carrier plate 23, directly forming bumps on the first conductive post 22 of chip 21 and the second conductive post 24 of carrier plate 23. This eliminates the need for the complex and indispensable under-bump metallization (UBM) structure required in traditional soldering processes. The fabrication process of this application eliminates a series of high-cost and complex semiconductor fabrication steps such as sputtering, photolithography, and electroplating, greatly simplifying the process flow, shortening the semiconductor device production cycle, and reducing the packaging cost of semiconductor devices. Furthermore, the core process temperature of the above embodiments is significantly reduced from above 240°C in traditional solder paste reflow soldering to the curing temperature of the conductive adhesive (150°C or below). This low-temperature process effectively reduces the enormous thermal stress caused by the mismatch in thermal expansion coefficients between chip 21, carrier plate 23, and interconnect materials, thereby reducing the risk of failure such as chip 21 warping, cracking, or interface delamination, and significantly improving the long-term reliability of the semiconductor device packaging structure.

[0068] Moreover, the equipment (drying equipment, hot pressing equipment) involved in the above embodiments are all mature and universal packaging equipment, which do not require huge investments in new special equipment and have high production line compatibility. At the same time, steps S11 and S13 can be designed to operate in parallel, simultaneously preparing bumps for chip 21 and carrier board 23, which helps to improve the overall production cycle time, shorten the preparation time of a single device, and thus improve production efficiency.

[0069] In other words, this application, through ingenious material selection and the process design of "step-by-step pre-curing and then hot-press bonding", can effectively solve the core problems of complex processes, high-temperature risks and high-density bridging in traditional solder interconnects, and provides a new path for achieving high-performance, high-yield and low-cost semiconductor packaging.

[0070] This application also provides a semiconductor device, which can be prepared by the preparation method of any of the above embodiments. For specific preparation methods of this semiconductor device, please refer to the descriptions of any of the above embodiments; they will not be repeated here.

[0071] The semiconductor device includes a chip and a carrier plate disposed opposite to each other. A first bump is provided on a first conductive post of the chip, and a second bump is provided on a second conductive post of the carrier plate. The first and second bumps are connected, and the first and second bumps are made of conductive adhesive. For a description of the first bump, second bump, and conductive adhesive, please refer to the description of the above embodiments; it will not be repeated here.

[0072] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: Conductive adhesive is applied to the top of multiple first conductive pillars of the chip to form corresponding first bumps on the multiple first conductive pillars; The first protrusions on the plurality of first conductive pillars are cured; The conductive adhesive is applied to the top of the plurality of second conductive pillars on the carrier plate to form corresponding second protrusions on the plurality of second conductive pillars; The chip with the cured first bump is inverted so that the cured first bump is aligned with the second bump. The chip and the carrier plate are pressed and heated to bond and cure each second bump and the corresponding cured first bump.

2. The preparation method according to claim 1, characterized in that, The conductive adhesive comprises: a matrix resin and conductive fillers. The basic resin includes at least one of epoxy resin, polyurethane, acrylate and silicone; The metal filler includes at least one of silver, copper, and nickel.

3. The preparation method according to any one of claims 1-2, characterized in that, The step of applying conductive adhesive to the top of the plurality of first conductive pillars of the chip includes: mounting the chip on the dispensing platform of the dispensing machine and positioning it; controlling the dispensing machine to apply the conductive adhesive to the top of the plurality of first conductive pillars according to a first preset program, so as to form corresponding first protrusions on the plurality of first conductive pillars. Applying the conductive adhesive to the top of the plurality of second conductive pillars on the carrier plate includes mounting the carrier plate on the dispensing platform of the dispensing machine and positioning it. The dispensing machine is controlled to apply conductive adhesive to the tops of the plurality of second conductive pillars according to a second preset program, so as to form corresponding second protrusions on the plurality of second conductive pillars.

4. The preparation method according to any one of claims 1-2, characterized in that, The step of applying conductive adhesive to the top of the plurality of first conductive pillars of the chip includes placing the chip on the printing platform of a screen printing machine and positioning it; the screen printing machine applies the conductive adhesive to the top of the plurality of first conductive pillars through a stencil to form corresponding first bumps on the plurality of first conductive pillars. The step of applying the conductive adhesive to the top of the plurality of second conductive pillars on the carrier plate includes placing the carrier plate on the printing platform of the screen printing machine and positioning it; the screen printing machine applies the conductive adhesive to the top of the plurality of second conductive pillars through the screen plate to form corresponding second protrusions on the plurality of second conductive pillars.

5. The preparation method according to any one of claims 1-2, characterized in that, After the step of forming corresponding first bumps on the plurality of first conductive pillars, the preparation method further includes: performing microscopic inspection on the first bumps on the plurality of first conductive pillars; if it is confirmed that the height and connection status of the plurality of first bumps meet the preset first qualification conditions, then performing a step of curing the first bumps on the plurality of first conductive pillars; if it is confirmed that the height and connection status of the plurality of first bumps do not meet the preset first qualification conditions, then cleaning the chip. After the step of forming corresponding second bumps on the plurality of second conductive pillars, the preparation method further includes: performing microscopic inspection on the second bumps on the plurality of second conductive pillars; if it is confirmed that the height and connection status of the plurality of second bumps meet the preset second qualification conditions, then performing the step of inverting the chip with the cured first bumps; if it is confirmed that the height and connection status of the plurality of second bumps do not meet the preset second qualification conditions, then cleaning the carrier plate.

6. The preparation method according to claim 1, characterized in that, The step of inverting the chip with the cured first bump so that the second bump aligns with the cured first bump includes: Place the carrier plate on the alignment stage, invert the chip onto the suction head on the opposite side of the alignment stage, and mark the position so that the second bump on the carrier plate aligns with the corresponding first bump on the chip.

7. The preparation method according to claim 1, characterized in that, Different first protrusions have the same height relative to the first conductive post, and different second protrusions have the same height relative to the second conductive post.

8. The preparation method according to claim 1, characterized in that, The curing temperature of the first bump and the second bump is 100-150 degrees Celsius.

9. The preparation method according to claim 1, characterized in that, The first protrusion and the second protrusion are cylindrical or hemispherical in shape.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the preparation method according to any one of claims 1-9.

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