Remote cache failure

Abstract

Techniques related to performing remote cache failures are disclosed. In some embodiments, the main processor circuit is configured to transmit a cache failure command to the coprocessor circuit based on execution of a remote failure instruction (e.g., ISA-defined instructions). The coprocessor circuit includes a coprocessor cache circuit and a cache failure control circuit configured to control a cache failure command transmitted by the host processor in response to the cache failure command transmitted by the host processor. One or more cache lines in a coprocessor cache circuit are disabled without executing any instructions on the coprocessor circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to computer processors, and more specifically to invalidating data in a remote cache by a processor. BACKGROUND

[0002] Processors typically include caches that provide fast access to various data relative to external memory. For example, instruction caches and data caches can store information from external memory to avoid higher latency accesses to the external memory. As another example, translation lookaside buffers (TLBs) store translations of memory addresses from page tables of external storage to avoid higher latency accesses to those translations.

[0003] In various scenarios, one processor can invalidate data in a cache of another processor. For example, a processor can map a page used by another processor in a virtual memory system. When the processor unmaps the page, the other processor can still have corresponding data in its cache that should be invalidated.

[0004] In typical processor implementations, coherency circuitry manages caches and ensures their contents are up-to-date relative to memory and other data. For example, if a cache entry is written with new data, the coherency circuitry can invalidate entries in other coherent caches. However, in some cases, a processor can unmap a page mapped for another processor that has a cache that is not managed by the coherency circuitry (e.g., a cache in a coprocessor). BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a block diagram illustrating an example host processor configured to execute a remote invalidate instruction to cause an invalidate in a coprocessor cache, in accordance with some embodiments.

[0006] Figure 2 is a block diagram illustrating an example host processor configured to maintain a page table for a coprocessor, in accordance with some embodiments.

[0007] Figure 3 is a block diagram illustrating an example system that supports both command-based remote cache invalidation and coherency-based cache invalidation, in accordance with some embodiments.

[0008] Figure 4A is a diagram illustrating example fields of a remote invalidate instruction, in accordance with some embodiments.

[0009] Figure 4B is a diagram illustrating example fields of a remote invalidate command, in accordance with some embodiments.

[0010] Figure 5 This is a block diagram illustrating a more detailed example of a main processor and coprocessor according to some implementation schemes.

[0011] Figure 6 This is a communication diagram illustrating example communication between the main processor, coprocessor, and coprocessor cache during a remote cache miss, according to some implementation schemes.

[0012] Figure 7 This is a flowchart illustrating an example method for remote cache invalidation according to some implementation schemes.

[0013] Figure 8 This is a block diagram illustrating an example computing device based on some implementation schemes.

[0014] Figure 9 These are illustrations illustrating example applications of systems and devices disclosed according to some implementation schemes.

[0015] Figure 10 This is a block diagram of an example computer-readable medium illustrating storage circuit design information according to some implementation schemes. Detailed Implementation

[0016] In the disclosed implementation, the main processor can remotely invalidate cache lines of the coprocessor cache in a safe and fine-grained manner based on the execution of a remote invalidation instruction. Specifically, the invalidation can occur without executing instructions on the coprocessor (e.g., based on bus commands to the coprocessor's invalidation control circuitry).

[0017] In various specific implementations, and in various aspects, the coprocessor is not a peer of the main processor. As an example, the system-wide coherence circuitry may not manage the coherence of one or more caches of the coprocessor. As another example, the coprocessor may operate outside of protection domains (e.g., security loops, privilege levels, etc.) implemented by the main processor. As yet another example, the coprocessor may operate within one or more shareability domains (e.g., ARM) implemented by the main processor. ® Operations outside of external / internal cacheable / shared domains in the architecture.

[0018] In some cases, the host processor may want to invalidate one or more coprocessor cache lines in such non-peer coprocessors. For example, when the host processor unmaps a page table entry, it may determine to invalidate a cache line in the coprocessor cache that contains an address in the unmapped page. As noted above, the host processor can execute a remote fail instruction to cause this fail, which ensures that the coprocessor does not keep dirty data of the unmapped page in the coprocessor cache.

[0019] In some implementations, the processor can cause remote invalidation (e.g., flush the entire coprocessor cache) at a coarse granularity. In some embodiments, in contrast, remote cache invalidation can be performed at a finer granularity (e.g., at cache line granularity), which can advantageously reduce disturbance to other cached data and thereby improve performance.

[0020] In some implementations, the processor can cause the coprocessor to perform software-based invalidation, e.g., using an inter-processor interrupt to trigger execution of an instruction on the coprocessor to cause the coprocessor cache line to be invalidated. However, software-based coprocessor cache invalidation can present potential security and performance issues. For example, the coprocessor can not be included in one or more trusted secure domains, and thus can be theoretically vulnerable, and can keep a dirty cache line marked as valid in the coprocessor cache.

[0021] As will be discussed below, the coprocessor can include an invalidation control circuit configured to cause one or more coprocessor cache lines to be invalidated in a more secure and efficient manner than other methods in response to an invalidation command transmitted by the processor. The invalidation control circuit can perform invalidation at cache line granularity based on the command without needing to execute any instructions on the coprocessor to perform the invalidation (although the coprocessor can execute other instructions for other operations during the time interval in which the invalidation occurs). The host processor can also trigger TLB invalidation (e.g., for unmapped pages corresponding to cache lines being invalidated) and issue a synchronization command (e.g., a barrier).

[0022] Figure 1 is a block diagram illustrating an example host processor configured to execute a remote invalidation instruction to cause invalidation in a coprocessor cache, in accordance with some embodiments. In the illustrated example, system 100 includes host processor circuitry 110 and coprocessor circuitry 120. Host processor 110 includes cache circuitry 130 and execution pipeline circuitry 140. Coprocessor 120 includes invalidation control circuitry 150, cache circuitry 160, and execution pipeline circuitry 170. For example, system 100 can be a system on a chip (SoC).

[0023] In some embodiments, host processor 110 can include circuitry and / or microcode configured to perform various operations based on, for example, instructions of an executing program. As used herein, the term “instruction” is intended to broadly encompass commands to a processor in a computer program, including but not limited to: instructions defined by an instruction set architecture (ISA), interpreted instructions, compiled instructions, microcode, machine code, etc. In various embodiments, execution pipeline 140 is configured to execute instructions, including the remote invalidation instruction discussed herein.

[0024] In some embodiments, the coprocessor 120 is configured to execute instructions using the execution pipeline 170. The coprocessor 120 can be a firmware processor, a graphics processor, an image processor, a display processor, etc. of a SoC. As discussed above, in various aspects, the coprocessor 120 can not be a peer of the main processor 110.

[0025] In some embodiments, the invalidation control circuit 150 is configured to receive an invalidation command 190 and, in response, invalidate one or more cache lines of the cache 160. As will be discussed in more detail with respect to FIGS. 4-6, the invalidation control circuit 150 can invalidate the cache 160 at a cache line granularity or a multi-cache line granularity depending on various fields of the command 190. As noted above, for example, use of the invalidation control circuit 150 can provide additional security relative to implementations in which invalidations are performed by software executing on the execution pipeline 170. Figure 5

[0026] In some embodiments, the cache circuit 160 is configured to store data for the coprocessor 120. The cache 160 can store various types of data from higher level caches or memory (e.g., an instruction cache that stores instructions, a data cache that stores data, etc.) to reduce data access latency. In some embodiments, the cache 160 is included in a multi-level cache hierarchy. Thus, the coprocessor 120 can include one or more low level caches relatively closer to the execution pipeline 170, one or more high level caches closer to system memory, or both.

[0027] As shown, the processor 110 is configured to remotely invalidate data in the cache 160. More specifically, in some embodiments, the processor 110 executes a remote invalidation instruction 180 using the execution pipeline 140 and, based on that execution, transmits a cache invalidation command 190 to the coprocessor 120. The coprocessor 120 receives the remote invalidation command 190 from the main processor 110 (e.g., via a fabric or bus) and routes the remote invalidation command to the invalidation control circuit. The invalidation control circuit 150 then invalidates one or more cache lines in the cache 160 based on the invalidation command 190 without needing to execute an instruction on the coprocessor 120.

[0028] As will be discussed with respect to Figures 4A-4B the command 190 can also include data specifying the granularity and location of the invalidation, such that the invalidation operation can advantageously be performed at a cache line granularity, e.g., to avoid flushing a larger portion of the cache 160. ​

[0029] Figure 2 is a block diagram illustrating an example host processor configured to maintain a page table for a coprocessor in accordance with some embodiments. As shown, host processor 110 is configured to populate page table 250 with mappings, some of which are utilized by coprocessor 120. As will be discussed below, subsequent changes in page table 250 can cause host processor 110 to perform a remote cache invalidation on cache 160 of coprocessor 120. Note that while page unmap is discussed herein as an example trigger for a remote cache invalidation, the disclosed invalidation techniques are contemplated for invalidations based on various suitable triggers.

[0030] In the illustrated example, host processor 110 is configured to create and populate page table 250 (here, a software data structure, as indicated by the dashed line) for coprocessor 120. As shown, MMU 220 is configured to generate translations, e.g., from OS virtual addresses to physical addresses of memory circuitry (e.g., memory 210), based on instructions executed by execution pipeline 140. MMU 220 is configured to store the generated translations in page table 250 for use by host processor 110, coprocessor 120, or both. In some embodiments, the maintenance of page table 250 is part of an operating system memory management process.

[0031] In some cases, host processor 110 can create page table 250 on behalf of coprocessor 120 to, e.g., enhance security. Coprocessor 120 can have only read access to page table 250 (and not write access). Example techniques by which a processor securely manages its own and other components’ (including coprocessors’) page tables can be found in U.S. Application No. 16 / 564,502, filed September 9, 2019, entitled “Page Protection Layer.”

[0032] In some cases, host processor 110 can determine to unmap a page of page table 250 (e.g., to replace a page that has not recently been used to manage overall memory occupancy). As discussed above, processor 110 can perform a remote validation of corresponding data in cache 160 in this context.

[0033] In the illustrated embodiment, coprocessor 120 is configured to access translations from page table 250. As shown, coprocessor 120 can use MMU 240 to walk page table 250 and store the resulting translations in TLB 230, e.g., to later access memory whose address translations are in page table 250. Note that because TLB 230 stores information related to page table 250, any modifications (e.g., unmap) at page table 250 can require corresponding modifications (e.g., invalidation) at TLB 230, as will be discussed with respect to FIG. 2B. Figure 6 More details are discussed.

[0034] Note that in some cases, cache 160 and cache 130 can be configured to cache data from the same memory space, which is mapped in shared page table 250. In the case of a shared page table page unmap, main processor 110 can cause data in its own cache 130 to be invalidated (e.g., using coherency control circuitry) in addition to performing a remote invalidation of data in cache 160 (e.g., via remote invalidation instruction 180).

[0035] Figure 3 is a block diagram illustrating an example system that supports both command-based remote cache invalidation and coherency-based cache invalidation in accordance with some embodiments. In the illustrated example, the computing system includes main processor 110, coprocessor 120, and peer processor 310. In one or more aspects, peer processor 310 is a peer of main processor 110. For example, processor 310 and processor 110 can be cores of the same multi-core processor or different processors in a processor cluster.

[0036] In the illustrated example, the system is configured to maintain coherency between cache 130 and cache 340. However, the system is not configured to maintain coherency between cache 130 and cache 160 (even though those caches can be used to cache data from the same memory space) in addition to the remote invalidation techniques discussed herein. As shown, main processor 110 can use different methods to cause cache invalidation: main processor 110 is configured to cause command-based remote invalidation in cache 160 of non-peer coprocessor 120, and to cause coherency-based invalidation in cache 340 of peer processor 310.

[0037] In some embodiments, the coherency control circuitry is configured to implement a coherency protocol (e.g., MESI, MOSEI, write invalidation, etc.) to maintain coherency between copies of data stored in multiple related different memory structures (including 130 and 340 in this example). The coherency control circuitry can perform various coherency-based operations, such as cache invalidation, cache flushing, barrier enforcement, etc., to implement those coherency protocols. In the illustrated example, coherency control circuitry 320 and coherency control circuitry 330 are configured to maintain coherency between cache 130 and cache 160.

[0038] As an example of coherency-based invalidation, coherency control circuitry 330 can invalidate a line of cache 130 based on a write to a corresponding entry in cache 340 (meaning that other caches need to invalidate their old copies). For example, circuitry 320 and circuitry 330 can implement snoop messages or directories to track coherency. As another example, when a page is de-mapped, processor 110 can use coherency control circuitry 320 and coherency control circuitry 330 to invalidate any corresponding lines in cache 130 and cache 340. Note that the bidirectional arrow coupling coherency control circuitry 320 and coherency control circuitry 330 indicates that coherency can be bidirectional.

[0039] Note that there can be various reasons why coherency control circuitry can not be implemented for cache 160 of coprocessor 120. For example, coherency control circuitry for non-peer coprocessors can have higher area and complexity costs for coprocessor 120. As another example, when main processor 110 and coprocessor 120 are not peers, coherency control circuitry can not be desired or needed at all.

[0040] Coprocessor 120 uses invalidation control circuitry 150 to perform command-based invalidation, rather than performing coherency-based invalidation as shown at peer processor 310, e.g., as discussed above with reference to Figure 1

[0041] Note that coprocessor 120 can have internal coherency control circuitry configured to maintain coherency between internal caches of coprocessor 120, but not maintain coherency with caches present on non-peer processors, as described in more detail with reference to Figure 5 Conversely, in some embodiments, processor 110 can transmit remote invalidation commands to peer processor 310 despite the presence of coherency control circuitry 320 / 330.

[0042] ​In some implementations, processor 110 may transmit remote fail commands to other processors or coprocessors that are not peers in various respects. For example, the other processor may be in a different shareability domain. For instance, consider that main processor 110 is in a first internal shareability domain, and coprocessor 120 is in a second separate internal shareability domain. Processor 110 may transmit the remote fail command to cache 160 because cache 160 is not included in the first shareability domain (of processor 110). Similarly, processor 110 may transmit remote fail commands to processors outside certain protection domains.

[0043] The following figures illustrate example fields included in example remote failure instructions and commands according to some implementation schemes. The various fields described below can be used in conjunction with the techniques discussed above.

[0044] Figure 4A This is a diagram illustrating example fields of a remote fail instruction according to some embodiments. In the illustrated embodiments, the address field indicates the location in a cache (e.g., cache 160 of coprocessor 120) to be failed (e.g., by failover control circuitry 150). In some cases, cache 160 is physically labeled, and the address includes all or part of the physical address corresponding to the cache(s)(s) to be failed. In these embodiments, processor 110 may advantageously be able to generate physical addresses for failover because the processor manages, for example, page table 250.

[0045] In other embodiments, cache 160 is virtually tagged, and the address is all or part of the virtual address. In other embodiments, cache 160 is physically tagged, and the address is all or part of the virtual address (however, coprocessor 120 may use MMU 240 to determine which cache lines need to be invalidated). In some embodiments, the address field may include multiple addresses, which may be non-contiguous for potential invalidations of different cache lines.

[0046] In the illustrated implementation, the granularity field describes the granularity of the invalidation. According to some implementations, if the granularity indicates a cache line, the invalidation can be for the cache line corresponding to the address specified in the address field. Otherwise, if the granularity indicates multiple lines, the invalidation circuitry is configured to invalidate up to N corresponding lines, where N is an integer greater than 1. In some implementations, the granularity is a numerical value specifying the number of cache lines potentially to be invalidated. In other implementations, the size is fixed (e.g., corresponding to the number of cache lines in a page).

[0047] Figure 4BThis is a diagram illustrating example fields of a remote invalidation command according to some implementation schemes. In the illustrated implementation, the processor ID field indicates (e.g., for routing purposes) which particular coprocessor in a set of coprocessors will receive the invalidation command. In the illustrated implementation, the cache ID field identifies the specific cache to be invalidated (e.g., specifying a multi-level cache hierarchy at the coprocessor).

[0048] As noted, a remote failure command can be generated in response to a remote failure instruction, and the fields of the remote failure command can therefore be obtained from them. Figure 4A The corresponding fields at the remote failure instruction are inherited. For example, in some implementations, the granularity fields are functionally identical to the granularity fields of the remote failure instruction. However, in some implementations, these fields may differ from their similar fields at instruction 180.

[0049] Figure 5 This is a block diagram illustrating a more detailed example of a main processor and coprocessor according to some implementation schemes. The diagram illustrates in more detail... Figure 1 The main processor 110, coprocessor 120, and remote failure example are depicted in the image.

[0050] As shown in the figure, the main processor 110 also includes an instruction cache circuit 520, which is coupled to the coprocessor 120 via a structure 510. Also as shown, the coprocessor 120 includes a bus control circuit 540, a coherence control circuit 575, and a load / store circuit 590. Furthermore, the failure control circuit 150 includes an instruction handler 552 and an iterator 554.

[0051] As also shown in the figure, coprocessor 120 has an example multi-level cache hierarchy including example cache control circuitry 570 configured to manage low-level cache 560 and high-level cache 580. As shown, the low-level cache 560 is closer to the execution pipeline 170 than the high-level cache circuitry 580. In some examples of multi-level cache hierarchies, coprocessor 120 includes multiple execution pipelines 170, multiple low-level caches 560 each coupled to the execution pipelines 170, and a single high-level cache 580 shared (and consistent with) among the multiple low-level caches 560. In some embodiments, the cache hierarchy of coprocessor 120 is a single-level cache hierarchy.

[0052] As shown in the figure, the main processor 110 stores a remote fail instruction 180 in the instruction cache 520 in response to a demapping. For example, software (e.g., an operating system) executing on the processor 110 may generate the fail instruction 180 by demapping a page at page table 250 (via MMU 220), which is then stored in the instruction cache 520. Additionally, in some embodiments, the processor 110 may also cause a fail on the TLB 230 of the coprocessor 120 by demapping, such as by demapping a page at page table 250. Figure 6 To be discussed in more detail.

[0053] Execution pipeline 140 fetches and executes the remote invalidation instruction 180 stored in instruction cache 520. For example... Figure 4A As shown, instruction 180 may have fields (e.g., address and granularity) specifying one or more lines of the coprocessor cache to be invalidated. As noted, pipeline 140 may execute additional instructions related to unmapping page table 250 and invalidating one or more entries in TLB 230.

[0054] As shown in the figure, in response to executing the remote fail instruction 180, the main processor 110 transmits the remote fail command 190 as a packet 535 via structure 510. Similar to instruction 180, command 190 / packet 535 may include further information specifying the fail (e.g., address, granularity, coprocessor ID, cache ID), such as... Figure 4B As described in [the document]. In some implementations, structure 510 is configured to use the Advanced Extensible Interface (AXI) protocol to handle communication between processor 110 and coprocessor 120.

[0055] Coprocessor 120 receives packet 535 at bus control circuitry 540, which is configured to forward invalidation command 190 to invalidation control circuitry 150. Invalidation control circuitry 150 then triggers an invalidation operation based on command 190 performed by cache control circuitry 570 (note that in some embodiments, invalidation control circuitry 150 is included within cache control circuitry 570). For example, command handler 552 and iterator 554 (in the case of multiple line invalidations) can use fields of command 190 to appropriately trigger invalidation.

[0056] In various implementations, command handler circuitry 552 is configured to determine which cache lines to invalidate based on command 190. In some implementations, command handler 552 may use an address field as the base address for invalidation and a granularity field to determine the size of the cache region to be invalidated. In some implementations, the command handler receives a virtual address from command 190 and uses TLB 230 to translate the address. However, in other implementations, command handler 552 receives the physical address from command 190 and bypasses the translation (thus avoiding TLB lookup latency, MMU latency, or both). Command handler 552 may also (e.g., based on the granularity field) determine that the invalidation is for multiple cache lines and forward the invalidation to iterator 554.

[0057] In various implementations, iterator 554 is configured to generate multiple cache line misses based on remote miss command 190. If miss command 190 (e.g., via a granularity field) indicates the miss of multiple lines, iterator 554 causes control circuitry 150 to issue multiple cache line miss commands to cache control circuitry 570 based on that indication. Iterator 554 may issue a predefined number of misses based on the granularity of command 190 (e.g., a predefined cache block size) or the number of misses specified by a numeric field of command 190. However, if command 190 specifies a single line to be missed, miss control circuitry 150 may bypass iterator 554 and issue a single cache miss command to cache control circuitry 570 at the specified address. Using iterator 554 may be advantageous, for example, to reduce bandwidth on structure 510, compared to transmitting an equivalent number of remote miss commands via structure 510.

[0058] In various implementations, cache control circuitry 570 is configured to perform cache misses at one or more cache levels of coprocessor 120 based on commands issued from miss control circuitry 150. For example, cache control circuitry 570 may check the tags of cache lines in higher-level cache 580 and miss any lines whose tags match the address of a remote miss command.

[0059] Generally, a remote miss in one cache can cause misses in other caches. For example, consistency control circuitry can maintain consistency across multiple low-level caches 560 and can perform misses based on higher-level caches 580 that serve as consistency points. For example, consistency control circuitry can use a directory-based or snoop-based architecture.

[0060] In various embodiments, the load / store circuit (LSU) 590 is configured to manage memory operations at various memory circuits. For example, circuit 590 may receive load requests and access one or more of cache 560, cache 580, and external memory circuits (e.g., memory 210) depending on whether the requested data is cached. In some embodiments, failure control circuit 150 is configured to utilize load / store circuit 590 to perform the disclosed failures. For example, failure control circuit 150 may issue a failure command to a memory queue of load / store circuit 590. Note that load / store circuit 590 may be configured to enforce ordering between memory operations (e.g., using CAM operations between load queues and memory queues), but may not enforce ordering for failure operations from failure control circuit 150. However, load / store circuit 590 may adjust counters associated with barrier operations, for example, based on failure operations from failure control circuit 150. Thus, newer barrier operations may wait until older failure operations from failure control circuit 150 complete. It should be noted that the use of the failure control circuit 150 for the LSU 590 does not execute instructions on the pipeline 170. Instead, in the illustrated example, the circuit 150 directly issues a failure command to the LSU 590.

[0061] In some cases, the load / store circuit 590 is configured to reduce or avoid conflicts associated with cache lines that are to be invalidated. Specifically, the load / store circuit may enforce a specific ordering of memory operations specified by a given synchronization barrier command, such as regarding... Figure 6 Described in more detail. In order to enforce the synchronization barrier, the load / store circuit 590 can be configured to perform various operations, such as (e.g., using a hardware counter) blocking various pending operations, rearranging the order of operations to enforce a specific sequence (e.g., using a comparator circuit), etc.

[0062] Figure 6 This is a communication diagram illustrating example communication between the main processor, coprocessor, and coprocessor cache during a remote cache miss, according to some implementation schemes. In the illustrated implementation scheme, the main processor 110 initiates a miss operation on data in the coprocessor cache 160 of the coprocessor 120 based on the execution of a remote cache miss instruction 180.

[0063] As will be discussed below, coprocessor 120 can use synchronization barrier commands to enforce the ordering of operations at load / store circuitry 590 and avoid potential deadlock scenarios. In some implementations, main processor 110 executes memory-related barrier instructions (e.g., ARM DSB or DMB instructions) and transmits the corresponding synchronization barrier commands to coprocessor 120. Coprocessor 120 then routes these synchronization barrier commands to load / store circuitry 590, which enforces the indicated synchronization. Furthermore, synchronization barriers can provide the correctness of data in various caches, including caches that may not have been directly invalidated by remote cache invalidation commands.

[0064] As shown in the figure, at 610, an example remote cache miss is triggered by processor 110 unmapping a page for coprocessor 120. Processor 110 then sends a remote TLB miss command 615 to coprocessor 120. In some cases, command 615 is used for any matching TLB entries that include translations in the unmapped page. Similar to cache miss command 190, processor 110 can perform a remote TLB miss in response to an instruction to execute a specified TLB miss. In some implementations, processor 110 sends command 615 to coprocessor 120 in a structured message or packet. Once the TLB miss is complete at 620, coprocessor 120 can return an acknowledgment of completion to master processor 110.

[0065] The main processor 110 transmits a synchronization barrier command 620, which ensures that the TLB invalidation is completed before the barrier command 620 completes (and before the execution of any operations after the barrier command 620). Once the synchronization barrier is complete (indicating that the TLB invalidation is also complete), the coprocessor returns the corresponding synchronization barrier response 625 to the processor 110.

[0066] Then, the main processor 110 sends a remote cache invalidation command 630 (e.g., command 190) to the coprocessor 120, which then continues to issue invalidation commands to the cache 160 (e.g., via invalidation control circuitry 150). In some embodiments, the processor 110 sends a packet containing the invalidation command to the coprocessor 120 via a structure.

[0067] In some cases, a cache miss command can specify multiple cache lines for the miss operation (e.g., via an opcode or granularity field). Therefore, at miss 635, coprocessor 120 can issue multiple remote misses (as indicated by the dashed lines) to cache 160 based on the command indication that the miss is for multiple cache lines (e.g., using iterator 554). Further note that coprocessor 120 can (e.g., via a coherence control mechanism) trigger miss operations for multiple cache levels. Once coprocessor cache 160 misses any matching data cache line, coprocessor cache 160 sends a remote cache miss response 640 to coprocessor 120.

[0068] As shown, processor 110 then transmits a second synchronization barrier command 645. Coprocessor 120 returns a synchronization barrier response 650, which ensures that the failure (and any related calculations) is completed before barrier command 645 (and any subsequent commands issued after 645) is completed.

[0069] When the illustrated barrier operation is executed, the system can avoid deadlock scenarios. In some implementations, when a remote cache miss command occurs, the synchronization barrier 620 ensures that no incomplete load / store / prefetch is pending for the address being missped. However, eviction traffic to those addresses may exist between cache levels or from the cache level to the bus interface. To avoid deadlock, the system can ensure that there is no dependency between bus traffic (including eviction traffic on the bus) and the remote cache miss response 640 (although some pauses may be acceptable).

[0070] For example, if there is an incomplete evict write to memory when a cache miss 635 is received for a given address, the system can immediately respond with the corresponding remote cache miss response 640 (instead of waiting for the evict write and creating a dependency). This avoids dependency deadlock.

[0071] Synchronization barrier 645 ensures the correct ordering of such eviction writes. For example, upon receiving synchronization barrier command 645, coprocessor 120 can wait for the eviction write to complete before responding with synchronization barrier response 650. It should be noted that in some implementations, the system is designed to tolerate bus transfers to barriers 620 and 645. For example, the system can allow non-barrier bypasses and can provide sufficient buffering for the maximum number of incomplete barriers the system can generate.

[0072] Therefore, in various implementations, the system can respond to cache invalidation commands before an incomplete transfer to the same address is completed to avoid deadlock, but barrier commands (such as barrier command 645) can ensure that the transfer is completed.

[0073] Example Method

[0074] Figure 7 This is a flowchart illustrating an example method for performing a remote cache invalidation according to some implementation schemes. Figure 7 The method 700 shown can be used in conjunction with any of the computer circuits, systems, devices, elements, or components disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0075] At 710, in the illustrated implementation, the processor circuitry (e.g., main processor 110) transmits a cache miss command (e.g., command 190) to the coprocessor circuitry (e.g., coprocessor 120) based on the execution of a remote miss instruction (e.g., instruction 180).

[0076] At 720, in the illustrated embodiment, the coprocessor circuitry responds to a cache miss command to (e.g., using miss control circuitry 150) miss one or more cache lines of the coprocessor cache circuitry (e.g., cache 160), wherein the miss is performed without requiring any instructions to be executed on the coprocessor circuitry (e.g., in execution pipeline 170).

[0077] In some implementations, a cache miss command is included in a packet transmitted over a communication structure, wherein the packet includes at least information specifying one or more addresses to be missted and an identifier of the coprocessor circuit. In some implementations, missting one or more cache lines in the coprocessor cache circuit includes missting multiple cache lines in the coprocessor cache circuit based on a single cache miss command instructing multiple cache lines of the coprocessor cache circuit to be missted. In some implementations, the coprocessor circuit supports instructions with virtual addresses and is configured to translate virtual addresses to physical addresses, the coprocessor cache circuit uses physical addresses for labeling, and the cache miss command indicates the physical address to be missted.

[0078] In some implementations, the main processor circuitry is configured to map memory pages to the coprocessor circuitry. The main processor circuitry can unmap the pages mapped to the coprocessor circuitry, wherein transfers are performed based on the unmapping. In some implementations, coherence control circuitry on the main processor is configured to maintain coherence between another cache circuitry on another processor and the main processor cache circuitry, including invalidating one or more cache lines of the other cache circuitry based on the unmapping to maintain consistency. The coherence control circuitry may not be configured to maintain coherence between the main processor cache circuitry and the coprocessor cache circuitry based on the unmapping.

[0079] In some implementations, the coprocessor circuitry further includes a translation back buffer circuitry configured to store entries for translations from a first address space to a second address space. The main processor circuitry may transmit a translation back buffer invalidation command to the coprocessor circuitry based on unmapping, the translation back buffer invalidation command invalidating one or more corresponding entries in the translation back buffer circuitry. In some implementations, the main processor further transmits a first barrier command between the translation back buffer invalidation command and a cache invalidation command, and a second barrier command following the cache invalidation command.

[0080] In some implementations, the main processor circuitry includes one or more caches that are included in one or more shared domains of a plurality of shared domains, the one or more caches including the main processor cache circuitry, and the coprocessor cache circuitry is not included in any shared domain of any cache that includes the main processor circuitry.

[0081] In some implementations, the coprocessor circuitry also includes coprocessor cache coherency circuitry and low-level cache circuitry, wherein, in the cache hierarchy, the low-level cache circuitry is located closer to the coprocessor circuitry's execution pipeline than the coprocessor cache circuitry. The coprocessor cache coherency circuitry can invalidate one or more corresponding cache lines in the low-level cache circuitry in response to a failure at the coprocessor cache circuitry.

[0082] The concept of a processor "pipeline" is well-known and refers to the division of the "work" a processor does on instructions into multiple stages. In some implementations, instruction decoding, dispatching, execution (i.e., performing), and rollback can be examples of different pipeline stages. Many different pipeline architectures may have different element / part orders. Various pipeline stages perform these steps on instructions during one or more processor clock cycles, then pass the instruction or the operation associated with the instruction to other stages for further processing.

[0083] Example device

[0084] Now for reference Figure 8 A block diagram illustrating an example embodiment of device 800 is shown. In some embodiments, device 800 may implement the functionality of system 100 (including processor 110 and coprocessor 120). In some embodiments, the components of device 800 may be included within a system-on-a-chip. In some embodiments, device 800 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 800 may be an important design consideration. In the illustrated embodiment, device 800 includes structure 810, computing complex 820, input / output (I / O) bridge 850, cache / memory controller 845, graphics unit 875, and display unit 865. In some embodiments, as supplements or alternatives to the illustrated components, device 800 may also include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0085] Structure 810 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 800. In some embodiments, portions of structure 810 may be configured to implement various different communication protocols. In other embodiments, structure 810 may implement a single communication protocol, and components coupled to structure 810 may internally switch from a single communication protocol to other communication protocols.

[0086] In the illustrated implementation, computing complex 820 includes a bus interface unit (BIU) 825, a cache 830, and cores 835 and 840. In various implementations, computing complex 820 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 820 may include one, two, four, or any other suitable number of processor cores. In one implementation, cache 830 is a set-associative L2 cache. In some implementations, cores 835 and 840 may include internal instruction and data caches. In some implementations, a coherence unit (not shown) in architecture 810, cache 830, or elsewhere in device 800 may be configured to maintain coherence between the various caches of device 800. BIU 825 may be configured to manage communication between computing complex 820 and other elements of device 800. Processor cores (such as cores 835 and 840) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions. These instructions can be stored in a computer-readable medium, such as memory coupled to the memory controller 845 discussed below.

[0087] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling can include intermediate elements. For example, in Figure 8 In this context, the graphics unit 875 can be described as being "coupled" to memory via structure 810 and cache / memory controller 845. In contrast, in... Figure 8 In the illustrated implementation, the graphics unit 875 is "directly coupled" to the structure 810 because there are no intermediate elements.

[0088] The cache / memory controller 845 can be configured to manage data transfers between the architecture 810 and one or more caches and memories. For example, the cache / memory controller 845 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 845 may be directly coupled to memory. In some embodiments, the cache / memory controller 845 may include one or more internal caches. The memory coupled to the controller 845 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR4, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled onto a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, these devices can be mounted with integrated circuits in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration. The memory coupled to the controller 845 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nanometer RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), raceway memory, memristor memory, etc. As noted above, this memory can store program instructions executable by the computing complex 820 to enable the computing device to perform the functionality described herein.

[0089] The graphics unit 875 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 875 may receive graphics-oriented instructions, such as OpenGL. ® Metal ® Or DIRECT3D ®Instructions. The graphics unit 875 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 875 is typically configured to process large blocks of data in parallel and can construct an image in a frame buffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 875 may include a transformation engine, a lighting engine, a triangle engine, and a rendering engine in one or more graphics processing pipelines. The graphics unit 875 can output pixel information for displaying the image. In various embodiments, the graphics unit 875 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0090] Display unit 865 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 865 can be configured as a display pipeline. Additionally, display unit 865 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 865 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0091] I / O bridge 850 may include various components configured to implement functionalities such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on connectivity. I / O bridge 850 may also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 800 via I / O bridge 850.

[0092] In some embodiments, device 800 includes network interface circuitry (not explicitly shown) that can be connected to structure 810 or I / O bridge 850. This network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via Wi-Fi), or a wireless LAN. ™ The network interface circuitry can communicate via one or more cellular networks using one or more radio access technologies, or wide area networks (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to use device-to-device communication (e.g., Bluetooth). ® or Wi-Fi ™Communication can be achieved through direct connection, etc. In various implementations, this network interface circuitry can provide device 800 with connectivity to various types of other devices and networks.

[0093] Example Application

[0094] Now go to Figure 9 This can include various types of systems, including any of the circuits, devices, or systems discussed above. The system or device 900, which may utilize one or more of the techniques described herein in combination with or otherwise, can be used in a wide range of fields. For example, the system or device 900 can be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0095] Similarly, the disclosed components can be used in wearable devices 960, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0096] System or device 900 can also be used in a variety of other contexts. For example, system or device 900 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 970. Furthermore, system or device 900 can be implemented in a wide range of dedicated everyday devices, including common household devices 980 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 900 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 990.

[0097] Figure 9 The applications illustrated herein are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0098] Example computer-readable media

[0099] Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that specify storage media for circuits in formats that cover not only means including the disclosed circuits, but also analog models for programming computing systems to generate hardware circuits, manufacturing systems configured to generate hardware (e.g., integrated circuits) including the disclosed circuits. Claims for such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves perform complete operations (such as design simulation, design synthesis, circuit fabrication, etc.).

[0100] Figure 10 This is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a computing system 1040 is configured to process the design information. This may include executing instructions included in the design information, interpreting instructions included in the design information, compiling, transforming, or otherwise updating the design information. Thus, in some embodiments, the design information (e.g., by programming the computing system 1040) controls the computing system 1040 to perform the various operations discussed below.

[0101] In the illustrated example, computing system 1040 processes design information to generate both a computer simulation model 1060 of the hardware circuit and lower-level design information 1050. In other embodiments, computing system 1040 may generate only one of these outputs, may generate other outputs based on the design information, or both. Regarding the computational simulation, computing system 1040 may execute instructions in a hardware description language, which includes register-transfer-level (RTL) code, behavioral code, structural code, or some combination thereof. The simulation model may perform the functionality specified by the design information, facilitate verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, etc.

[0102] In the illustrated example, computing system 1040 also processes the design information to generate lower-level design information 1050 (e.g., gate-level design information, netlists, etc.). As shown, this may include synthesis operations such as constructing multi-level networks, optimizing the network using technology-independent techniques, technology-dependent techniques, or both, and outputting a gate network (with potential constraints based on a library of available gate pairs, size adjustments, delays, power, etc.). Based on the lower-level design information 1050 (and potentially other inputs), semiconductor manufacturing system 1020 is configured to manufacture integrated circuit 1030 (which may correspond to the functionality of simulation model 1060). Note that computing system 1040 may generate different simulation models based on design information at various descriptive levels (including information 1050, 1015, etc.). Data representing design information 1050 and model 1060 may be stored on medium 1010 or one or more other media.

[0103] In some implementations, lower-level design information 1050 controls (e.g., programs) the semiconductor manufacturing system 1020 to manufacture integrated circuit 1030. Therefore, when processed by the manufacturing system, the design information can program the manufacturing system to manufacture circuits including the various circuits disclosed herein.

[0104] The non-transitory computer-readable storage medium 1010 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be: mounting media, such as CD-ROM, floppy disk, or magnetic tape devices; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media, such as hard disk drives or optical storage devices; registers or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. Therefore, the non-transitory computer-readable storage medium 1010 may include two or more memory media; such media may reside in different locations—for example, in different computer systems connected via a network.

[0105] Design information 1015 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The formats of various design information can be recognized by one or more applications executed by computing system 1040, semiconductor manufacturing system 1020, or both. In some embodiments, design information may also include one or more cell libraries specifying the composition, layout, or both of integrated circuit 1030. In some embodiments, design information is specified wholly or partially in the form of a netlist specifying cell library elements and their connectivity. Individually, the design information discussed herein may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information may specify circuit elements to be manufactured but not their physical layout. In this case, design information may need to be combined with layout information to actually manufacture the specified circuit.

[0106] In various implementations, the integrated circuit 1030 may include one or more custom macrocells, such as memory and analog or mixed-signal circuitry. In this case, design information may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. Mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0107] The semiconductor manufacturing system 1020 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1020 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0108] In various embodiments, integrated circuit 1030 and model 1060 are configured to operate according to a circuit design specified by design information 1015, which may include performing any of the functionalities described herein. For example, integrated circuit 1030 may include Figure 1 , Figure 2 and Figure 5 Any of the various components shown herein. Additionally, integrated circuit 1030 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0109] ***

[0110] As used herein, a phrase in the form of “design information specifying a circuit configured to…” does not imply that the circuit in question must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components. Similarly, stating that “instructions of a hardware description programming language” are “executable” to program a computing system to generate a computer simulation model does not mean that the instructions must be executed to satisfy the element, but rather specifies the characteristics of those instructions. In this case, additional features associated with the model (or the circuit represented by the model) may similarly relate to the characteristics of those instructions. Therefore, an entity selling a computer-readable medium having instructions that satisfy the stated characteristics may provide an infringing product even if another entity actually executes those instructions on the medium.

[0111] It is important to note that a given design, at least within a digital logic context, can be implemented using multiple different gate arrangements, circuit techniques, etc. As an example, different designs may choose or connect gates based on design trade-offs (e.g., focusing on power consumption, performance, circuit area, etc.). Furthermore, different manufacturers may have proprietary libraries, gate designs, physical gate implementations, etc. Different entities may also use different tools to process design information at various layers (e.g., from behavioral specifications to the physical layout of gates).

[0112] However, once a digital logic design is specified, those skilled in the art do not need to perform extensive experiments or studies to determine these specific implementations. Instead, they understand the process for reliably and predictably producing one or more circuit implementations that provide the functionality described by the design information. Different circuit implementations may affect the performance, area, power consumption, etc., of a given design (potentially trade-offs between different design goals), but the logic function remains unchanged between different circuit implementations of the same circuit design.

[0113] In some implementations, instructions included in the design information instructions provide RTL information (or other higher-level design information) and can be executed by a computing system to synthesize a gate-level netlist representing the hardware circuitry based on the RTL information as input. Similarly, these instructions provide behavioral information and can be executed by the computing system to synthesize netlists or other lower-level design information. This lower-level design information can be used to program the manufacturing system 1020 to manufacture the integrated circuit 1030.

[0114] ***

[0115] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” and “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0116] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0117] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0118] For example, the features in the present application may be combined in any suitable manner. Thus, during the filing of the present application (or an application claiming priority therefrom), new claims may be made for any such combinations of features. Specifically, referring to the appended claims, the features of the dependent claims may, where appropriate, be combined with the features of other dependent claims, including claims that depend from other independent claims. Similarly, the features from the respective independent claims may be combined, where appropriate.

[0119] Thus, while the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in the present application or in another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0120] Where appropriate, claims drafted in one format or statutory type (e.g., apparatus) are also contemplated as being intended to support corresponding claims in another format or statutory type (e.g., method).

[0121] ***

[0122] Since the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0123] Unless the context clearly dictates otherwise, a reference to an item in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items refers to a collection of two or more items.

[0124] The word "may" is used herein in an enabling sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0125] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0126] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both”, and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0127] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0128] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0129] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0130] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0131] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions capable of being executed to perform the task. This phrase is not used herein to refer to intangible things.

[0132] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0133] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0134] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0135] ***

[0136] Different “circuits” may be described in this disclosure. These circuits, or “circuits,” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits.

[0137] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0138] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of such circuits / cells / components relative to each other and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, this HDL description is a way of transforming the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0139] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0140] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: The coprocessor circuit includes: Coprocessor cache circuitry; and Cache invalidation control circuit; The main processor circuit includes: Execution pipeline; and Main processor cache circuit; in: The main processor circuit is configured to send cache invalidation commands to the coprocessor circuit based on the execution of remote invalidation instructions in the execution pipeline; and The cache invalidation control circuit is configured to invalidate one or more cache lines in the coprocessor cache circuit in response to the cache invalidation command, wherein the cache invalidation control circuit is configured to perform the invalidation without executing any instructions on the coprocessor circuit.

2. The apparatus according to claim 1, wherein: The main processor circuit is configured as follows: Map memory pages for the aforementioned coprocessor circuit; Unmapping is performed on the pages mapped to the coprocessor circuitry, and the transfer is performed based on the unmapping.

3. The apparatus according to claim 2, further comprising: Consistency control circuit; and Another processor circuit, which includes another cache circuit; in: The consistency control circuit is configured to maintain consistency between the other cache circuit and the main processor cache circuit, including invalidating one or more cache lines of the other cache circuit based on the demapping to maintain consistency; and The consistency control circuit is not configured to maintain consistency between the main processor cache circuit and the coprocessor cache circuit for the purpose of demapping.

4. The apparatus according to claim 2, wherein: The coprocessor circuitry further includes a translation backup buffer circuit, which is configured to store entries for translations from a first address space to a second address space; and The main processor circuit is also configured to transmit a translation backstop buffer invalidation command to the coprocessor circuit based on the demapping, the translation backstop buffer invalidation command invalidating one or more corresponding entries in the translation backstop buffer circuit.

5. The apparatus according to claim 4, wherein: The main processor circuit is also configured to transmit: The first barrier command between the transition backup buffer invalidation command and the cache invalidation command; and The second barrier command following the cache invalidation command.

6. The apparatus according to claim 5, wherein: The coprocessor circuitry is also configured to respond to the cache miss command before eviction of the address matching the cache miss command is completed; and The second barrier command ensures the completion of the expulsion.

7. The apparatus according to claim 1, wherein: The coprocessor circuitry supports instructions with virtual addresses and is configured to translate virtual addresses into physical addresses. The coprocessor cache circuitry is labeled using physical addresses; and The cache invalidation command indicates the physical address to be invalidated.

8. The apparatus according to claim 1, wherein: Invalidating one or more cache lines in the coprocessor cache circuitry includes invalidating multiple cache lines in the coprocessor cache circuitry based on a single cache invalidation command that instructs the invalidation of multiple cache lines in the coprocessor cache circuitry.

9. The apparatus according to claim 1, wherein: The device supports multiple shareability domains; The main processor circuitry includes one or more caches, which are included in one or more of the plurality of shareable domains, and the one or more caches include the main processor cache circuitry; and The coprocessor cache circuitry is not included in any shareability domain of any cache that includes the main processor circuitry.

10. The apparatus according to claim 1, wherein: The cache invalidation command is included in a packet transmitted over the communication structure, wherein the packet includes at least the following: Specify information about one or more addresses to be invalidated; and The identifier of the coprocessor circuit.

11. The apparatus according to claim 1, wherein: The coprocessor circuit also includes: A low-level cache circuit, wherein in a cache hierarchy, the low-level cache circuit is located closer to the execution pipeline of the coprocessor circuit than the coprocessor cache circuit; and Coprocessor cache coherency circuitry; and The coprocessor cache coherence circuit is configured to invalidate one or more corresponding cache lines in the lower-level cache circuit in response to a failure at the coprocessor cache circuit.

12. The apparatus of claim 1, wherein the apparatus is a computing device, the computing device further comprising: monitor; and Network interface circuit.

13. A method, the method comprising: The processor circuitry transmits cache invalidation commands to the coprocessor circuitry based on the execution of remote invalidation instructions; as well as The coprocessor circuit invalidates one or more cache lines of the coprocessor cache circuit in response to the cache invalidation command, wherein the invalidation is performed without executing any instructions on the coprocessor circuit.

14. The method according to claim 13, further comprising: The processor circuit maps memory pages to the coprocessor circuit. as well as Unmapping is performed on the pages mapped to the coprocessor circuitry, and the transfer is performed based on the unmapping.

15. The method according to claim 14, further comprising: The coprocessor circuit implements a translation backup buffer circuit, which is configured to store translations from a first address space to a second address space. as well as The coprocessor circuit transmits a translation backstop invalidation command based on the unmapping, the translation backstop invalidation command invalidating one or more corresponding entries in the translation backstop circuit.

16. The method according to claim 15, further comprising: Transmitted from the main processor circuit to the coprocessor circuit: The first barrier command between the conversion backup buffer invalidation command and the cache invalidation command; and The second barrier command following the cache invalidation command.

17. A non-transitory computer-readable medium storing instructions of a hardware description programming language, which, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents hardware circuitry comprising: The coprocessor circuit includes: Coprocessor cache circuitry; and Cache invalidation control circuit; The main processor circuit includes: Execution pipeline; and Main processor cache circuit; in: The main processor circuit is configured to send cache invalidation commands to the coprocessor circuit based on the execution of remote invalidation instructions in the execution pipeline; and The cache invalidation control circuit is configured to invalidate one or more cache lines in the coprocessor cache circuit in response to the cache invalidation command, wherein the cache invalidation control circuit is configured to perform the invalidation without executing any instructions on the coprocessor circuit.

18. The non-transitory computer-readable medium of claim 17, wherein the hardware circuitry further comprises: Consistency control circuit; and Another processor circuit, which includes another cache circuit; in: The consistency control circuit is configured to maintain consistency between the other cache circuit and the main processor cache circuit, including invalidating one or more cache lines of the other cache circuit based on the demapping to maintain consistency; and The consistency control circuit is not configured to maintain consistency between the main processor cache circuit and the coprocessor cache circuit for the purpose of demapping.

19. The non-transitory computer-readable medium according to claim 17, wherein: The hardware circuitry supports multiple shareable domains; The main processor circuitry includes one or more caches, which are included in one or more of the plurality of shareable domains, and the one or more caches include the main processor cache circuitry; and The coprocessor cache circuitry is not included in any shareability domain of any cache that includes the main processor circuitry.

20. The non-transitory computer-readable medium according to claim 17, wherein: The coprocessor circuit also includes: A low-level cache circuit, wherein in a cache hierarchy, the low-level cache circuit is located closer to the execution pipeline of the coprocessor circuit than the coprocessor cache circuit; and Coprocessor cache coherency circuitry; and The coprocessor cache coherence circuit is configured to invalidate one or more corresponding cache lines in the lower-level cache circuit in response to a failure at the coprocessor cache circuit.

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