Component carrier and method for producing same

Abstract

The invention relates to a component carrier comprising a stack (1) comprising at least one electrically conductive layer structure (2) and at least one electrically insulating layer structure (3), said at least one electrically conductive layer structure (2) comprising two portions (P1, P2) arranged adjacent to each other on a common layer (5), each portion (P1, P2) has a base (6) in contact with the common layer (5), an upper end (7) opposite the base (6), and at least one side wall (8) connecting the base (6) and the upper end (7), where the base (6) of each portion (P1, P2) is connected to the at least one side wall (8) forming a base edge (9), the side wall (8) facing an adjacent portion (P1, P2) and having an inclination (alpha) of less than 90 DEG with respect to the base (6), and the base edge (9) is connected to the upper end (7). The distance between the base edges (9) of two adjacent portions (P1, P2) is less than 10 [mu] m. The invention also relates to a method for producing such a component carrier.

Description

Technical Field

[0001] The present invention relates to a component carrier of the preamble of claim 1, and a method for producing such a carrier of the preamble of claim 23. Background Technology

[0002] Known component carriers are typically stacked components comprising at least one conductive layer structure and at least one electrically insulating layer structure. The at least one conductive layer structure comprises two adjacent portions arranged on a common layer, each portion having a base in contact with the common layer, an upper end opposite the base, and at least one sidewall connecting the base and the upper end.

[0003] Known methods for producing such stacks include fabricating fine-line structures (similar to traces) on the stack via photolithography (e.g., using LDI). This necessitates resist lamination, development, and stripping steps. For fine-line structures <5 μm, a Ti / Cu seed layer needs to be sputtered to ensure good adhesion of the plated copper to the dielectric. After photolithography and electroplating, the seed layer needs to be etched away. Special chemicals are required to etch away the Ti.

[0004] CN108282964A proposes a fine-line structure (1-110 μm spacing, 0.2-500 μm depth) in a conductive layer, with an underlying adhesive line (acrylic or epoxy film). After laser ablation, a protective sheet is laminated on top of the substrate.

[0005] CN113068310A discloses laser ablation of a conductive paste to form micron / nanometer pitches for circuit boards. Metal can be selectively electroplated on top of the conductive layer before ablation.

[0006] Following the teachings of TW201026168A, a conductive layer is deposited on a dielectric material that has already formed trenches. Laser ablation is then performed on the conductive layer within the trenches and on top of the dielectric. This results in the formation of fine lines (<10 μm) within the trenches. A seed layer can be observed below the fine lines and on one sidewall. The dielectric material needs to be patterned prior to electroplating.

[0007] CN110572945A describes the formation of lines in copper using a laser for PCBs. Prior to laser ablation, the copper surface requires polishing, brushing, cleaning, and drying, and necessitates CMP treatment. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and to provide an improved component carrier and an improved method for producing the component carrier.

[0009] The scope of this invention is determined by the subject matter of the independent claims. The dependent claims specify particular embodiments of the invention.

[0010] To provide an enhanced component carrier, the present invention proposes a stack in which the base of each portion is connected to at least one sidewall to form a base edge, the sidewall facing the adjacent portion and having an inclination of less than 90° relative to the base, wherein the distance between the base edges of two adjacent portions is less than 10 μm.

[0011] This offers the following advantages: a high density of conductive portions can be generated in at least a portion of the component carrier. Furthermore, this can facilitate miniaturization of the component carrier, particularly due to the appropriate use of specific removal processes, suitably configured to achieve a distance of less than 10 μm between two adjacent portions. The actual shape of the portion (having at least one sidewall with a specific inclination) is clearly imprinted by a removal process (e.g., laser subtraction) that creates a space between the portions.

[0012] A preferred embodiment is characterized by a rounded lateral transition region between at least one sidewall and the upper end of the portion. This shape with a rounded upper profile can result in at least one of improved mechanical reliability, prevention of material migration, reduced signal paths, and higher current carrying capacity. For prevention of material migration, this means optimizing the shape and material of the portion in a way that reduces or ultimately eliminates material migration from the conductive layer structure into the electrically insulating layer structure. This effect may be more pronounced at the edges due to the higher current density. A rounded profile can have a lower current density compared to the edges, thus protecting the material from migration.

[0013] According to another embodiment of the invention, a component carrier is provided, wherein at least one of two adjacent portions has a thickness ranging from 1 μm to 20 μm, and in particular, the ratio of the thickness difference is in the range of 80% to 120%. This provides the advantage of high design flexibility through easy subtraction steps. Moreover, portions with different corresponding application purposes (e.g., transmitting electrical signals or transmitting heat energy (thermal conduction)) can be easily integrated into the component carrier. The thickness difference refers to the difference in thickness (height, in the vertical direction) between two adjacent portions and / or between two sides of a particular portion, for example, by removing the top portion of a portion or due to the tilt and / or unevenness of the outer plane of the conductive layer structure caused by laser ablation.

[0014] The simple profile of this section is achieved through an embodiment in which at least one sidewall extends linearly or in a curved shape from the upper end (particularly from the rounded corner transition area) to the base edge at various locations along its length. This can provide the additional advantages of highly reliable and fast signal transmission. Moreover, it can prevent short-circuit events between two adjacent sections.

[0015] A preferred embodiment of the invention is characterized in that the two portions comprise two traces adjacent to each other. This can bring the advantage of easy production of component carriers with easily integrated structures (for example, for transmitting electrical signals or transmitting heat energy (thermal conduction)), particularly with highly reliable and fast signal transmission and prevention of any short-circuit events between the traces, while achieving a fine-wire conductive layout.

[0016] Preferably, at least one of the traces includes a base in contact with a common layer, an upper end opposite the base, and two sidewalls connecting the base and the upper end. This allows for a highly reliable and mechanically stable arrangement of the traces. A component carrier is preferred, wherein the width of the base of at least one of the two traces is less than 20 μm, particularly less than 10 μm, and most preferably less than 6 μm. This can provide the advantage of producing smaller conductive traces, which can be obtained, particularly in high-density interconnect layers, using suitable material removal processes (e.g., laser ablation), to produce these fine lines / traces. Furthermore, the smaller traces can be connected to active components (e.g., chips).

[0017] Another advantageous embodiment is characterized in that more than two traces are provided along each other, wherein the distance between the nearest base edges of two adjacent traces is less than 10 μm. This can provide the advantage of precisely generating conductive traces without product-related size limitations. In particular, this can provide greater handling and / or product flexibility.

[0018] In a more preferred embodiment, at least one of the two traces includes a 1 μm... 2 Up to 120μm 2 Cross-sectional area within the range between, especially at 4μm 2 up to 35μm 2 Within this range, the advantages are as follows: high-density conductive traces can be generated in at least a portion of the component carrier. Furthermore, this facilitates miniaturization of the component carrier due to the use of precise manufacturing methods employing material removal processes (particularly laser beams). Specific cross-sections allow for the appropriate current flow, thus preventing the traces from overheating and appropriately balancing them with the smaller trace dimensions.

[0019] Preferably, the ratio between the distance between two adjacent base edges and the thickness of the portion is less than 1, particularly less than 0.5. This feature offers the advantage of creating two portions (e.g., conductive traces) that are closely spaced from each other. This can result in a very high localized density of conductive material, enabling rapid data transmission and / or heat dissipation. Through specific material removal processes, the distance between two adjacent gaps that ultimately form a single trace can be reduced, resulting in a smaller width of the base of that portion compared to the thickness of the conductive layer structure from which the material has been removed.

[0020] Another embodiment of the invention shows that the sidewalls facing adjacent portions have an inclination relative to the base in the range of 75° to 85°. This can provide the advantage of reliably generating conductive portions (e.g., traces) without the risk of short-circuit connections. It is possible to prevent two adjacent portions from connecting at their respective upper ends because the inclination increases the distance between the portions compared to the distance between the nearest base edges.

[0021] Another embodiment features a base forming a sharp edge transition portion that transitions to the adjacent sidewall. This offers the advantage of ensuring the high integrity of the corresponding conductive portion and the stack, because a gap is formed between the two adjacent portions defining the sharp edge after the conductive layer structure is provided. Furthermore, the sharp edge transition portion can aid in the transmission of electrical signals.

[0022] According to an advantageous embodiment of the invention, the outer contour of at least one portion above the base and rising above the base has no sharp edges. This can provide the advantage of fast signal transmission while ensuring low signal loss, since edges can interfere with proper signal transmission. Moreover, the free edges can protect these portions from the effects of conductive material migration.

[0023] Preferably, all parts (especially the sidewalls) have a roughness parameter Ra of less than 15 μm, particularly less than 5 μm, and even more particularly less than 2 μm. This offers the advantage of reduced signal loss due to the skin effect. Furthermore, it ensures a low surface area that may be susceptible to chemical decomposition (e.g., oxidation).

[0024] In a more preferred embodiment, the common layer comprises a material different from that of the portion, particularly an electrically insulating material, and more particularly an organic polymer material. This ensures electrical integrity within the component carrier and prevents short circuits.

[0025] According to an advantageous embodiment of the invention, the electrical insulating material is arranged in the gap between at least two adjacent portions. This can provide the advantage of reduced chemical decomposition, particularly on the sidewalls. Furthermore, this can improve the mechanical stability of the component carrier, since there may be no available cavities between these portions, thus enhancing mechanical properties.

[0026] The preferred embodiment is characterized by including an electrically insulating material with embedded fillers. This can have the advantage of altering the physical properties of the electrically insulating material (e.g., Young's modulus).

[0027] In a more preferred embodiment, a portion of the common layer located between two adjacent portions has a tray-like shape. This feature offers the advantage of preventing electrical connections between the respective two adjacent portions, which is particularly beneficial for portions in the form of traces. Furthermore, the tray-like portion can additionally enhance the mechanical stability of the stack.

[0028] Another highly advantageous embodiment of the invention is a component carrier that further includes another conductive layer structure comprising two or more adjacent portions disposed on another common layer, each portion having another base in contact with the other common layer, another upper end opposite the other base, and at least one other sidewall connecting the other base and the other upper end, wherein the other base of each portion is connected at its end to its corresponding at least one other sidewall, each forming another base edge, the other sidewall facing the adjacent portion having an inclination of less than 90° relative to the other base, wherein the other distance between the nearest other base edges of the two adjacent portions is less than 10 μm.

[0029] This offers the advantage of greater flexibility in component carrier design. Furthermore, another conductive portion (e.g., in the form of a trace) allows for more complex component carrier designs, while also enabling the precise formation of another portion created through material removal processes.

[0030] Preferably, the two additional portions are positioned such that they are offset along the stack thickness direction compared to the two portions viewed below or above along the stack thickness direction. This can offer the advantage of easily and efficiently producing a high-density three-dimensional matrix of conductive material / structure through material removal processes. Furthermore, fewer processing steps may be required (to produce the same or similar component carriers) compared to standard component carrier manufacturing processes.

[0031] A further preferred embodiment of the invention is characterized in that a laser stopping layer is provided or included at least at the bottom of the gap between adjacent portions. This feature ensures high-precision manufacturing of the component carrier and helps to guarantee the defined geometry of the portions produced by material removal processes (especially laser beams).

[0032] Another preferred embodiment of the invention provides a component carrier in which at least one of the two parts defines a connecting disk. This offers the advantages that these structures can be easily manufactured with high precision and easily integrated into complex designs, while also exhibiting high mechanical stability and improved electrical and electronic properties.

[0033] According to another embodiment of the invention, a component carrier in which two parts are connected to each other, particularly defining two opposite sides of a hole or groove, allows for easy fabrication of structures such as degassing holes or grooves, and also has fewer processing steps compared to standard component carrier manufacturing processes. Holes can have various desired forms, having circular or elliptical shapes, or even polygonal or irregular closed curve edges. Grooves can be straight or have curved longitudinal extensions, or even both shapes.

[0034] The object of the present invention is also achieved by a method for producing a component carrier according to any of the preceding paragraphs, the method comprising the steps of: providing a stack comprising at least one conductive layer structure and at least one electrically insulating layer structure; and then performing a material removal process, wherein the material removal process is applied to the at least one conductive layer structure. This can provide the advantages of high production volume due to fewer manufacturing steps, while ensuring highly reliable products with well-defined trace geometry produced by the material removal process.

[0035] A preferred embodiment of this method is characterized in that the material removal process includes the application of electromagnetic waves, particularly a laser beam. This method of using laser ablation to create generally elongated recesses in a conductive layer (e.g., a copper layer) allows for precise fine-line patterning with easy selective processing, requiring fewer processing steps as photolithography cycles, CMP, and Ti etching are unnecessary. Traces with defined shapes and high aspect ratios can be obtained. This offers the advantage of enabling the production of part carriers with high precision using precisely manipulated electromagnetic waves. Furthermore, the properties of the laser beam can be tuned very accurately, for example, by applying the laser beam for a few femtoseconds (fs).

[0036] Preferably, a laser beam is applied, the laser beam comprising at least one of the following wavelength ranges: green light of 480nm-580nm, UV light of 280nm-410nm, a laser source of 218nm-299nm, or a CO2 laser of 750nm-2500nm. This allows for the most precise and efficient material handling of the material present in the component carrier and the material used for the trace.

[0037] Another preferred embodiment of the above method includes providing a laser stop layer at the rear bottom position of the gap between adjacent portions, preferably removing the laser stop layer after the portion has been formed by etching. Compared to prior art manufacturing processes, this offers the advantage of improved accuracy in material removal while reducing the number of processing steps.

[0038] Preferably, the material removal process does not use a mask. This can bring the advantage of simplifying the manufacturing process, especially by using fewer processing steps, while having highly precise and well-defined parts inside the part carrier through the use of material removal.

[0039] Component carriers can also be configured as one of a group including printed circuit boards and substrates (particularly IC substrates). In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a component carrier (which can be planar (i.e., planar), three-dimensionally curved (e.g., when manufactured using 3D printing), or of any other shape) formed by laminating multiple conductive layer structures with multiple electrically insulating layer structures, for example by applying pressure, accompanied by the supply of heat when necessary. As preferred materials for PCB technology, the conductive layer structures are made of metal (e.g., copper), while the electrically insulating layer structures can include resin and / or glass fiber, so-called prepreg or FR4 material. Various conductive layer structures can be connected to each other in a desired manner by forming vias through the laminate (e.g., by laser drilling or mechanical drilling) and by filling them with a conductive material (particularly copper), thereby forming via connections. In addition to one or more components that can be embedded in a printed circuit board, printed circuit boards are generally configured to accommodate one or more components on one or two opposing surfaces of a planar printed circuit board. They can be connected to the respective main surfaces by soldering. The dielectric portion of a PCB can be made of resin with reinforcing fibers (such as glass fiber).

[0040] In the context of this application, the term "substrate" can specifically refer to a small component carrier having substantially the same size as the component (particularly electronic component) to be mounted thereon. More specifically, a substrate can be understood as a carrier for electrical connections or networks and a component carrier equivalent to a printed circuit board (PCB), however, with a significantly higher density of laterally and / or vertically arranged connectors. Lateral connectors are, for example, conductive paths, while vertical connectors can be, for example, drilled holes. These lateral and / or vertical connectors are arranged within the substrate and can be used to provide electrical and / or mechanical connections between packaged or unpackaged components (e.g., bare dies) (particularly IC chips) and the printed circuit board or intermediate printed circuit board. Therefore, the term "substrate" also includes "IC substrate." The dielectric portion of the substrate can be constructed of resin with reinforcing spheres (e.g., glass spheres).

[0041] At least one electrically insulating layer structure can include at least one of the following groups: resins (e.g., reinforced or unreinforced resins, such as epoxy resins or bismaleimide-triazine resins, more particularly FR-4 or FR-5), cyanate esters, polyphenylene derivatives, glass (especially glass fibers, multilayer glass, glassy materials), prepreg materials, polyimides, polyamides, liquid crystal polymers (LCPs), epoxy-based laminated films, polytetrafluoroethylene (Teflon), ceramics, and metal oxides. Reinforcing materials, such as meshes, fibers, or spheres, made of glass (multilayer glass), may also be used. While prepregs or FR4 are generally preferred, other materials may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate ester resins can be implemented as electrically insulating layer structures within a component carrier. The electrically insulating layer structure may include multiple electrically insulating layer structures with optional conductive layer structures (multilayer cores).

[0042] At least one conductive layer structure may include at least one material from the group consisting of copper, aluminum, nickel, silver, gold, palladium, tin, titanium, cobalt, manganese, and platinum. While copper is generally preferred, other materials or their coating forms are also possible, particularly coatings with superconducting materials such as graphene. The conductive layer structure may include a surface finish. Furthermore, the conductive layer structure may include materials such as conductive polymers (e.g., graphene or poly(3,4-ethylenedioxythiophene) (PEDOT)). Moreover, it may have an electrically insulating core covered by a conductive shell. Furthermore, it may be a metal containing fluid or solid particles (similar to a gel or foam).

[0043] Conductive layers can form electrical or electronic components, conductive traces, vias, etc. Traces are highly conductive lines used to connect components on a circuit carrier or stack to each other. Because traces are used for conduction, they are made of highly conductive and stable materials. Key parameters to consider include trace width, trace thickness, trace resistance, trace impedance, and trace current.

[0044] At least one component can be selected from the group consisting of, for example, non-conductive inlays, conductive inlays (e.g., metallic inlays, preferably copper or aluminum), heat transfer units (e.g., heat pipes), optical guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. For example, the component can be an active electronic component, a passive electronic component, an electronic chip, a storage device (e.g., DRAM or other data storage), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a encryption component, a transmitter and / or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components can be embedded within a component carrier. For example, a magnetic element can be used as a component. This magnetic element can be a soft magnetic element, particularly a ferromagnetic, antiferromagnetic, or ferrimagnetic element, such as a ferrite core, or it can be a paramagnetic element. However, the component can also be another component carrier, such as in a board-in-board structure. Components can be surface-mounted on a component carrier and / or embedded within it. Furthermore, other components (particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment) can also be used as components.

[0045] In this embodiment, the component carrier is a laminated component carrier, also known as a stack. In such an embodiment, the component carrier is a multilayer composite structure that is stacked, particularly in parallel layers, and bonded together by applying pressure (accompanied by heat if necessary). The component carrier may be configured to carry another electrical and / or electronic component, such as a resistor, capacitor, diode, transistor, or integrated circuit. The thickness of the stack is a dimension of the stack that is perpendicular to the plane of its layers. Attached Figure Description

[0046] Embodiments of the present invention are described below with reference to the accompanying drawings. The present invention is not limited to the embodiments shown or described.

[0047] Figure 1 It shows the basic structure of the component carrier;

[0048] Figure 2 A top view showing a first simple arrangement of two parts according to the invention, which are the conductive region and adjacent traces;

[0049] Figure 3 The top view shows a second arrangement of two parts, both of which are in the form of adjacent traces of curved longitudinal extensions;

[0050] Figure 4This illustrates another embodiment of the invention, which consists of two parts: a connecting disk and a short straight trace.

[0051] Figure 5 This illustrates the arrangement of the two parts that define the basic circular hole;

[0052] Figure 6 The vertical section of a schematic cross-sectional view of two adjacent traces according to the present invention is shown.

[0053] Figure 7 A schematic cross-sectional view showing two adjacent traces of different shapes;

[0054] Figure 8 This shows three different arrangements of traces on the component carrier;

[0055] Figure 9 This indicates the arrangement of traces at different levels within the component carrier;

[0056] Figure 10 This indicates three stages in the production and processing of the component carrier;

[0057] Figure 11 An embodiment of a component carrier having a laser stopping layer is shown. Detailed Implementation

[0058] The component carrier used in this invention includes a stack 1 having at least one conductive layer structure 2 (preferably copper or a copper-based material) and at least one electrically insulating layer structure 3. The conductive layer structure 2 includes at least two portions P1 and P2, which can be adjacent traces 4 arranged on a common layer 5, typically an electrically insulating layer structure, but possibly also a thermally insulating layer structure, such as glass. As a further or alternative to such traces 4, the conductive layer structure 2 may include a connecting disk 25, typically a circular design, constituting another embodiment of portions P1 and P2. The portions P1 and P2 may also be a combination of the connecting disk 25 and traces 4 and disks, or even holes 26 defined in the material of at least one conductive layer structure 2 and ultimately at least one electrically insulating layer structure 3 (see...). Figure 5 ) or slot.

[0059] Figure 2 The arrangement according to the invention is shown, comprising two portions P1 and P2, which take the form of a boundary region of an extended conductive structure 27 (for P1) and an adjacent narrow trace 4 (for P2). Although Figure 2 Some examples represent straight structures, but Figure 3 This is an example of a curved structure, in which the curved structure takes the form of two adjacent traces 4 of a curved longitudinal extension, with each of the two parts P1 and P2 being a narrow trace 4.

[0060] As a further step or alternative to trace 4 or segment 27 of the wide conductivity structure, at least one of portions P1 and P2 may also include a connecting disk 25. This connecting disk 25 ( Figure 4 P2) is the exposed area of ​​conductive material on the stack 1, on which components can be soldered, here in the form of surface mount disks. These are constructed using space-constrained structures and can be separated from adjacent portions of the conductive layer structure by a removal process (e.g., by laser ablation), thus allowing for rectangular, circular, square, elliptical, or any other suitable design; and for use with Figure 4 The same as disk 25 in the middle, Figure 1 , Figure 2 and Figure 3 The trace 4 in the diagram is also a result of a removal process applied to the conductive layer structure, which separates the conductive layer structure into multiple parts to obtain the desired partial shape. These disks 25 can be arranged adjacent to other similar disks 25 or adjacent traces 4, such as... Figure 4 Part P1 is shown in the middle.

[0061] Parts P1 and P2 can also be connected to each other by defining notches, holes, grooves, or drilled holes in a specific material. For example... Figure 5 As shown, portions P1 and P2 can specifically define two opposite sides of the hole 26 or slot. Similar to the disc 25, the hole 26 can be rectangular, circular, square, elliptical, or any other suitable design.

[0062] The groove can have any desired longitudinal extension and can be straight or curved, or include both types of extensions. Also according to this embodiment, the extension is the result of a removal process applied to the conductive layer structure, in this case manifesting as a through-hole or groove obtained, for example, by laser ablation.

[0063] Features and description of the invention (refer to below) Figures 6 to 11 (The arrangement of portions P1 and P2, including two adjacent traces 4, is described.) All structures of portions P1 and P2 are applied in a similar or analogous manner, and these may be traces 4, disks 25, holes 26, or slots.

[0064] Trace 4 can be a straight linear structure, but it can also be bent once or multiple times, with sharp or rounded bends, and can be curved, spiral (to define a flat coil structure), tortuous, or have any other geometry required in the integrated circuit structure. Gaps or notches can even be provided within an identical trace 4 in any part of P1, P2.

[0065] The layer sandwiched between the two parts of the insulating layer structure 3 will also typically include structures such as traces and disks as part of the conductive layer structure 2 at the top surface of the stack 1.

[0066] like Figure 6 As shown in the diagram, each trace 4 has a base 6 that contacts the common layer 5, an upper end 7 opposite to the base 6, and two sidewalls 8 connecting the base 6 and the upper end 7.

[0067] The base 6 does not need to be a continuous plane, but may have at least one notch in the central direction of the trace 4, and / or may have at least one protrusion penetrating into the support layer. The support layer (especially the common layer 5) may be designed to at least partially protrude into the possible notch in the base 6 of the trace 4, thereby filling the notch with its own common layer material.

[0068] The upper end 7 of the trace 4 may be arranged parallel to the base 6. Other possible embodiments of the upper end 7 include an upper end 7 inclined toward the base 6, having a roof-like shape, having a recessed portion or a continuous or coherent groove, a stepped design 24 on one or both sides of the trace 4, defining a concave notch in the upper transition portion of the trace 4, or any other structure required for a special purpose.

[0069] Each trace 4 rises above the common layer 5. The common layer 5 is preferably made of a material different from that of the trace 4, particularly an electrically insulating material, and more particularly an organic polymer material.

[0070] The base 6 of each trace 4 connects to two corresponding sidewalls 8 at its opposite ends, with each sidewall forming a base edge 9. Preferably, the base 6 forms a sharp edge portion that transitions into at least one adjacent sidewall 8 (most preferably two adjacent sidewalls 8), although at least one rounded edge structure is preferably on the side opposite to the nearest adjacent trace 4.

[0071] At least the sidewalls 8 facing adjacent traces 4 have a total inclination (α) of less than 90° relative to the base 6. The total inclination refers to the inclination when a straight line is drawn from the base edge 9 to the upper transition region (from the sidewall 8 to the upper end). Between these endpoints, the sidewalls 8 may deviate from the straight line or deviate multiple times. Since the base 6 is substantially parallel to the plane of the common layer 5 and the entire plane of the stack 1, the sidewalls 8 have substantially the same inclination (α) relative to the common layer 5 and the entire stack 1. Preferably, the inclination (α) is in the range of 50° to 85°, preferably but not necessarily for the two sidewalls 8 of the same trace 4. Most preferably, the inclination (α) is in the range of 75° to 85°. Moreover, the inclination (α) can be different for two nearest adjacent traces 4, and can be different for all sidewalls 8 of the trace 4. The precise value of the inclination (α) can be changed once or multiple times along the longitudinal extension of the trace 4, wherein there are sloping or sharp transition portions between portions with different inclinations. These transition sections may also have non-shaped transitions between inclinations, for example, when at least one parameter used to calculate the gap between the two traces 4 changes.

[0072] The distance D between the base edges 9 of two adjacent traces 4 at their nearest location is less than 10 μm, and this distance can be greater at other locations when needed or intentionally, thus providing the advantage of greater design flexibility.

[0073] Each trace 4 preferably represents a rounded lateral transition region 10 between each of the two sidewalls 8 and the upper end 7, for example, as shown in the figure. Figure 6 As shown. In addition, a sharp edge transition area can be provided between the sidewall 8 and the upper end 7, such as... Figure 7 Another embodiment of portions P1 and P2 shown. For example... Figure 8 In the upper arrangement shown, all types of transition designs can also be set in the same trace 4.

[0074] Preferably, the rounded lateral transition region 10 has a convex shape. Alternatively, the rounded lateral transition region 10 may also have a concave shape. However, at various locations along the length of the trace 4, each of the two sidewalls 8 preferably extends linearly from the upper end 7 (particularly from the rounded lateral transition region 10) to the base edge 9.

[0075] Preferably, at least one trace 4 includes a 1 μm 2 Up to 120μm 2 The cross-sectional area within the range between, especially at 4 μm 2 up to 35μm 2Within the range between [specific values]. The overall aspect ratio of the arrangement of trace 4 and adjacent traces 4 is 1:1.5 for the upper platform to the base width, 5:1 for the base width to the trace thickness, preferably 2:1, or most preferably 1:1 (minimum), and 5:1 for the distance between the base width and the trace 4, preferably 2:1, or most preferably 1:1 (minimum). When provided by lamination, electrochemical plating, or any non-electrochemical process (e.g., chemical or physical deposition), the maximum thickness of the copper trace 4 depends on the thickness of the copper layer. The width of the base 6 of at least one of the two traces 4 is less than 20 μm, particularly less than 10 μm, and most preferably less than 6 μm. Alternatively, the width is in the range of 20-50 μm.

[0076] like Figure 7 As shown, adjacent traces 4 can have different shapes and cross-sections. Instead of the rounded transition region 10, it is preferable that the sidewalls 8 and the upper end 7 can also form sharp upper edges 11, preferably through a suitable arrangement of parameters to remove the processing. It is also preferable to have an arrangement of portions P1 and P2, wherein at least one of the two adjacent traces 4 has a thickness in the range of 1 μm to 20 μm, particularly with the thickness difference ratio in the range of 80% to 120%. Preferably, the area ratio between adjacent traces 4 can be in the range of 50-100%.

[0077] Refer again Figure 1 Another embodiment of the component carrier according to the invention includes a stack 1, wherein more than two portions P1, P2 (e.g., more than two traces 4) are arranged to extend along each other and possibly parallel to each other over a considerable length, wherein the distance between each pair of adjacent base edges 9 of every two adjacent traces 4 is less than 10 μm. For all embodiments having any number of traces 4, it is preferred that the ratio between the distance between two adjacent base edges 9 and the thickness of the trace 4 is less than 1, particularly less than 0.5. Alternatively, it may be in the range of 1 to 5.

[0078] Alternatively, for all embodiments of the component carrier according to the invention, at least one of the traces 4 rising above the base 6 and above the base 6 and the common layer 5 has no edge on its outer profile. This can include a semi-circular / semi-elliptical shape in cross-section. Moreover, it is preferred that all traces 4 (especially their sidewalls 8) have a roughness parameter Ra of less than 15 μm. In particular, Ra is less than 5 μm, and most preferably even less than 2 μm. Alternatively, Ra can be in the range of 15-30 μm.

[0079] As in Figure 8As shown in all three alternatives illustrated, the electrical insulating material 12 can be arranged in the gap between at least two adjacent traces 4, or, when necessary, in any possible hole 26 or slot 23 defined by or within portions P1, P2 (see [reference]). Figure 8 (bottom arrangement) or stepped recesses 24. The grooves 23 in the upper portion of the trace 4 may also remain without any filler 12 (see...). Figure 8 (Upper arrangement). Preferably, the gaps are completely filled. Alternatively, the gaps may include voids filled with a fluid (e.g., gas (air) or liquid (water)). The insulating material 12 used to fill the gaps between traces 4 can be different from the material used for the common layer 5, although both may be the same material. The gap-filling insulating material 12 can include embedded fillers. Also, on any outer layer, any gap is preferably filled using any solder resist (also a non-conductive insulating material as described herein), since no wire is exposed at any layer. Preferably, the filler can have a circular shape, such as a sphere. More preferably, the diameter of the filler can be less than 1 μm, more preferably less than 500 nm. The filler material can be made of organic materials (e.g., organic polymers) or inorganic materials (e.g., ceramics or glass or materials without glass spheres) or any nano-sized particles (e.g., flame retardants or stabilizers). Moreover, the filler can be fluid or solid, and when it is solid, it can be porous.

[0080] Still Figure 8 The embodiment of the component carrier is shown in the middle line, wherein at least a portion of the common layer 5 located between two adjacent traces 4 has a tray-like shape 13 with rounded corners or sharp edges.

[0081] Figure 9 Another embodiment of the invention, P1 and P2, is shown, in which a component carrier is provided, the stack 1 of which includes at least one other conductive layer structure 14, the other conductive layer structure 14 including two other traces 15 arranged adjacent to each other on another common layer 16. The other common layer 16 may be another separate layer of the stack 1, with the advantage of being able to freely choose materials independent of all other materials, or it may be an integral part of the electrically insulating structure 3.

[0082] Each other trace 15 again has another base 17 in contact with another common layer 16 and another upper end 18 opposite to said other base 17. Each other trace 15 again has two other sidewalls 19 connecting the other base 17 and the other upper end 18. As in the above embodiment, here again, the other base 17 of each other trace 15 connects to its corresponding two other sidewalls 19 at opposite ends, each forming another base edge. Preferably, all geometric and other features of the other trace 15 are similar to those in the above embodiment, in particular, the inclination (β) of the other sidewall 19 facing the adjacent trace 15 relative to the other base 17 is less than 90°, preferably between 75° and 85°. It is also preferred that the other distance between the nearest other base edges of two other adjacent traces 15 is less than 10 μm.

[0083] like Figure 9 As can be clearly seen, in another embodiment of the invention, the two additional traces 15 are positioned such that the two additional traces 15 are preferably offset along the stack thickness direction compared to the two traces 4. Therefore, the base 17 of the additional trace 15 faces the upper end 7 of the trace 4. Alternatively, the other upper end 18 may face the upper end 7. The trace 15 may be connected to the trace 4 via vias or other conductive elements, or it may be a completely independent circuit.

[0084] The following will refer to Figure 10 A preferred embodiment of the method for manufacturing a component carrier having portions P1 and P2, as described with reference to a specific embodiment including trace 4, disk 25, hole 26, or groove.

[0085] The method includes the step of providing a stack 1 comprising: at least one conductive layer structure 2, which will later become a structured layer having disks and traces; and at least one electrically insulating layer structure 3. This can include vias 20 or subsequently form vias 20 in a dielectric 21, which is part of the insulating layer structure 3. Next, another conductive material 22 is applied for later forming of traces 4 to produce… Figure 10 The intermediate product shown in the middle; alternatively, traces can be formed on the conductive layer structure 2. A seed layer can be provided between the electrically insulating layer structure 3 and the corresponding conductive layer structure. For example, non-electrodeposited copper, which is commonly used to form the seed layer, can also achieve the required conductive material thickness, preferably made of the same material as the conductive material. Even other conductive and / or organic insulating materials can be used as the seed layer.

[0086] Then, a material removal process is performed, preferably by applying an electromagnetic wave, preferably a laser beam, to the conductive material 22, particularly a laser pulse. The stack 1 moves along a track according to the shape of the traces 4 to be processed below the processing device, wherein the depth of the gap between adjacent traces 4 is a function of processing parameters. Furthermore, the inclination and shape of the sidewalls 8 of the traces 4 are determined by processing parameters, particularly the wavelength, energy, and pulse width of the laser device.

[0087] For example, the following parameters have been found to be advantageous:

[0088] Example 1:

[0089] L / S ~ 2μm, 343nm, 6kHz, 0.026W, 10-40 repetitions per line, velocity 0.5-5mm / s, pulse energy ~50nJ

[0090] Example 2:

[0091] L / S > 10 μm, 355 nm, 1000 kHz, pulse length 10 ps, ​​energy 0.25–0.5 μJ, velocity 1–2 m / s, optimal 0.5 μJ, 2 m / s, repeated 30 times.

[0092] Finally, it was achieved as follows Figure 10 The last line shows and Figure 1 The component carrier shown has some of the desired structures of P1 and P2, such as trace 4. In this process, the fine line structure is directly ablated into, for example, a copper layer by laser. Simultaneously, the seed layer is removed. Preferably, laser ablation is also used to form disks (such as disks around laser vias). Even the traces can have circular shapes of different diameters.

[0093] Preferably, the laser radiation is used in at least one of the following ranges: green light (480nm-580nm), UV light (280nm-410nm), laser source (218nm-299nm), and CO2 laser (750nm-2500nm). The choice of laser parameters will determine the ablation width and quality. Ultrashort pulse lasers (fs or ps) with UV or green wavelengths are the most suitable lasers for fine lines.

[0094] like Figure 11 As shown, the laser stopping layer 28 can be positioned at the bottom rear of the gap between adjacent traces 4. The material removal process for ablating conductive material (particularly copper) to create a gap between adjacent traces 4 proceeds from the top to the bottom of the gap until it reaches the laser stopping layer 28. Here, the laser action is blocked by the laser stopping layer 28.

[0095] The laser stop layer 28 may comprise a carbon-based material, particularly a multi-carbon structure (polyol or sugar molecule), or a silicon-based material, particularly a (poly)silicate structure. The laser stop layer 28 can be readily and selectively removed using polar solvents (e.g., water or alcohol compounds or mixtures thereof). After the formation of the trace 4, the laser stop layer 28 of different materials can be removed in a subsequent step by an etching process. Another embodiment of the invention provides a laser stop layer 28 that can be retained within the stack 1. The trace 4 or any other structure on and within the stack is unaffected by the etching step, which does not further modify the geometry of the formed copper trace 4. Optionally, at least 100 nm of exposed conductive traces / structures may be further removed.

[0096] This process can also be used to form fine lines in selected areas, such as RDL layers used for chip interconnects. The thickness of trace 4 can also be modified (reduced) by laser ablation. This results in lower resistance, which simultaneously enhances (electrical) signal transmission when trace 4 and / or disk 25 are connected to (active) components (such as chips).

[0097] List of reference numerals

[0098] 1 stacked component

[0099] 2. Conductive layer structure

[0100] 3 Electrical insulation layer structure

[0101] 4 traces

[0102] 5 public floors

[0103] 6 base

[0104] 7. Top

[0105] 8 sidewalls

[0106] 9 Base Edge

[0107] 10. Rounded lateral transition area

[0108] 11 top edge

[0109] 12 Electrical insulation materials

[0110] 13 Tray-shaped gap bottom

[0111] 14 Another conductive structure

[0112] 15 Another trace

[0113] 16 Another public floor

[0114] 17 Another base

[0115] 18 Another upper end

[0116] 19. The other side wall

[0117] 20 through holes

[0118] 21 Dielectric

[0119] 22 seed layers

[0120] 23 slots

[0121] 24 stepped transition sections

[0122] 25 connecting disks

[0123] 26 exhaust holes

[0124] 27 Extended conductive structure

[0125] 28 laser stop layers

[0126] (α) Inclination of the sidewall

[0127] (β) Inclination of the other sidewall

[0128] Part of the P1 conductive layer structure

[0129] Part of the P2 conductive layer structure

[0130] Another part of the P3 conductive layer structure

[0131] Another part of the P4 conductive layer structure

Claims

1. A component carrier, the component carrier comprising: The stack (1) includes at least one conductive layer structure (2) and at least one electrically insulating layer structure (3). The at least one conductive layer structure (2) includes two adjacent portions (P1, P2) arranged on a common layer (5). Each of the two parts (P1, P2) has a base (6) in contact with the common layer (5), an upper end (7) opposite to the base (6), and at least one sidewall (8) connecting the base (6) and the upper end (7). The base (6) of each part (P1, P2) is connected to at least one sidewall (8) to form a base edge (9). The sidewall (8) faces the adjacent portions (P1, P2) and has an inclination (α) of less than 90° relative to the base (6), and The distance between the base edges (9) of the two adjacent parts (P1, P2) is less than 10 μm.

2. The component carrier according to claim 1, wherein: A rounded lateral transition region (10) exists between at least one sidewall (8) and the upper end (7) of the portions (P1, P2).

3. The component carrier according to claim 1 or 2, wherein: The at least one sidewall (8) extends linearly or in a curved shape from the upper end (7), particularly from the rounded side to the transition region (10), at various locations along its length to the base edge (9).

4. The component carrier according to any one of claims 1 to 3, wherein: The two parts (P1, P2) consist of two adjacent traces (4).

5. The component carrier according to claim 4, wherein: At least one of the traces (4) includes a base (6) in contact with the common layer (5), an upper end (7) opposite to the base (6), and two sidewalls (8) connecting the base (6) and the upper end (7).

6. The component carrier according to claim 5, wherein: The width of the base (6) of at least one of the two traces (4) is less than 20 μm, particularly less than 10 μm, and most preferably less than 6 μm.

7. The component carrier according to any one of claims 5 or 6, wherein: Two or more traces (4) are set along each other, and the distance between the nearest base edges (9) of two adjacent traces (4) is less than 10 μm.

8. The component carrier according to any one of claims 5 to 7, wherein: At least one of the traces (4) includes 1 μm 2 With 120μm 2 The cross-sectional area within the range between, especially at 4 μm 2 With 35μm 2 The cross-sectional area within the range between.

9. The component carrier according to any one of claims 1 to 8, wherein: The ratio between the distance between two adjacent base edges (9) and the thickness of the portion (P1, P2) is less than 1, and in particular less than 0.

5.

10. The component carrier according to any one of claims 1 to 9, wherein: The sidewall (8) facing the adjacent portions (P1, P2) has an inclination (α) relative to the base (6) in the range of 75° to 85°.

11. The component carrier according to any one of claims 1 to 10, wherein: The base (6) forms a sharp edge transition portion that transitions to the adjacent sidewall (8).

12. The component carrier according to any one of claims 1 to 11, wherein: At least one of the portions (P1, P2) that are raised above the base (6) has no sharp edges on its outer contour.

13. The component carrier according to any one of claims 1 to 12, wherein: All parts (P1, P2), especially the sidewalls (8), have a roughness parameter Ra of less than 15 μm, especially less than 5 μm, and even more especially less than 2 μm.

14. The component carrier according to any one of claims 1 to 13, wherein: The common layer (5) comprises a material different from that of the portions (P1, P2), particularly an electrical insulating material, and more particularly an organic polymer material.

15. The component carrier according to any one of claims 1 to 14, wherein: Electrical insulation material (12) is arranged in the gap between at least two adjacent portions (P1, P2).

16. The component carrier according to claim 15, wherein: The electrical insulating material (12) includes embedded fillers.

17. The component carrier according to any one of claims 1 to 15, wherein: The portion of the common layer (5) located between two adjacent parts (P1, P2) has a tray-like shape.

18. The component carrier according to any one of claims 1 to 17, wherein: The component carrier also includes: Another conductive layer structure (14) includes two adjacent portions (P3, P4) disposed on another common layer (16). Each of the other portions has another base (17) in contact with another common layer (16), another upper end (18) opposite to the other base (17), and at least one other sidewall (19) connecting the other base (17) and the other upper end (18), wherein the other base (17) of each of the other portions (P3, P4) is connected to at least one other sidewall (19) at its end (18), thereby forming the other base edge. The other lateral sidewall (19) facing the adjacent portions (P3, P4) has an inclination (β) of less than 90° relative to the other base (17), and The other distance between the nearest other base edge of the two adjacent other parts (P3, P4) is less than 10 μm.

19. The component carrier according to claim 18, wherein: The two additional portions (P3, P4) are positioned such that the two additional portions (P3, P4) are offset along the stack thickness direction compared to the two portions (P1, P2).

20. The component carrier according to any one of claims 1 to 19, wherein: At least at the bottom of the gap between adjacent portions (P1, P2) a laser stopping layer (27) is provided or included.

21. The component carrier according to any one of claims 1 to 20, wherein: At least one of the two parts (P1, P2) is designated as the connecting disk (25).

22. The component carrier according to any one of claims 1 to 3 or 10 to 21, wherein: The two parts (P1, P2) are connected to each other, specifically defining the two opposite sides of the hole (26) or groove.

23. A method for producing a component carrier, said component carrier being a component carrier according to any one of claims 1 to 22, the method comprising: A stack is provided (1), the stack comprising at least one conductive layer structure (2) and at least one electrically insulating layer structure (3). Then perform the material removal process. The material removal process is applied to the at least one conductive layer structure (2).

24. The method according to claim 23, wherein: Material removal processes include applying electromagnetic waves, particularly laser beams.

25. The method of claim 24, wherein: The laser beam includes at least one of the following wavelength ranges: Green light in the 480nm-580nm range; UV light in the 280nm-410nm range; Laser light sources in the 218nm-299nm range; CO2 laser with a wavelength of 750nm-2500nm.

26. The method according to any one of claim 24 or 25, further comprising: A laser stop layer (27) is provided at the bottom (13) of the gap between adjacent portions (P1, P2), preferably the laser stop layer (27) is removed by etching after the portions (P1, P2) are formed.

27. The method for producing a component carrier according to any one of claims 23 to 26, wherein: No mask is applied during material removal.

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