Multi-layer dielectric gate spacer for finfet and gate-all-wall (GAA) devices

Abstract

An electronic device having one or more non-planar transistors is disclosed. At least one of the non-planar transistors includes: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one of the one or more gate spacers having a multi-layer dielectric structure, the multi-layer dielectric structure comprising an inner wall, the inner wall is adjacent to a corresponding gate structure in the one or more gate structures, and the inner wall is formed by a first dielectric material; an outer wall spaced apart from the inner wall, where the outer wall is formed of a second dielectric material; and a third dielectric material disposed between the inner wall and the outer wall, where a dielectric constant of the third dielectric material is lower than a dielectric constant of the first dielectric material and lower than a dielectric constant of the second dielectric material.

Description

Technical Field

[0001] This disclosure relates generally to nonplanar transistors, and more specifically to multilayer dielectric gate spacers for nonplanar transistors, and methods for fabricating multilayer dielectric gate spacers. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electronic components. An IC can be implemented as an IC chip on which a set of circuits is integrated. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where the various power and signal nodes of the one or more IC chips can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in the package substrate. Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing technologies can be used to implement complex devices such as multi-component devices and system-on-a-chip (SoC) devices, which can include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., WiFi, Bluetooth, and other communications), etc.

[0003] Transistors are considered the fundamental building blocks of electronic devices and are frequently incorporated into IC chips. These transistors have undergone several evolutionary changes to meet the ever-growing demands for high performance, low power consumption, and miniaturization. As the size of these transistors scales down to meet the need for higher transistor density, challenges such as short-channel effects, leakage current, and power dissipation become increasingly problematic.

[0004] Non-planar transistors, such as FinFETs and Gate-All-Around (GAA) transistors, have been developed to address these challenges. In FinFETs, the conductive channel rises above the substrate, forming a fin-like structure. In GAA transistors, the gate material completely surrounds the conductive channel, which is typically formed from nanowires or nanosheets, thereby improving electrostatic control and uniformity of the electric field. Non-planar transistor designs offer advantages such as lower leakage current, improved threshold voltage control, and the ability to operate at reduced supply voltages, thus improving overall energy efficiency.

[0005] While such nonplanar transistor architectures have improved transistor performance, they also present new challenges and complexities in terms of fabrication, material selection, and electrical characteristics. Therefore, there is a need for improved nonplanar transistor architectures and their fabrication methods. Summary of the Invention

[0006] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0007] In one aspect, an electronic device having one or more nonplanar transistors includes one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one of the gate spacers having a multilayer dielectric structure including an inner wall disposed adjacent to a corresponding gate structure of the one or more gate structures, wherein the inner wall is formed of a first dielectric material; an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0008] In one aspect, a nonplanar transistor includes: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one of the gate spacers having a multilayer dielectric structure including an inner wall disposed adjacent to a corresponding gate structure of the one or more gate structures, wherein the inner wall is formed of a first dielectric material; an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0009] In one aspect, a method of forming a fin field-effect transistor (FinFET) includes forming a channel structure having a semiconductor channel between the source and drain of the FinFET; forming a gate structure covering the semiconductor channel; and forming at least one gate spacer associated with the gate structure, wherein forming at least one gate spacer includes forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0010] In one aspect, a method of forming a gate all-around (GAA) transistor includes forming a plurality of channel structures between the source and drain of the GAA transistor; forming a gate structure associated with the plurality of channel structures; and forming at least one gate spacer associated with the gate structure, wherein forming at least one gate spacer includes forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0011] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0012] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0013] Figure 1A and Figure 1B Various elements of a FinFET (Fin Field-Effect Transistor) according to aspects of this disclosure are illustrated.

[0014] Figure 2A and Figure 2B Various elements of a FinFET employing multilayer dielectric gate spacers are illustrated according to various aspects of this disclosure.

[0015] Figure 3A and Figure 3B Various elements of a FinFET employing multilayer dielectric gate spacers are illustrated according to various aspects of this disclosure.

[0016] Figure 4A and Figure 4B Various elements of a gate all around (GAA) transistor according to aspects of this disclosure are illustrated.

[0017] Figure 5A and Figure 5B Various elements of a GAA transistor, including a multilayer dielectric structure for internal and external gate spacers, are illustrated according to aspects of this disclosure.

[0018] Figure 6A and Figure 6BVarious elements of a GAA transistor, including a multilayer dielectric structure for internal and external gate spacers, are illustrated according to aspects of this disclosure.

[0019] Figures 7A to 7I Example processes that can be used to manufacture FinFETs according to various aspects of this disclosure are shown.

[0020] Figures 8A to 8R Example processes that can be used to manufacture GAA transistors according to various aspects of this disclosure are shown.

[0021] Figure 9 This is a flowchart illustrating an example method for manufacturing a FinFET according to various aspects of this disclosure.

[0022] Figure 10 This is a flowchart illustrating an example method for manufacturing a GAA transistor according to various aspects of this disclosure.

[0023] Figure 11 A cross-sectional view of a package including a surface mount substrate, an integrated device, and an integrated passive device, according to various aspects of this disclosure, is illustrated.

[0024] Figure 12 Example methods for providing or manufacturing packages comprising integrated devices having electronic components mounted in a core, according to various aspects of this disclosure, are illustrated.

[0025] Figure 13 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC).

[0026] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0027] Various aspects of this disclosure are illustrated in the following description and related figures with respect to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Furthermore, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in this disclosure.

[0028] In some of the described example implementations, instances are identified where various component structures and operational parts are available from known conventional techniques and are then arranged according to one or more exemplary embodiments. In such instances, internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary embodiments disclosed herein.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the term “comprising,” as used herein, indicates the presence of stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be understood that when a layer is described as “on top of another layer,” “covering another layer,” “below another layer,” or “as lining another layer,” the use of intermediate layers and / or materials that may otherwise be used to ensure adhesion between layers is not necessarily excluded. Furthermore, it should be understood that when a layer is described as “on top of another layer,” “covering another layer,” “below another layer,” or “as lining another layer,” such terms are used with reference to the orientation of these layers as depicted in the reference system shown in the corresponding figures.

[0030] Figure 1A and Figure 1B Various elements of a FinFET 100 according to various aspects of this disclosure are illustrated. Here, Figure 1A This is a top view of the FinFET 100, and Figure 1B This is a cross-sectional view of FinFET 100 through axis X1-X1'. In this example, FinFET 100 is configured to receive bias and control signals via metallization structures 102, 104, and 106. In one aspect, metallization structures 102 and 106 may be formed of cobalt, manganese, or tungsten, and metallization structure 104 may be formed of tungsten. Metallization structures 102 and 106 extend through interlayer dielectric 108 to contact epitaxial structures 110 and 112, which are disposed on opposite sides of doped channel 114 and form the source / drain (S / D) structure of FinFET 100. In one aspect, epitaxial structures 110 and 112 may be formed of epitaxial silicon germanium (eSiGe) and / or epitaxial silicon (eSi) materials. Doped channel 114 is defined on its lateral sides by dummy gate structures 116 and 118, and below thereunder by a doped well 120 covering substrate 122. The doping of the doped well 120 (e.g., n or p doping) depends on the doping used for the doped channel 114.

[0031] FinFET 100 includes a gate structure 124 covering a doped channel 114. In one aspect, the gate structure 124 includes a gate contact 126 defined externally by a work function metal layer 128. The work function metal layer 128 is then externally defined by a gate dielectric layer 130, which is typically formed of a high dielectric constant material.

[0032] exist Figure 1B In the example shown, gate structure 124 is associated with a corresponding gate spacer 132. In one aspect, gate spacer 132 provides mechanical support for gate structure 124, thereby enhancing the mechanical stability of the gate structure and providing electrical isolation between gate structure 124 and other elements of FinFET 100. Gate spacer 132 is typically formed from a single layer of high-dielectric-constant material. In this example, and in other examples described herein, the gate spacer may have a wall width W of approximately 5 nanometers. In one aspect, dummy gate spacers 133 and 135 may have the same structure, may be formed from the same material, and / or may be fabricated concurrently with other gate elements to simplify the fabrication of FinFET 100. In another aspect, the dummy gate is filled with a dielectric material to serve as an isolation channel.

[0033] Some aspects of this disclosure were achieved with the understanding that using a single layer of high-dielectric-constant material as the gate spacer may increase parasitic capacitance, which degrades transistor performance by increasing power consumption and reducing transistor switching speed. Here, a parasitic capacitance 134 (shown schematically as a capacitor) is formed between the metallization structure 106 and the gate contact 126. Similarly, a parasitic capacitance 136 is formed between the metallization structure 102 and the gate contact 126. Figure 1B In the conventional FinFET structure shown, the values ​​of parasitic capacitances 134 and 136 can be quite large.

[0034] Some aspects of this disclosure were made with the understanding that the structure and materials used for the gate spacer 132 can reduce the values ​​of parasitic capacitances 134 and 136, thereby enhancing the performance of the FinFET. Figure 2A and Figure 2B Various elements of a FinFET 200 employing an example multilayer dielectric gate spacer according to aspects of this disclosure are illustrated. Here, Figure 2A It is FinFET200 that passes through Figure 1A The cross-sectional view shown is of section X1-X1'. Figure 2B Is it through Figure 1A The cross-sectional view shown is of section X2-X2'.

[0035] In this example, the FinFET 200 is configured to receive bias and control signals via metallization structures 202, 204, and 206. In one aspect, metallization structures 202 and 206 may be formed of cobalt, manganese, or tungsten, and metallization structure 204 may be formed of tungsten. Metallization structures 202 and 206 extend through interlayer dielectric 208 to contact epitaxial structures 210 and 212, which are disposed on opposite sides of a doped channel 214 and form the S / D structure of the FinFET 200. In one aspect, epitaxial structures 210 and 212 may be formed of eSiGe and / or eSi material. The doped channel 214 is defined on its lateral sides by dummy gate structures 216 and 218, and below it by a substrate structure 220 consisting of a layer 222 covering a substrate 223. In one aspect, layer 222 may be a doped well with doping (e.g., n- or p-doped), the doping depending on the doping used for doping channel 214. Alternatively or additionally, layer 222 may comprise silicon-on-insulator (SiO) and / or buried oxide (BOX) layers.

[0036] The FinFET 200 includes a gate structure 224 covering a doped channel 214. In one aspect, the gate structure 224 includes a gate contact 226 defined externally by a work function metal layer 228. The work function metal layer 228 is then externally defined by a gate dielectric layer 230, which is typically formed of a high dielectric constant material.

[0037] In this example, gate structure 224 is associated with a corresponding gate spacer 232. Unlike conventional gate spacers, gate spacer 232 is formed as a multilayer dielectric structure. In one aspect, gate spacer 232 includes an inner wall 234 disposed adjacent to gate structure 224 (shown in this example as adjacent to gate dielectric layer 230). In another aspect, inner wall 234 is formed of a high-dielectric-constant material. Gate spacer 232 also includes an outer wall 236 laterally spaced from inner wall 234 and also formed of a high-dielectric-constant material, which may be the same as or different from the dielectric material used for inner wall 234. Furthermore, gate spacer 232 includes a low-dielectric-constant material 238 disposed between inner wall 234 and outer wall 236. In one aspect, inner wall 234 and outer wall 236 may be formed of a high-dielectric-constant material such as silicon nitride (SiN). The low-dielectric-constant material 238 can be a low-dielectric-constant material such as silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), a gap, or any combination thereof. In one aspect, the low-dielectric-constant material 238 is formed as a monolayer extending from the inner surface of the inner wall 234 and the inner surface of the outer wall 236. The FinFET 200 may also include dummy gate spacers 246 and 248 having a multilayer dielectric structure similar to that of the gate spacer 232.

[0038] The total dielectric constant of gate spacer 232 is lower than that of conventional gate spacers typically used in FinFETs (e.g., Figure 1A The dielectric constant of the gate spacer 132 shown. Therefore, the parasitic capacitances 242 and 244 are significantly smaller than the parasitic capacitances associated with conventional gate spacers (e.g., ...). Figure 1B The parasitic capacitances 136 and 134 are shown in the diagram. Therefore, the performance of the FinFET 200 is improved by reducing power consumption and increasing switching speed.

[0039] Figure 2B It is an example of FinFET 200 passing through Figure 1A The diagram shows a cross-sectional view along section X2-X2'. In this region, layer 222 of substrate structure 220 can provide shallow trench isolation (STI), which electrically isolates individual transistors, such as FinFET 200, from other active components within the IC. In one aspect, the STI process may involve etching shallow trenches into substrate 223 and then filling the shallow trenches with an insulating material, such as silicon dioxide (SiO2).

[0040] Figure 3A and Figure 3B Various elements of a FinFET 300 employing an example multilayer dielectric gate spacer according to aspects of this disclosure are illustrated. Here, Figure 3A It is FinFET 300 that passes through Figure 1A The cross-sectional view shown is of section X1-X1'. Figure 3B Is it through Figure 1A The cross-sectional view shown is of section X2-X2'.

[0041] In this example, the FinFET 300 is configured to receive bias and control signals via metallization structures 302, 304, and 306. In one aspect, metallization structures 302 and 306 may be formed of cobalt, manganese, or tungsten, and metallization structure 304 may be formed of tungsten. Metallization structures 302 and 306 extend through interlayer dielectric 308 to contact epitaxial structures 310 and 312, which are disposed on opposite sides of the doped channel 214 and form the S / D structure of the FinFET 300. In one aspect, epitaxial structures 310 and 312 may be formed of eSiGe and / or eSi material. The doped channel 314 is defined on its lateral sides by dummy gate structures 316 and 318, and below it by a substrate structure 320 consisting of a layer 322 covering a substrate 323. In one aspect, layer 322 may be a doped well with doping (e.g., n- or p-doped), the doping depending on the doping used for doping channel 314. Alternatively or additionally, layer 322 may comprise SiO2 and / or BOX layers.

[0042] The FinFET 300 includes a gate structure 324 covering a doped channel 314. In one aspect, the gate structure 324 includes a gate contact 326 externally defined by a work function metal layer 328. The work function metal layer 328 is then externally defined by a gate dielectric layer 330, which is typically formed of a high dielectric constant material.

[0043] In this example, gate structure 324 is associated with a corresponding gate spacer 332. In one aspect, gate spacer 332 includes an inner wall 334 disposed adjacent to the corresponding gate structure 324 (shown in this example as adjacent to gate dielectric layer 330). In another aspect, the inner wall 334 is formed of a high-dielectric-constant material. Gate spacer 332 also includes an outer wall 336 laterally spaced from the inner wall 334 and also formed of a high-dielectric-constant material, which may be the same as or different from the dielectric material used for the inner wall 334. Furthermore, gate spacer 332 includes a low-dielectric-constant material 338 disposed between the inner wall 334 and the outer wall 336. According to certain aspects of this disclosure, gate spacer 332 also includes an upper wall 350 formed of a high-dielectric-constant material, which covers the low-dielectric-constant material 338 extending between the inner wall 334 and the outer wall 336. Additionally, the gate spacer 332 includes a lower wall 352 formed of a high-dielectric-constant material beneath a low-dielectric-constant material 338, the lower wall extending between the inner wall 334 and the outer wall 336. In one aspect, the inner wall 334, outer wall 336, upper wall 350, and lower wall 352 may be formed of the same or different dielectric materials. In another aspect, walls 334, 336, 350, and 352 may be formed of a high-dielectric-constant material such as silicon nitride (SiN). The low-dielectric-constant material 338 may be a low-dielectric-constant material such as silicon dioxide (SiO2), a gap, or any combination thereof. In another aspect, the low-dielectric-constant material 338 is formed as a monolayer extending from the inner surface of the inner wall 334 and the inner surface of the outer wall 336. The FinFET 300 may also include dummy gate spacers 346 and 348 having a multilayer dielectric structure similar to that of the gate spacer 332 to simplify the fabrication of the FinFET 300.

[0044] The overall dielectric constant of gate spacer 332 is lower than that of conventional gate spacers typically used in FinFETs (e.g., Figure 1A The dielectric constant of the gate spacer 132 shown. Therefore, the parasitic capacitances 342 and 344 are significantly smaller, and the parasitic capacitances are associated with conventional gate spacers (e.g., Figure 1B The parasitic capacitances 136 and 134 are shown in the diagram. Therefore, the performance of the FinFET 300 is improved by reducing power consumption and increasing switching speed.

[0045] Figure 3B It is an example of FinFET 300 passing through Figure 1A The cross-sectional view shown is section X2-X2'. In this region, layer 322 of substrate structure 320 can provide STI, which electrically isolates individual transistors, such as FinFET 300, from other active components within the IC. In one aspect, the STI process may involve etching shallow trenches into substrate 323 and then filling the shallow trenches with an insulating material, such as silicon dioxide (SiO2).

[0046] Figure 4A and Figure 4B Various elements of a gate-all-around (GAA) transistor 400 according to various aspects of this disclosure are illustrated. Here, Figure 4A This is a top view of the GAA transistor 400, and Figure 4B This is a cross-sectional view of the GAA transistor 400 through axis X3-X3'. In this example, the GAA transistor 400 is configured to receive bias and control signals through metallization structures 402, 404, and 406. In one aspect, metallization structures 402 and 406 may be formed of cobalt, manganese, or tungsten, and metallization structure 404 may be formed of tungsten. Metallization structures 402 and 406 extend through interlayer dielectric 408 to contact epitaxial structures 410 and 412, which are disposed on opposite sides of a plurality of doped channels 414 and form the S / D structure of the GAA transistor 400. In one aspect, the doped channels 414 may be formed of nanosheets (e.g., in...). Figure 4B (As shown in the configuration). However, it should be understood that similar doped channels for GAA transistors can be formed by forked plates. In one aspect, epitaxial structures 410 and 412 can be formed from eSiGe and / or eSi materials.

[0047] The GAA transistor 400 includes at least one gate structure associated with each doped channel in the doped channel 414. In this example, the GAA transistor 400 includes an external gate structure 418 and a plurality of internal gate structures 420. In one aspect, the external gate structure 418 includes a gate contact 422 defined externally by a work function metal layer 424. The work function metal layer 424 is then externally defined by a gate dielectric layer 426, which is typically formed of a high dielectric constant material.

[0048] exist Figure 4B In the example shown, the external gate structure 418 is associated with a corresponding external gate spacer 428. The external gate spacer 428 is typically formed of a single layer of high-dielectric-constant material. On the other hand, a dummy gate spacer (not shown) with the same structure and formed of the same material can be produced during the manufacture of the GAA transistor 400.

[0049] In one aspect, each internal gate structure 420 includes an inner layer of work function metal 430 surrounded by a gate dielectric layer 432. Each internal gate structure 420 is associated with a corresponding internal gate spacer 434. The internal gate spacer 434 is typically formed of a monolayer of high dielectric constant material.

[0050] The aforementioned element of the GAA transistor 400 covers the substrate structure 436. In this example, the substrate structure 436 includes a layer 438 that includes a doped well 440 and an STI structure 442. Layer 438 covers the substrate layer 444.

[0051] Figure 5A and Figure 5B Various elements of a GAA transistor 500, including a multilayer dielectric structure for internal and external gate spacers, are illustrated according to various aspects of this disclosure. Figure 5A It is GAA transistor 500 passing through Figure 4A The cross-sectional view shown is of section X3-X3'. Figure 5B Is it through Figure 4A The cross-sectional view shown is of section X4-X4'.

[0052] In this example, the GAA transistor 500 is configured to receive bias and control signals via metallization structures 502, 504, and 506. In one aspect, metallization structures 502 and 506 may be formed of cobalt, manganese, or tungsten, and metallization structure 504 may be formed of tungsten. Metallization structures 502 and 506 extend through interlayer dielectric 508 to contact epitaxial structures 510 and 512, which are disposed on opposite sides of a plurality of doped channels 514 and form the S / D structure of the GAA transistor 500. In one aspect, the doped channels 514 may be formed of nanosheets (e.g., as in...). Figure 5B (As shown in the configuration). However, it should be understood that similar doped channels for such GAA transistors can also be formed by forked plates. In one aspect, the epitaxial structures 510 and 512 can be formed from eSiGe and / or eSi materials.

[0053] The GAA transistor 500 includes at least one gate structure associated with each doped channel in the doped channel 514. In this example, the GAA transistor 500 includes an external gate structure 518 and a plurality of internal gate structures 520. In one aspect, the external gate structure 518 includes a gate contact 522 defined externally by a work function metal layer 524. The work function metal layer 524 is then externally defined by a gate dielectric layer 526, which is typically formed of a high dielectric constant material.

[0054] exist Figure 5AIn the example shown, the external gate structure 518 is associated with a corresponding external gate spacer 528. Unlike conventional external gate spacers, the external gate spacer 528 is formed as a multilayer dielectric structure. In one aspect, the external gate spacer 528 includes an inner wall 534 disposed adjacent to the external gate structure 518 (shown in this example as adjacent to the gate dielectric layer 526). In another aspect, the inner wall 534 is formed of a high-dielectric-constant material. The external gate spacer 528 also includes an outer wall 536 laterally spaced from the inner wall 534 and also formed of a high-dielectric-constant material, which may be the same as or different from the dielectric material used for the inner wall 534. Furthermore, the external gate spacer 528 includes a low-dielectric-constant material 538 disposed between the inner wall 534 and the outer wall 536. In one aspect, the inner wall 534 and the outer wall 536 may be formed of a high-dielectric-constant material such as SiN. The low-dielectric-constant material 538 can be a low-dielectric-constant material such as SiO2, a gap, or any combination thereof. In one aspect, the low-dielectric-constant material 538 is formed as a monolayer extending from the inner surface of the inner wall 534 and the inner surface of the outer wall 536. The GAA transistor 500 may also include a dummy gate spacer (not shown) having a multilayer dielectric structure similar to that of the outer gate spacer 528.

[0055] In one aspect, each internal gate structure 520 includes an inner layer of work function metal 530 surrounded by a gate dielectric layer 532. Each internal gate structure 520 is associated with a corresponding internal gate spacer 540. Unlike conventional internal gate spacers, the internal gate spacers 540 are formed as multilayer dielectric structures. In one aspect, each internal gate spacer 540 includes an inner wall 542 disposed adjacent to the corresponding internal gate structure 520 (shown in this example as immediately adjacent to the gate dielectric layer 532). In one aspect, the inner wall 542 is formed of a high dielectric constant material. Each internal gate spacer 540 also includes an outer wall 544 laterally spaced from the inner wall 542 and also formed of a high dielectric constant material, which may be the same as or different from the dielectric material used for the inner wall 542. Furthermore, each internal gate spacer 540 includes a low dielectric constant material 546 disposed between the inner wall 542 and the outer wall 544. In one aspect, the inner wall 542 and the outer wall 544 may be formed of a high-dielectric-constant material such as silicon nitride (SiN). The low-dielectric-constant material 546 may be a low-dielectric-constant material such as silicon dioxide (SiO2), a gas gap, or any combination thereof. In another aspect, the low-dielectric-constant material 546 of each inner gate spacer 540 is formed as a monolayer extending from the inner surface of the inner wall 542 of the corresponding inner gate spacer 540 and the inner surface of the outer wall 544 of the corresponding inner gate spacer 540.

[0056] The aforementioned elements of the GAA transistor 500 cover the substrate structure 550. In this example, the substrate structure 550 includes a layer 552 that includes a doped well 554 and an STI structure 556. Layer 552 covers the substrate layer 558. It should be understood that the substrate structure 550 will vary depending on the starting elements used in the manufacturing process (e.g., body, SOI, etc.).

[0057] Figure 6A and Figure 6B Various elements of a GAA transistor 600, including a multilayer dielectric structure for internal and external gate spacers, are illustrated according to various aspects of this disclosure. Figure 6A It is GAA transistor 600 passing through Figure 4A The cross-sectional view shown is of section X3-X3'. Figure 6B Is it through Figure 4A The cross-sectional view shown is of section X4-X4'.

[0058] In this example, the GAA transistor 600 is configured to receive bias and control signals via metallization structures 602, 604, and 606. In one aspect, metallization structures 602 and 606 may be formed of cobalt, manganese, or tungsten, and metallization structure 604 may be formed of tungsten. Metallization structures 602 and 606 extend through interlayer dielectric 608 to contact epitaxial structures 610 and 612, which are disposed on opposite sides of a plurality of doped channels 614 and form the S / D structure of the GAA transistor 600. In one aspect, the doped channels 614 may be formed of nanosheets (e.g., in...). Figure 6B (As shown in the configuration). However, it should be understood that similar doped channels for such GAA transistors can also be formed by forked plates. In one aspect, the epitaxial structures 610 and 612 can be formed from eSiGe and / or eSi materials.

[0059] The GAA transistor 600 includes at least one gate structure associated with each doped channel in the doped channel 614. In this example, the GAA transistor 600 includes an external gate structure 618 and a plurality of internal gate structures 620. In one aspect, the external gate structure 618 includes a gate contact 622 defined externally by a work function metal layer 624. The work function metal layer 624 is then externally defined by a gate dielectric layer 626, which is typically formed of a high dielectric constant material.

[0060] exist Figure 6AIn the example shown, the external gate structure 618 is associated with a corresponding external gate spacer 628. Unlike conventional external gate spacers, the external gate spacer 628 is formed as a multilayer dielectric structure. In one aspect, the external gate spacer 628 includes an inner wall 634 disposed adjacent to the external gate structure 618 (shown in this example as adjacent to the gate dielectric layer 626). In another aspect, the inner wall 634 is formed of a high-dielectric-constant material. The external gate spacer 628 also includes an outer wall 636 laterally spaced from the inner wall 634 and also formed of a high-dielectric-constant material, which may be the same as or a different dielectric material used for the inner wall 634. Furthermore, the external gate spacer 628 includes a low-dielectric-constant material 638 disposed between the inner wall 634 and the outer wall 636. According to certain aspects of this disclosure, the external gate spacer 628 further includes an upper wall 670 formed of a high-dielectric-constant material, which covers the low-dielectric-constant material 638 and extends between the inner wall 634 and the outer wall 636. Additionally, the external gate spacer 628 includes a lower wall 672 formed of a high-dielectric-constant material below the low-dielectric-constant material 638, which extends between the inner wall 634 and the outer wall 636. In one aspect, the inner wall 634, outer wall 636, upper wall 670, and lower wall 672 may be formed of the same or different high-dielectric-constant materials. In another aspect, walls 634, 636, 670, and 672 may be formed of a high-dielectric-constant material such as SiN. The low-dielectric-constant material 638 may be a low-dielectric-constant material such as SiO2, a gap, or any combination thereof. In one aspect, the low-dielectric-constant material 638 is formed as a monolayer extending from the inner surface of the inner wall 634 and the inner surface of the outer wall 636. The GAA transistor 600 may also include a dummy gate spacer (not shown) having a multilayer dielectric structure similar to that of the external gate spacer 628.

[0061] In one aspect, each internal gate structure 620 includes an inner layer of work function metal 630 surrounded by a gate dielectric layer 632. Each internal gate structure 620 is associated with a corresponding internal gate spacer 640. Unlike conventional internal gate spacers, the internal gate spacers 640 are formed as multilayer dielectric structures. In one aspect, each internal gate spacer 640 includes an inner wall 642 disposed adjacent to the corresponding internal gate structure 620 (shown in this example as immediately adjacent to the gate dielectric layer 632). In one aspect, the inner wall 642 is formed of a fifth high-dielectric-constant material. Each internal gate spacer 640 also includes an outer wall 644 laterally spaced from the inner wall 642 and also formed of a high-dielectric-constant material, which may be the same as or different from the dielectric material used for the inner wall 642. Furthermore, each internal gate spacer 640 includes a low-dielectric-constant material 646 disposed between the inner wall 642 and the outer wall 644. According to certain aspects of this disclosure, each internal gate spacer 640 further includes an upper wall 674 formed of a high-dielectric-constant material, which covers a low-dielectric-constant material 646 extending between the inner wall 642 and the outer wall 644. Additionally, each internal gate spacer 640 includes a lower wall 676 formed of a high-dielectric-constant material below the low-dielectric-constant material 646, which extends between the inner wall 642 and the outer wall 636. In one aspect, the inner wall 642, outer wall 644, upper wall 674, and lower wall 676 may be formed of the same or different high-dielectric-constant materials. In another aspect, walls 642, 644, 674, and 676 may be formed of a high-dielectric-constant material such as SiN. The low-dielectric-constant material 646 may be a low-dielectric-constant material such as SiO2, a gap, or any combination thereof. On one hand, the low dielectric constant material 646 is formed as a monolayer extending from the inner surface of the inner wall 642 and the inner surface of the outer wall 644.

[0062] The aforementioned elements of the GAA transistor 600 cover a substrate structure 660. In this example, the substrate structure 660 includes a layer 662 that includes a doped well 664 and an STI structure 666. Layer 662 covers a substrate layer 668. It should be understood that the substrate structure 660 will vary depending on the starting elements used in the manufacturing process (e.g., body, SOI, etc.).

[0063] Figures 7A to 7I An example process for manufacturing FinFETs according to various aspects of this disclosure is illustrated. In this example process, the fabrication is carried out in... Figure 7AThe process begins with the formation of P and N doped layers 704 for the device on an SOI substrate 702. After patterning, a high-k dielectric layer (e.g., SiN) 706 is deposited. The resulting structure is then patterned to form fins, followed by the deposition of an STI oxide that undergoes chemical mechanical polishing (CMP). The oxide is then recessed to form the STI structure, and the high-k dielectric layer is removed.

[0064] exist Figure 7B In the process, a dummy polysilicon layer and a hard mask layer are deposited, and then the dummy polysilicon layer and the hard mask layer are patterned to form a gate element 708, which is ultimately used to form a gate structure (center gate element) and a dummy gate (outer gate element).

[0065] exist Figure 7C In the process, a thin SiN layer (e.g., 1 nm to 2 nm) is deposited, and then the thin SiN layer is etched back to form the inner wall 710, which will eventually become part of the gate spacer.

[0066] exist Figure 7D In the process, a thin layer of low-dielectric-constant material (e.g., 2 nm to 5 nm of SiO2) is deposited. Then, the layer is etched back and recessed to form part of the low-dielectric-constant layer 712 that will eventually become the gate spacer.

[0067] exist Figure 7E In this process, a thin layer of high-k dielectric material (e.g., 1 nm to 3 nm SiN) is deposited, and then the thin layer of high-k dielectric material is etched back to form a portion that will eventually become the outer wall 714 of the gate spacer. At this point, the gate spacer (both the actual gate spacer and the dummy gate spacer) has been formed as a multilayer dielectric gate spacer. The source and drain regions of the fin are recessed and an epitaxial structure 716 (e.g., an S / D structure) is formed (e.g., eSiGe for P-channel metal-oxide-semiconductor devices or eSi for n-channel metal-oxide-semiconductor devices). If the air gap is used as a low-k dielectric material, then in Figure 7D In the process steps shown, the material deposited for the intermediate layer can be a sacrificial layer (e.g., an air gap membrane) that is removed (e.g., using a thermal process).

[0068] exist Figure 7F In the process, interlayer dielectric oxide 718 is deposited and subjected to CMP process.

[0069] exist Figure 7G In the process, the dummy polysilicon gate region is removed. The area left by removing the dummy polysilicon gate region is filled with a metal gate contact 720, a work function metal 722, and a gate dielectric 724 to form the gate structure of a FinFET.

[0070] exist Figure 7HIn the process, material is removed from the dummy gate 726.

[0071] exist Figure 7I In this process, FinFET fabrication is completed. To this end, another interlayer dielectric 728 is deposited and patterned to open regions for depositing the metallization structure 730, which serves as a contact for the epitaxial structure 716. Similarly, the interlayer dielectric 728 is patterned to open regions for the metal structure 732, which provides an electrical path to the gate contacts of the gate structure. A CMP process can be performed after each metallization layer forming the metal structure.

[0072] Figures 8A to 8R An example process for manufacturing GAA transistors according to various aspects of this disclosure is illustrated. In this example process, the transistor is manufactured in... Figure 8A Starting at point 802, a doped well 804 is implanted in a substrate 802. A multilayer structure 806, consisting of alternating layers of epitaxial material (e.g., SiGe / Si layers, each having a thickness of 8 nm to 10 nm), is deposited over the doped well 804. A high-dielectric-constant material 808 (e.g., SiN) is deposited over the top epitaxial layer.

[0073] exist Figure 8B In the patterned active region of the device within the doped well 804, an STI oxide layer is deposited, followed by a CMP process. The STI oxide is then recessed to form the STI structure 810, and the hard mask (not shown) used in the patterning process is removed.

[0074] exist Figure 8C In the process, a polysilicon layer and a patterned hard mask are deposited and etched to form the gate element 812.

[0075] exist Figure 8D In this process, a thin layer of high dielectric constant material (e.g., 1 nm to 2 nm SiN) is deposited over the polysilicon layer and etched back to the appropriate thickness to form part of the inner wall 814 that will eventually become the external gate spacer.

[0076] exist Figure 8E In this process, a thin layer of low-dielectric-constant material (e.g., an oxide of 2 nm to 3 nm) is deposited and etched back to form part of the low-dielectric-constant material 816 that will eventually become the external gate spacer.

[0077] exist Figure 8F In this process, a thin layer of high dielectric constant material (e.g., 1 nm to 2 nm SiN) is deposited and etched back to form part of the outer wall 818 that will eventually become the external gate spacer.

[0078] Figure 8G and Figure 8H The optional treatment of the external gate spacer is shown in the diagram. For example... Figure 8G and Figure 8H As shown, an optional lower wall 820 of high dielectric constant material can be deposited and etched back before the operations for forming the inner wall 814, outer wall 818, and low dielectric constant material 816 of the external gate spacer.

[0079] exist Figure 8I In the initial internal structure processing, the internal gate structure, internal gate spacers, and doped channels are formed. During the initial internal structure processing, the nanosheets are cut to the same width as the external gate spacers. Furthermore, grooves are formed in the SiGe dummy nanosheets using an etching operation, within which the internal gate spacers will be formed. A thin layer of high-dielectric-constant material (e.g., approximately 1 nm to 2 nm of SiN) is deposited and etched back to form a portion of the inner wall 821 that will ultimately become the internal gate spacers.

[0080] exist Figure 8J In this process, a thin layer of low-dielectric-constant material (e.g., a 1 nm to 2 nm oxide layer) is deposited and etched back to form part of the low-dielectric-constant material 822 that will eventually become the internal gate spacer.

[0081] exist Figure 8K In this process, a thin layer of high-k dielectric material (e.g., 1 nm to 2 nm SiN) is deposited and etched back to form a portion of the outer wall 824 that will eventually become the internal gate spacer. If a low-k dielectric material will become the air gap, a dummy air gap film can be deposited to replace the low-k dielectric material. The dummy air gap film can then be removed using, for example, a thermal process to leave the air gap as an intermediate low-k dielectric layer for the internal gate spacer.

[0082] On one hand, the dielectric material used to form the inner wall can be deposited to fill the grooves of the inner gate spacers and etched back to leave not only the inner wall 821, but also optional upper walls 823 and lower walls 825 of high dielectric constant material, such as... Figures 8L to 8M As shown. In one aspect, the inner wall 821, optional upper wall 823, and optional lower wall 825 can be formed of SiN and have a thickness of 1 nm to 2 nm. After forming the inner wall 821, upper wall 823, and lower wall 825 of the internal gate spacer, a low-dielectric-constant material 822 of the internal gate spacer can be deposited and etched back. Figure 8M Then, a high-dielectric-constant material is deposited and etched back to ultimately form the outer wall 824 of the internal gate spacer. Figure 8N ).

[0083] exist Figure 8O In the process, a thin oxide layer is deposited and etched (optional) to expose the nanosheets forming the doped channels. An epitaxial structure 826 forming the S / D structure is fabricated (e.g., using eSiGe to fabricate a PMOS device or using eSi to fabricate an NMOS device).

[0084] exist Figure 8P In the process, an interlayer dielectric ILD oxide film 828 is deposited and subjected to a CMP process. Additionally, the sacrificial polysilicon material and a dummy SiGe layer are removed to open up regions that will be used to form the internal and external gate structures.

[0085] exist Figure 8Q In this process, the area left by the removal of sacrificial polysilicon material is filled with work function metal 830 and gate dielectric 832 to form a gate structure. Additionally, metallization 834 for the gate contacts can be deposited and subjected to CMP processing.

[0086] exist Figure 8R In this process, the fabrication of the GAA transistor is completed. To this end, another interlayer dielectric layer 836 is deposited to accumulate the interlayer dielectric, such that this interlayer dielectric extends over the external gate structure. Then, the interlayer dielectric is patterned to open regions for depositing the metallization structure 838, which serves to contact the epitaxial structure 826. Similarly, the interlayer dielectric is patterned to open regions for the metal structure 840, which provides an electrical path to the gate contact 842 of the external gate structure. After each metallization layer forming the metal structure is deposited, a CMP process can be performed.

[0087] Figure 9 This is a flowchart illustrating an example method 900 for manufacturing a FinFET according to various aspects of the present disclosure. At operation 902, a channel structure is formed having a semiconductor channel separating the source and drain of the FinFET. At operation 904, a gate structure is formed covering the semiconductor channel. At operation 906, at least one gate spacer associated with the gate structure is formed, wherein forming the at least one gate spacer includes forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0088] The technical advantage of method 900 is that it forms a FinFET with reduced parasitic capacitance. By reducing parasitic capacitance, the FinFET consumes less power and can operate at higher speeds.

[0089] Figure 10This is a flowchart illustrating an example method 1000 for manufacturing a GAA transistor according to various aspects of the present disclosure. At operation 1002, a plurality of channel structures are formed between the source and drain of the GAA transistor. At operation 1004, a gate structure associated with the plurality of channel structures is formed. At operation 1006, at least one gate spacer associated with the gate structure is formed, wherein forming at least one gate spacer includes forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0090] The technical advantage of method 1000 is that it forms a GAA transistor with reduced parasitic capacitance. By reducing parasitic capacitance, the GAA transistor consumes less power and can operate at a higher speed.

[0091] Figure 11 A cross-sectional view of a package 1100, including a surface mount substrate 1102, an integrated device 1103, and an integrated passive device 1105, is illustrated according to various aspects of this disclosure. The package 1100 may be coupled to a printed circuit board (PCB) 1106 via a plurality of solder interconnects 1110. The PCB 1106 may include at least one board dielectric layer 1160 and a plurality of board interconnects 1162.

[0092] Surface mount substrate 1102 includes at least one dielectric layer 1120 (e.g., a substrate dielectric layer), a plurality of interconnects 1122 (e.g., substrate interconnects), a solder mask layer 1140, and a solder mask layer 1142. Integrated device 1103 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1130. Integrated device 1103 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1132 and a plurality of solder interconnects 1130. Integrated passive device 1105 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1150. Integrated passive device 1105 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1152 and a plurality of solder interconnects 1150.

[0093] The package (e.g., 1100) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 1100) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 1100) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 1100) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0094] Figure 12 An example method 1200 for providing or manufacturing a package including an integrated device having electronic components mounted in a core, according to various aspects of this disclosure, is illustrated. In some specific embodiments, Figure 12 Method 1200 can be used to provide or manufacture the invention described in this disclosure. Figure 11 Package 1100. However, method 1200 can be used to provide or manufacture any package described in this disclosure.

[0095] It should be noted that, according to all aspects of this disclosure, Figure 12 The method may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing packages that include integrated devices having electronic components mounted in a core. In some specific implementations, the order of the processes may be changed or modified.

[0096] The method (at 1205) provides a substrate (e.g., 1102). The substrate 1102 may be supplied by a vendor or manufactured in-house. The substrate 1102 includes at least one dielectric layer 1120 and a plurality of interconnects 1122. The substrate 1102 may include an embedded trace substrate (ETS). In some embodiments, at least one dielectric layer 1120 may include a prepreg layer.

[0097] The method (at 1210) couples at least one integrated device (e.g., 1103) to a first surface of a substrate (e.g., 1102). For example, the integrated device 1103 may be coupled to the substrate 1102 via a plurality of solder interconnects 1132 and a plurality of solder interconnects 1130. The plurality of solder interconnects 1132 may be optional. The plurality of solder interconnects 1130 are coupled to a plurality of interconnects 1122. A solder reflow process may be used to couple the integrated device 1103 to the plurality of interconnects via the plurality of solder interconnects 1130.

[0098] The method (at 1210) also couples at least one integrated passive device (e.g., 1105) to a first surface of a substrate (e.g., 1102). For example, the integrated passive device 1105 can be coupled to the substrate 1102 via a plurality of solder interconnects 1152 and a plurality of solder interconnects 1150. The plurality of solder interconnects 1152 may be optional. The plurality of solder interconnects 1150 are coupled to a plurality of interconnects 1122. A solder reflow process can be used to couple the integrated passive device 1105 to the plurality of interconnects via the plurality of solder interconnects 1150.

[0099] The method (at 1215) couples a plurality of solder interconnects (e.g., 1110) to a second surface of a substrate (e.g., 1102). A solder reflow process can be used to couple the plurality of solder interconnects 1110 to the substrate.

[0100] Figure 13 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1302, laptop computer device 1304, fixed-location terminal device 1306, wearable device 1308, or motor vehicle 1313 may include device 1300 as described herein. For example, device 1300 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 13 The illustrated devices 1302, 1304, 1306, and 1308, as well as vehicle 1313, are merely exemplary. Other electronic devices may also feature device 1300, including but not limited to devices (e.g., electronic devices) comprising the following group: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (such as watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0101] Specific implementation examples are described in the following numbering section: Aspect 1. An electronic device having one or more nonplanar transistors, at least one of the one or more nonplanar transistors comprising: one or more gate structures; and one or more gate spacers, the one or more gate spacers being associated with each of the one or more gate structures, at least one of the one or more gate spacers having a multilayer dielectric structure, the multilayer dielectric structure including an inner wall disposed adjacent to a corresponding gate structure of the one or more gate structures, wherein the inner wall is formed of a first dielectric material; an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0102] Aspect 2. The electronic device according to aspect 1, wherein: the inner wall is disposed adjacent to the gate dielectric layer of the corresponding gate structure.

[0103] Aspect 3. The electronic device according to any one of Aspects 1 to 2, wherein: the first dielectric material and the second dielectric material are the same dielectric material.

[0104] Aspect 4. The electronic device according to any one of Aspects 1 to 3, wherein: the third dielectric material includes an air gap.

[0105] Aspect 5. The electronic device according to any one of Aspects 1 to 4, wherein the one or more gate spacers further comprises: an upper wall formed of a fourth dielectric material, the upper wall formed of the fourth dielectric material covering the third dielectric material and extending between the inner wall and the outer wall; and a lower wall formed of a fifth dielectric material, the lower wall formed of the fifth dielectric material below the third dielectric material and extending between the inner wall and the outer wall.

[0106] Aspect 6. The electronic device according to aspect 5, wherein: the first dielectric material, the second dielectric material, the fourth dielectric material and the fifth dielectric material are the same dielectric material.

[0107] Aspect 7. The electronic device according to any one of Aspects 1 to 6, wherein: the third dielectric material extends from the inner surface of the inner wall and the inner surface of the outer wall.

[0108] Aspect 8. An electronic device according to any one of Aspects 1 to 7, wherein the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communication device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed-location terminal; a tablet computer; a computer; a wearable device; a laptop computer; a server; an Internet of Things (IoT) device; or a device in a motor vehicle.

[0109] Aspect 9. A nonplanar transistor comprising: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one of the gate spacers having a multilayer dielectric structure including an inner wall disposed adjacent to a corresponding gate structure of the one or more gate structures, wherein the inner wall is formed of a first dielectric material; an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0110] Aspect 10. The nonplanar transistor according to aspect 9, wherein: the inner wall is disposed adjacent to the gate dielectric layer of the corresponding gate structure.

[0111] Aspect 11. The nonplanar transistor according to any one of Aspects 9 to 10, wherein: the first dielectric material and the second dielectric material are the same dielectric material.

[0112] Aspect 12. The nonplanar transistor according to any one of Aspects 9 to 11, wherein: the third dielectric material includes an air gap.

[0113] Aspect 13. The nonplanar transistor according to any one of Aspects 9 to 12, wherein the one or more gate spacers further comprises: an upper wall formed of a fourth dielectric material, the upper wall formed of the fourth dielectric material covering the third dielectric material and extending between the inner wall and the outer wall; and a lower wall formed of a fifth dielectric material, the lower wall formed of the fifth dielectric material below the third dielectric material and extending between the inner wall and the outer wall.

[0114] Aspect 14. The nonplanar transistor according to aspect 13, wherein: the first dielectric material, the second dielectric material, the fourth dielectric material and the fifth dielectric material are the same dielectric material.

[0115] Aspect 15. The nonplanar transistor according to any one of Aspects 9 to 14, wherein: the third dielectric material extends from the inner surface of the inner wall and the inner surface of the outer wall.

[0116] Aspect 16. A method of forming a fin field-effect transistor (FinFET), the method comprising: forming a channel structure having a semiconductor channel between a source and a drain of the FinFET; forming a gate structure covering the semiconductor channel; and forming at least one gate spacer associated with the gate structure, wherein forming the at least one gate spacer includes forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0117] Aspect 17. A method of forming a gate all-around (GAA) transistor, the method comprising: forming a plurality of channel structures between a source and a drain of the GAA transistor; forming a gate structure associated with the plurality of channel structures; and forming at least one gate spacer associated with the gate structure, wherein forming the at least one gate spacer comprises forming an inner wall adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material; forming an outer wall spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material; and forming a third dielectric material disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than the dielectric constant of the first dielectric material and lower than the dielectric constant of the second dielectric material.

[0118] Aspect 18. The method according to aspect 17, wherein: the first dielectric material and the second dielectric material are the same dielectric material.

[0119] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0120] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulation” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10% of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0121] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0122] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0123] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features in the example aspects than are explicitly mentioned in each aspect. Rather, the various aspects of this disclosure may include fewer features than those in the individual example aspects disclosed. Therefore, the following aspects should be regarded accordingly as incorporated into the description, where each aspect can be considered as a separate example on its own. Although each dependent aspect may refer in the aspect to a particular combination with one aspect of other aspects, the aspect of the dependent aspect is not limited to that particular combination. It should be understood that other example aspects may also include combinations of the subject matter of a dependent aspect with any other dependent or independent aspect, or any feature combined with other dependent and independent aspects. The various aspects disclosed herein expressly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of an aspect may be included in any other independent aspect, even if that aspect does not directly depend on the independent aspect.

[0124] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. An electronic device having one or more non-planar transistors, wherein at least one of the one or more non-planar transistors comprises: One or more gate structures; and One or more gate spacers, each gate spacer being associated with each of the one or more gate structures, wherein at least one of the gate spacers has a multilayer dielectric structure, the multilayer dielectric structure comprising... The inner wall, which is disposed adjacent to a corresponding gate structure in one or more gate structures, is formed of a first dielectric material. An outer wall, spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material, and A third dielectric material is disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than that of the first dielectric material and lower than that of the second dielectric material.

2. The electronic device according to claim 1, wherein: The inner wall is disposed adjacent to the gate dielectric layer of the corresponding gate structure.

3. The electronic device according to claim 1, wherein: The first dielectric material and the second dielectric material are the same dielectric material.

4. The electronic device according to claim 1, wherein: The third dielectric material includes an air gap.

5. The electronic device of claim 1, wherein the one or more gate spacers further comprises: An upper wall formed of a fourth dielectric material, the upper wall formed of the fourth dielectric material covering the third dielectric material and extending between the inner wall and the outer wall; and A lower wall formed of a fifth dielectric material extends below the third dielectric material and between the inner wall and the outer wall.

6. The electronic device according to claim 5, wherein: The first dielectric material, the second dielectric material, the fourth dielectric material, and the fifth dielectric material are the same dielectric material.

7. The electronic device according to claim 1, wherein: The third dielectric material extends from the inner surface of the inner wall and the inner surface of the outer wall.

8. The electronic device of claim 1, wherein the electronic device comprises at least one of the following: Music player; Video player; Entertainment section; Navigation equipment; Communication equipment; mobile device; Mobile phones; Smartphone; Personal digital assistant; Fixed-location terminal; Tablet computers, computers; Wearable devices; Laptop computers; server; Internet of Things (IoT) devices; or Equipment in motor vehicles.

9. A nonplanar transistor, the nonplanar transistor comprising: One or more gate structures; and One or more gate spacers, each gate spacer being associated with each of the one or more gate structures, wherein at least one of the gate spacers has a multilayer dielectric structure, the multilayer dielectric structure comprising... The inner wall, which is disposed adjacent to a corresponding gate structure in one or more gate structures, is formed of a first dielectric material. An outer wall, spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material, and A third dielectric material is disposed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than that of the first dielectric material and lower than that of the second dielectric material.

10. The nonplanar transistor of claim 9, wherein: The inner wall is disposed adjacent to the gate dielectric layer of the corresponding gate structure.

11. The nonplanar transistor of claim 9, wherein: The first dielectric material and the second dielectric material are the same dielectric material.

12. The nonplanar transistor according to claim 9, wherein: The third dielectric material includes an air gap.

13. The nonplanar transistor of claim 9, wherein the one or more gate spacers further comprise: An upper wall formed of a fourth dielectric material, the upper wall formed of the fourth dielectric material covering the third dielectric material and extending between the inner wall and the outer wall; and A lower wall formed of a fifth dielectric material extends below the third dielectric material and between the inner wall and the outer wall.

14. The nonplanar transistor of claim 13, wherein: The first dielectric material, the second dielectric material, the fourth dielectric material, and the fifth dielectric material are the same dielectric material.

15. The nonplanar transistor according to claim 9, wherein: The third dielectric material extends from the inner surface of the inner wall and the inner surface of the outer wall.

16. A method for forming a fin field-effect transistor (FinFET), the method comprising: A channel structure with a semiconductor channel is formed between the source and drain of the FinFET; A gate structure covering the semiconductor channel is formed; as well as Forming at least one gate spacer associated with the gate structure, wherein forming the at least one gate spacer includes An inner wall is formed adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material. An outer wall is formed, spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material, and A third dielectric material is formed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than that of the first dielectric material and lower than that of the second dielectric material.

17. A method of forming a gate-all-around (GAA) transistor, the method comprising: Multiple channel structures are formed between the source and drain of the GAA transistor; A gate structure associated with the plurality of channel structures is formed; as well as Forming at least one gate spacer associated with the gate structure, wherein forming the at least one gate spacer includes An inner wall is formed adjacent to the gate structure, wherein the inner wall is formed of a first dielectric material. An outer wall is formed, spaced apart from the inner wall, wherein the outer wall is formed of a second dielectric material, and A third dielectric material is formed between the inner wall and the outer wall, wherein the dielectric constant of the third dielectric material is lower than that of the first dielectric material and lower than that of the second dielectric material.

18. The method of claim 17, wherein: The first dielectric material and the second dielectric material are the same dielectric material.

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