Chip test system and test method

Abstract

The invention provides a chip test system comprising a test board used for installing a to-be-tested chip; the data processing platform board is connected with the test board and is connected with the chip to be tested through the test board so as to send first test data to the chip to be tested or receive second test data sent by the chip to be tested; the standard measuring instrument assembly is connected with the test board and is connected with the chip to be tested through the test board so as to assist in completing the test of the chip to be tested; and the upper computer is connected with the data processing platform plate and the standard measuring instrument assembly so as to send a test instruction to the data processing platform plate and receive and analyze second test data sent by the data processing platform plate or measurement data sent by the standard measuring instrument assembly so as to obtain a test result of the to-be-tested chip. According to the invention, the test automation of the to-be-tested chip is realized, and the chip test efficiency and precision can be remarkably improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing system and testing method. Background Technology

[0002] Currently, common ADC / DAC (digital-to-analog converter chip) testing solutions are mainly divided into two categories. One category is application-specific integrated circuit testing systems (such as ATE; Automatic Test Equipment). These systems have high integration and fast testing speed, but the equipment cost is expensive and the testing flexibility is poor, making it difficult to meet testing requirements. The other category is testing platforms built based on discrete instruments. Although this type of solution has a lower cost, it usually relies on manual operation and data recording, and the testing process is not standardized, resulting in low efficiency. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a chip testing system and testing method to solve at least one of the technical problems involved in the background art.

[0004] To achieve the above objectives, this application provides a chip testing system, comprising: Test board, used to mount the chip under test; A data processing platform board is connected to the test board and connected to the chip under test through the test board to send first test data to the chip under test or receive second test data sent by the chip under test. A standard measuring instrument assembly is connected to the test board, and the test board is connected to the chip under test to assist in completing the test of the chip under test; The host computer is connected to the data processing platform board and the standard measuring instrument assembly to send test commands to the data processing platform board and receive and analyze the second test data sent by the data processing platform board or the measurement data sent by the standard measuring instrument assembly to obtain the test results of the chip under test.

[0005] Furthermore, the standard measurement instrument assembly includes an excitation signal source, a spectrum analyzer, and a multimeter. The excitation signal source is used to send an excitation signal to the chip under test (DUT), the spectrum analyzer is used to analyze the output signal spectrum of the DUT, and the multimeter is used to measure the static parameters of the DUT.

[0006] Furthermore, the data processing platform board includes a first FMC interface, an FPGA chip, and a second FMC interface connected in sequence. The first FMC interface is used to connect to the test board, and the second FMC interface is used to connect to the host computer.

[0007] Furthermore, the test board includes a connected chip mounting socket and a third FMC interface. The chip mounting socket is used to mount the chip under test. The third FMC interface is connected to the first FMC interface. The test board is connected to the data processing platform through the first FMC interface and the third FMC interface.

[0008] Furthermore, the test board also includes a clock module, which is connected to the chip mounting base and the third FMC interface to provide a synchronous clock signal to the chip under test and the data processing platform.

[0009] Furthermore, the test board also includes a power management module, which is connected to the third FMC interface, the clock module, and the chip mounting base. The power management module obtains power from the data processing platform through the third FMC interface to provide power to the chip under test connected to the clock module and the chip mounting base.

[0010] Furthermore, the host computer includes an interface display module, which is used to display the settings window of the chip under test, the instrument connection status, and the test results of the chip under test.

[0011] Furthermore, the host computer also includes a network communication module, which is used to communicate with the data processing platform to send test commands to the chip under test through the data management platform, send first test data to the chip under test, and receive second test data sent by the chip under test.

[0012] Furthermore, the host computer also includes a standard measuring instrument control module, which is connected to the standard measuring instrument assembly and used to control the standard measuring instruments connected to the standard measuring instrument assembly. The standard measuring instrument control module is also connected to the network communication module to control the standard measuring instruments connected to the standard measuring instrument assembly based on the network communication module.

[0013] Furthermore, the host computer also includes an ADC chip testing module and a DAC chip testing module. Both the ADC chip testing module and the DAC chip testing module are connected to the interface display module, the network communication module, and the standard measuring instrument control module. The interface display module, the network communication module, and the standard measuring instrument control module configure the standard measuring instrument connected to the standard measuring instrument component and the chip under test connected to the test board, and acquire the measurement data and second test data sent by the standard measuring instrument and the chip under test connected to the test board to obtain the measurement result of the chip under test.

[0014] Based on the same inventive concept, this application also provides a chip testing method, applied to the chip testing system described above, the method comprising: The chip under test is mounted on the test board, and the test board is connected to the data processing platform board; Connect the data processing platform board to the host computer, and connect the test board to the standard measuring instrument assembly; The host computer confirms the connection status of the data processing platform board, test board, and standard measuring instrument components; After setting the test parameters according to the type of chip under test, the test system is started through the host computer to receive the second test data or measurement data and analyze the test results.

[0015] Furthermore, the step of setting test parameters according to the type of chip under test and then starting the test system via the host computer to receive second test data or measurement data and analyze the test results includes: In response to determining that the chip under test is an ADC chip, the host computer controls the excitation signal source of the standard measuring instrument component to generate dynamic test excitation signal and static test excitation signal in sequence, and receives the second test data sent by the data processing platform board respectively. The second test data includes test data corresponding to the dynamic test excitation signal and test data corresponding to the static test excitation signal. The host computer analyzes the second test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

[0016] Furthermore, the step of setting test parameters according to the type of chip under test and then starting the test system via the host computer to receive second test data or measurement data and analyze the test results includes: In response to determining that the chip under test is a DAC chip, the host computer sequentially sends dynamic test data and static test data to the data processing platform board. Both the dynamic test data and the static test data are first test data. The host computer also sequentially receives measurement data sent by the spectrum analyzer and the multimeter of the standard measurement instrument assembly. The host computer analyzes the test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

[0017] As can be seen from the above, this application provides a chip testing system and method. The testing system includes a test board, a data processing platform board, a standard measuring instrument assembly, and a host computer connected to each other. The test board is used to mount the chip under test (DUT). The host computer sends first test data to the DUT and receives second test data sent by the DUT through the data processing platform board and the test board. The host computer controls the measuring instruments arranged on the standard measuring instrument assembly through the standard measuring instrument assembly and receives the measurement data obtained by the measuring instruments through the test board testing the DUT. The host computer analyzes the test data or the second test data to obtain the test results of the DUT, realizing automatic testing of the DUT. Furthermore, different DUTs can be mounted through the test board settings, which helps to improve the flexibility of the testing system. This application realizes the collaboration between the standard measuring instrument assembly and the data processing platform board through the host computer, achieving automated testing of the DUT, which can significantly improve chip testing efficiency and accuracy. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a chip testing system according to an embodiment of this application; Figure 2 This is a schematic flowchart of a chip testing method according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application.

[0020] In the diagram: 10. Test board; 11. Chip mounting socket; 12. Third FMC interface; 20. Data processing platform board; 21. First FMC interface; 22. Second FMC interface; 30. Standard measuring instrument assembly; 40. Host computer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] With the increasing demands for signal processing speed and accuracy in systems such as communication, radar, and medical imaging, the performance testing of ADC / DAC chips, as the key interface between analog and digital signals, has become a crucial step in the R&D and production process. Currently, common ADC / DAC testing solutions fall into two main categories: one is application-specific integrated circuit (ATE) testing systems, which offer high integration and fast testing speeds, but are expensive and lack testing flexibility, making them difficult to meet testing requirements; the other is testing platforms built on discrete instruments, which are lower in cost but typically rely on manual operation and data recording, resulting in inconsistent testing procedures and low efficiency. Furthermore, traditional testing systems lack a collaborative control mechanism between the digital signal processing platform and analog measurement instruments, leading to fragmented testing processes and hindering fully automated parameter extraction and result analysis.

[0024] Based on this, this application provides a chip testing system and method. The testing system includes a data processing platform board, a test board, a host computer, and a standard measuring instrument assembly. The testing system drives the chip under test (DUT) mounted on the test board through the data processing platform board. The test board enables hardware compatibility with different ADC / DAC testing requirements. The host computer controls the data processing platform board and receives test data from the DUT acquired by the data management platform board. It also remotely controls the standard measuring instruments on the standard measuring instrument assembly to acquire measurement data or control the standard instruments to generate excitation signals. Through linkage with the standard measuring instrument assembly, automated measurement and recording of the ADC / DAC chip under test are completed. Based on this application, users only need to customize the test board to perform performance testing on ADC or DAC chips, offering excellent flexibility. Furthermore, the high performance and high precision of the standard measuring instruments ensure more reliable test results and guarantee high accuracy.

[0025] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] In some embodiments, such as Figure 1 As shown, a chip testing system includes: Test board, used to mount the chip under test; A data processing platform board is connected to the test board and connected to the chip under test through the test board to send first test data to the chip under test or receive second test data sent by the chip under test. A standard measuring instrument assembly is connected to the test board, and the test board is connected to the chip under test to assist in completing the test of the chip under test; The host computer is connected to the data processing platform board and the standard measuring instrument assembly to send test commands to the data processing platform board and receive and analyze the second test data sent by the data processing platform board or the measurement data sent by the standard measuring instrument assembly to obtain the test results of the chip under test.

[0027] Specifically, the test board is adapted to the chip under test for installing the chip under test. The data processing platform board is a chip that generates and collects data, used to send the first test data to the test board based on the test instructions sent by the host computer, or to collect the second test data generated by the chip under test through the test board and send it to the host computer for analysis.

[0028] The standard measuring instrument assembly is connected to the test board to collect measurement data generated by the chip under test (DUT) or send excitation signals to the DUT for testing. The standard measuring instrument assembly is also connected to the host computer, and its operation is controlled by the host computer. It collects measurement data or generates excitation signals according to the host computer's instructions and sends the collected measurement data to the host computer for analysis to obtain the measurement results of the DUT.

[0029] It should be noted that the test system is used to test DAC chips and ADC chips. Therefore, the test board includes two types: one adapted to DAC chips and the other adapted to ADC chips. The test system can test both types of chips by simply changing the test board, which helps to reduce the cost of the test system and improve its practicality.

[0030] In this embodiment, the testing system includes a test board, a data processing platform board, a standard measuring instrument assembly, and a host computer connected to each other. The test board is used to mount the chip under test (DUT). The host computer sends first test data to the DUT and receives second test data sent by the DUT through the data processing platform board and the test board. The host computer controls the measuring instruments arranged on the standard measuring instrument assembly through the standard measuring instrument assembly and receives the measurement data obtained by the measuring instruments from testing the DUT through the test board. The host computer analyzes the test data or the second test data to obtain the test results of the DUT, realizing automatic testing of the DUT. Furthermore, different DUTs can be mounted through the test board settings, which helps to improve the flexibility of the testing system. This application realizes the collaboration between the standard measuring instrument assembly and the data processing platform board through the host computer, realizing the automation of testing of the DUT, which can significantly improve the chip testing efficiency and accuracy.

[0031] In some embodiments, the standard measurement instrument assembly includes an excitation signal source, a spectrum analyzer, and a multimeter. The excitation signal source is used to send an excitation signal to the chip under test (DUT), the spectrum analyzer is used to analyze the output signal spectrum of the DUT, and the multimeter is used to measure the static parameters of the DUT.

[0032] Specifically, the control and output terminals of the standard measuring instrument assembly are connected to the host computer, and the test terminal of the standard measuring instrument assembly is connected to the test board to connect to the chip under test through the test board in order to obtain the measurement data of the chip under test.

[0033] The standard measuring instrument assembly includes an excitation signal source, a spectrum analyzer, and a multimeter. Each of the excitation signal source, spectrum analyzer, and multimeter has an independent power supply. After connecting them to the host computer and the test board, the host computer can control their startup and output of measurement data.

[0034] The excitation signal source includes a function signal generator and an RF signal generator. The function signal generator generates low-frequency signals, and the RF signal generator generates high-frequency signals. The host computer drives the function signal generator and the RF signal generator sequentially according to test requirements to test the performance of the chip under test at low and high frequencies, respectively. The excitation signal source is used to test the ADC chip.

[0035] The spectrum analyzer and multimeter are used to test the DAC chip and measure the signal generated by the chip under test under the input signal of the data processing platform board.

[0036] In this embodiment, the standard measurement instrument assembly includes an excitation signal source, a spectrum analyzer, and a multimeter to adapt to the testing of different types of chips under test. This allows the host computer to drive different measurement instruments to perform measurements according to the type of chip under test, meeting the measurement requirements. At the same time, the measurement instruments included in the standard measurement instrument assembly are all standard measurement instruments, which helps to improve the flexibility and accuracy of the system.

[0037] In some embodiments, the data processing platform board includes a first FMC interface, an FPGA chip, and a second FMC interface connected in sequence. The first FMC interface is used to connect to the test board, and the second FMC interface is used to connect to the host computer.

[0038] Specifically, the first FMC interface and the second FMC interface are the structure for connecting the FPGA chip with the host computer and the test board. The FPGA chip receives and sends data through the first FMC interface and the second FMC interface, and realizes the transmission of electrical signals, so as to realize the application of the FPGA chip and the chip under test installed on the test board.

[0039] In some embodiments, the test board includes a connected chip mounting base and a third FMC interface. The chip mounting base is used to mount the chip under test. The third FMC interface is connected to the first FMC interface. The test board is connected to the data processing platform through the first FMC interface and the third FMC interface.

[0040] Specifically, the test board is connected to the first FMC interface through the third FMC interface, which is connected to the chip mounting base so that the chip under test mounted on the chip mounting base can be connected to the third FMC interface and thus connected to the FPGA chip. This facilitates the interconnection between the chip under test mounted on the chip mounting base and the FPGA chip.

[0041] In some embodiments, the test board further includes a clock module connected to the chip mounting base and the third FMC interface to provide a synchronous clock signal to the chip under test and the data processing platform.

[0042] Specifically, the clock module includes a clock chip that can be configured via programming. It can support coherent sampling testing of the ADC (Analog-to-Digital Converter) from an externally input high-precision, low-jitter clock signal, or it can choose to provide the clock signal to the clock chip via an onboard high-performance crystal oscillator. The clock module not only provides a clock signal to the ADC but also fans out a clock signal through the first and third FMC interfaces to provide a clock to the FPGA chip on the data processing platform board, ensuring clock synchronization. Furthermore, the selected clock chip's fan-out frequency can be programmed to meet the testing requirements of different sampling rates.

[0043] In some embodiments, the test board further includes a power management module, which is connected to the third FMC interface, the clock module, and the chip mounting base. The power management module obtains power from the data processing platform through the third FMC interface to provide power to the chip under test connected to the clock module and the chip mounting base.

[0044] Specifically, the power management module obtains power from the data processing platform board through the third FMC interface and supplies power to the chip under test and the clock module to ensure the normal operation of the chip under test and the clock module.

[0045] In some embodiments, the host computer includes an interface display module, which is used to display the settings window of the chip under test, the instrument connection status, and the test results of the chip under test.

[0046] Specifically, when using the testing system to test the chip under test, the interface display module displays the chip under test's settings window, providing information such as the chip type and test parameters during testing. The interface display module also displays the real-time connection status between the host computer and the standard measuring instrument components for user viewing, meeting testing needs. When the host computer completes the testing of the chip under test, it analyzes the results, which are then displayed by the interface display module, serving as an interactive element for the user.

[0047] In some embodiments, the host computer further includes a network communication module, which is used to communicate with the data processing platform to send test commands to the chip under test through the data management platform, send first test data to the chip under test, and receive second test data sent by the chip under test.

[0048] Specifically, the network communication module is used to communicate with the data processing platform board, issue configuration commands to the chip under test, issue test data to the chip under test when the chip under test is a DAC chip, and receive sampling data from the data management platform board when the chip under test is an ADC chip. At the same time, the network communication module is also used for remote control communication of the standard measuring instrument assembly, including issuing control commands to each instrument in the standard measuring instrument assembly and receiving measurement data from each instrument in the standard measuring instrument assembly, so as to realize the test automation of the test system.

[0049] In some embodiments, the host computer further includes a standard measuring instrument control module, which is connected to the standard measuring instrument assembly and is used to control the standard measuring instruments connected to the standard measuring instrument assembly. The standard measuring instrument control module is also connected to the network communication module to control the standard measuring instruments connected to the standard measuring instrument assembly based on the network communication module.

[0050] Specifically, the standard measuring instrument control module integrates a low-level I / O library and supports SCPI commands for remote control of each instrument in the standard measuring instrument component. The standard measuring instrument control module is connected to the network communication module to control each instrument in the standard measuring instrument component with the communication support of the network communication module.

[0051] In some embodiments, the host computer further includes an ADC chip testing module and a DAC chip testing module. Both the ADC chip testing module and the DAC chip testing module are connected to the interface display module, the network communication module, and the standard measurement instrument control module. The interface display module, the network communication module, and the standard measurement instrument control module configure the standard measurement instrument connected to the standard measurement instrument component and the chip under test connected to the test board, and acquire the measurement data and second test data sent by the standard measurement instrument and the chip under test connected to the test board to obtain the measurement result of the chip under test.

[0052] Specifically, the ADC chip testing module supports setting the test status of the chip under test (ADC) on the host computer and configuring the excitation signal source (function signal generator or RF signal source) by calling the standard measurement instrument control module to generate the required test excitation signal for testing the ADC. The ADC chip testing module can also analyze and process the second test data received from the ADC to obtain the dynamic indicators of the ADC, including signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), total harmonic distortion (THD), and effective number of bits (ENOB). It can also obtain static indicators, including integral nonlinearity (INL) and differential nonlinearity (DNL). The DAC chip testing module supports setting the test status of the chip under test (DAC) on the host computer. It configures the spectrum analyzer or benchtop multimeter by calling the standard measurement instrument control module. The module analyzes the raw spectrum test data of the DAC returned by the spectrum analyzer to obtain the dynamic indicators of the DAC, including signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), total harmonic distortion (THD), and effective bits (ENOB). It also analyzes the test results returned by the benchtop multimeter to obtain the static indicators of the DAC chip, including integral nonlinearity (INL) and differential nonlinearity (DNL). The ADC chip testing module and DAC chip testing module are used to analyze the test results when the chip under test is an ADC and a DAC, respectively, to achieve different analysis processes for different types of chips under test, thus improving the practicality of the testing system.

[0053] Based on the same inventive concept, this application also provides a chip testing method, applied to the chip testing system described above, such as... Figure 2 As shown, the method includes: Step S101: Install the chip under test on the test board and connect the test board to the data processing platform board; Specifically, before testing the chip under test using the testing system, a corresponding test board is determined according to the type of the chip under test, and the chip under test is installed on the test board. Then, the test board with the chip under test installed is connected to the data management platform board.

[0054] Step S102: Connect the data processing platform board to the host computer, and connect the test board to the standard measuring instrument assembly; Specifically, the data management platform board connected to the test board is connected to the host computer, and the test board is connected to the standard test instrument assembly.

[0055] It should be noted that, depending on the type of the chip under test (DUT), the instruments in the standard test instrument assembly are connected to the test board. For example, when the DUT is an ADC, the test board is connected to the excitation signal source in the standard test instrument assembly to generate an excitation signal for the DUT. The data management platform board is used to obtain the second test data generated by the DUT under the action of the excitation signal. When the DUT is a DAC, the test board is connected to the spectrum analyzer and multimeter in the standard test instrument assembly to obtain the measurement data of the DUT under the action of the first test data generated by the data management platform board.

[0056] Step S103: The host computer confirms the connection status of the data processing platform board, the test board, and the standard measuring instrument assembly. Specifically, the host computer and the standard measuring instrument assembly are wirelessly connected and can automatically connect when the host computer is turned on. Therefore, after the test board, the standard measuring instrument assembly and the data management platform board are all connected, the connection status of each structure in the test system can be viewed through the host computer to make a final confirmation of the connection status before the test.

[0057] Step S104: After setting the test parameters according to the type of chip under test, the test system is started through the host computer to receive the second test data or measurement data and analyze the test results.

[0058] Specifically, after confirming that the connection of the test system is normal, the test parameters can be set on the host computer, and the test system can be started on the host computer to execute the test steps. After receiving the second test data sent by the data management platform board or the test data sent by the standard measuring instrument component, the host computer analyzes it to obtain the test results of the chip under test.

[0059] It should be noted that when the chip under test is an ADC, the host computer receives the second test data and analyzes the second test data to obtain the test result. When the chip under test is a DAC, the host computer receives the measurement data and analyzes the measurement data to obtain the test result.

[0060] In this embodiment, when using the testing system to test the chip under test, the chip under test is first installed on a compatible testing board, then the testing board is connected to the data management platform board, the data management platform is connected to the host computer, and the standard measuring instrument assembly is connected to the testing board, thus completing the installation of the testing system. The host computer starts the standard measuring instrument assembly and starts the testing system to test the chip under test according to the type of the chip under test. The host computer can automatically analyze and obtain the test results of the chip under test, realizing automated testing of the chip under test. This is beneficial to improving testing efficiency. At the same time, testing the chip under test through the standard measuring instrument and the data management platform can also improve the testing accuracy of the testing system.

[0061] In some embodiments, step S104: after setting the test parameters according to the type of the chip under test, the test system is started through the host computer to receive second test data or measurement data and analyze the test results, including: Step S201: In response to determining that the chip under test is an ADC chip, the host computer controls the excitation signal source of the standard measuring instrument component to generate dynamic test excitation signal and static test excitation signal in sequence, and receives the second test data sent by the data processing platform board respectively. The second test data includes test data corresponding to the dynamic test excitation signal and test data corresponding to the static test excitation signal. Specifically, the user sets test parameters on the host computer according to the type of the chip under test (DUT), so that the test system performs tests matching the type of the DUT. When the DUT is an ADC chip, the ADC dynamic index test frequency and ADC sampling rate are set. The host computer controls the excitation signal source to generate a dynamic test excitation signal according to the dynamic index. The host computer receives the second test data sent by the DUT through the data processing platform board. This second test data is the data corresponding to the dynamic test excitation signal. Then, the ADC static index test frequency and sampling rate are set. The host computer controls the excitation signal source to generate a static test excitation signal according to the static index. The host computer receives the second test data sent by the DUT through the data processing platform board. This second test data is the data corresponding to the static test excitation signal. Thus, the second test data obtained by the host computer is the test data of the DUT (ADC). The host computer can obtain the test result of the DUT (ADC) by analyzing this test data.

[0062] In step S202, the host computer analyzes the second test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

[0063] Specifically, the host computer analyzes the test data corresponding to the dynamic test excitation signal in the second test data to obtain the dynamic results of the chip under test (ADC) at the test frequency, including: signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), total harmonic distortion (THD), and effective number of bits (ENOB); the host computer analyzes the test data corresponding to the static test excitation signal in the second test data to obtain the static results of the chip under test (ADC), including: integral nonlinearity (INL) and differential nonlinearity (DNL).

[0064] It should be noted that after obtaining the test results, the host computer displays the test results on its interface, which is done through the interface display module.

[0065] In this embodiment, when the chip under test is an ADC, the host computer controls the excitation signal source of the standard measurement instrument component to generate dynamic test excitation signals and static test excitation signals respectively, so as to obtain the second test data of the chip under test through the data processing platform board, and obtain the dynamic and static results of the chip under test by analyzing the second test data, thereby obtaining the test result of the chip under test. The user only needs to make settings before the test starts to realize the automated testing of the ADC chip, which greatly improves the testing efficiency.

[0066] In some embodiments, step S104: after setting the test parameters according to the type of the chip under test, the test system is started through the host computer to receive second test data or measurement data and analyze the test results, including: In step S301, in response to determining that the chip under test is a DAC chip, the host computer sequentially sends dynamic test data and static test data to the data processing platform board. Both the dynamic test data and the static test data are first test data. The host computer also sequentially receives measurement data sent by the spectrum analyzer and the multimeter of the standard measurement instrument component. Specifically, when the chip under test (DUT) is an ADC chip, the DAC dynamic performance test frequency and DAC sampling rate are set. The host computer controls the spectrum analyzer in the standard measurement instrument assembly to complete the working parameter settings and sends the test data corresponding to the DAC chip being tested, i.e., the first test data, to the data processing platform board. This allows the data processing platform board to send the dynamic test signal in the first test data as an excitation signal to the DUT, thereby enabling the spectrum analyzer to detect the measurement data of the DUT. It should be noted that the measurement data obtained by the spectrum analyzer corresponds to the dynamic test signal. Next, the DAC static performance test working parameters are set. The host computer controls a multimeter to complete the parameter settings, and the data processing platform board sends the static test data in the first test data as an excitation signal to the DUT, thereby enabling the multimeter to detect the measurement data of the DUT. It should be noted that the measurement data obtained by the multimeter corresponds to the static test signal.

[0067] In step S302, the host computer analyzes the test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

[0068] Specifically, the host computer analyzes the measurement data sent by the multimeter to obtain static results, including integral nonlinearity (INL) and differential nonlinearity (DNL). The host computer also analyzes the measurement data sent by the spectrum analyzer to obtain dynamic results, including signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), total harmonic distortion (THD), and effective number of bits (ENOB).

[0069] It should be noted that after obtaining the test results, the host computer displays the test results on its interface, which is done through the interface display module.

[0070] In this embodiment, when the chip under test is a DAC, the host computer sends first test data to the data processing platform board, causing the data processing platform board to sequentially send dynamic test excitation signals and static test excitation signals to the chip under test. This allows the standard measurement instrument component to acquire the measurement data of the chip under test, and by analyzing the measurement data, the dynamic and static results of the chip under test are obtained, thus yielding the test results of the chip under test. Automated testing of the DAC chip can be achieved simply by the user setting it up before the test begins, greatly improving testing efficiency.

[0071] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method described.

[0072] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0073] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the testing method described in any of the above embodiments.

[0074] Figure 3 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0075] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0076] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0077] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0078] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0079] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0080] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0081] The electronic devices described above are used to implement the corresponding test methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0082] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to perform the test method as described in any of the above embodiments.

[0083] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0084] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the test method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0085] Based on the same concept, corresponding to any of the above embodiments, this application also provides a computer program product, including computer program instructions, which, when run on a computer, cause the computer to perform the method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0086] It is understood that before using the technical solutions of the various embodiments in this disclosure, users will be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner, and user authorization will be obtained.

[0087] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations of this disclosed technical solution.

[0088] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0089] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0090] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0091] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0092] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0093] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the claims of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip testing system, characterized in that, include: Test board, used to mount the chip under test; A data processing platform board is connected to the test board and connected to the chip under test through the test board to send first test data to the chip under test or receive second test data sent by the chip under test. A standard measuring instrument assembly is connected to the test board, and the test board is connected to the chip under test to assist in completing the test of the chip under test; The host computer is connected to the data processing platform board and the standard measuring instrument assembly to send test commands to the data processing platform board and receive and analyze the second test data sent by the data processing platform board or the measurement data sent by the standard measuring instrument assembly to obtain the test results of the chip under test.

2. The chip testing system according to claim 1, characterized in that, The standard measurement instrument assembly includes an excitation signal source, a spectrum analyzer, and a multimeter. The excitation signal source is used to send an excitation signal to the chip under test (DUT), the spectrum analyzer is used to analyze the output signal spectrum of the DUT, and the multimeter is used to measure the static parameters of the DUT.

3. The chip testing system according to claim 1, characterized in that, The data processing platform board includes a first FMC interface, an FPGA chip, and a second FMC interface connected in sequence. The first FMC interface is used to connect to the test board, and the second FMC interface is used to connect to the host computer.

4. The chip testing system according to claim 3, characterized in that, The test board includes a connected chip mounting base and a third FMC interface. The chip mounting base is used to mount the chip under test. The third FMC interface is connected to the first FMC interface. The test board is connected to the data processing platform through the first FMC interface and the third FMC interface.

5. The chip testing system according to claim 4, characterized in that, The test board also includes a clock module, which is connected to the chip mounting base and the third FMC interface to provide a synchronous clock signal to the chip under test and the data processing platform.

6. The chip testing system according to claim 5, characterized in that, The test board also includes a power management module, which is connected to the third FMC interface, the clock module, and the chip mounting base. The power management module obtains power from the data processing platform through the third FMC interface to provide power to the chip under test connected to the clock module and the chip mounting base.

7. The chip testing system according to claim 1, characterized in that, The host computer includes an interface display module, which is used to display the settings window of the chip under test, the instrument connection status, and the test results of the chip under test.

8. The chip testing system according to claim 7, characterized in that, The host computer also includes a network communication module, which is used to communicate with the data processing platform to send test commands to the chip under test through the data management platform, send first test data to the chip under test, and receive second test data sent by the chip under test.

9. The chip testing system according to claim 8, characterized in that, The host computer also includes a standard measuring instrument control module, which is connected to the standard measuring instrument assembly and is used to control the standard measuring instruments connected to the standard measuring instrument assembly. The standard measuring instrument control module is also connected to the network communication module to control the standard measuring instruments connected to the standard measuring instrument assembly based on the network communication module.

10. The chip testing system according to claim 9, characterized in that, The host computer also includes an ADC chip testing module and a DAC chip testing module. Both the ADC chip testing module and the DAC chip testing module are connected to the interface display module, the network communication module, and the standard measuring instrument control module. The interface display module, the network communication module, and the standard measuring instrument control module configure the standard measuring instrument connected to the standard measuring instrument component and the chip under test connected to the test board, and acquire the measurement data and second test data sent by the standard measuring instrument and the chip under test connected to the test board to obtain the measurement result of the chip under test.

11. A chip testing method, characterized in that, The method, applied to the chip testing system as described in any one of claims 1-10, comprises: The chip under test is mounted on the test board, and the test board is connected to the data processing platform board; Connect the data processing platform board to the host computer, and connect the test board to the standard measuring instrument assembly; The host computer confirms the connection status of the data processing platform board, test board, and standard measuring instrument components; After setting the test parameters according to the type of chip under test, the test system is started through the host computer to receive the second test data or measurement data and analyze the test results.

12. The chip testing method according to claim 11, characterized in that, The process of setting test parameters according to the type of chip under test and then starting the test system via the host computer to receive second test data or measurement data and analyze the test results includes: In response to determining that the chip under test is an ADC chip, the host computer controls the excitation signal source of the standard measuring instrument component to generate dynamic test excitation signal and static test excitation signal in sequence, and receives the second test data sent by the data processing platform board respectively. The second test data includes test data corresponding to the dynamic test excitation signal and test data corresponding to the static test excitation signal. The host computer analyzes the second test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

13. The chip testing method according to claim 11, characterized in that, The process of setting test parameters according to the type of chip under test and then starting the test system via the host computer to receive second test data or measurement data and analyze the test results includes: In response to determining that the chip under test is a DAC chip, the host computer sequentially sends dynamic test data and static test data to the data processing platform board. Both the dynamic test data and the static test data are first test data. The host computer also sequentially receives measurement data sent by the spectrum analyzer and the multimeter of the standard measurement instrument assembly. The host computer analyzes the test data to obtain the test results of the chip under test, and the test results include dynamic results and static results.

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