Trigger clock generation circuit and chip

Abstract

The invention relates to a trigger clock generation circuit and a chip, and the circuit comprises a clock gating module which is used for outputting a first write clock signal; the synchronous gating module is used for performing synchronous gating processing on the write-in signal according to a second clock signal and outputting a first node signal and a second write clock signal; the enabling control module is connected with the crystal oscillator and is used for carrying out delay processing on the primary enabling signal so as to output a second node signal and a target enabling signal; and the clock gating module is respectively connected with the clock gating module, the synchronous gating module, the enabling control module and the configuration register, and is used for outputting a trigger clock signal for triggering the configuration register to perform write-in operation according to the first node signal, the second node signal, the third clock signal, the first write clock signal and the second write clock signal. Based on the trigger clock generation circuit provided by the invention, the configuration register can be triggered to write no matter whether the internal clock source of the chip is started or not.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a trigger clock generation circuit and chip. Background Technology

[0002] In related technologies, when writing to the configuration register inside the chip, the chip's internal clock source is usually used to synchronize the external write signal to eliminate the risk of metastability. At this time, the trigger clock of the configuration register is the internal clock domain signal.

[0003] However, when the chip's internal clock source is turned off, the configuration register cannot be written to. Summary of the Invention

[0004] Therefore, it is necessary to provide a trigger clock generation circuit and chip that can trigger the configuration register to perform write operations regardless of whether the internal clock source is enabled, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a trigger clock generation circuit, comprising:

[0006] A clock gating module is used to perform gating processing on the received write signal according to the received first clock signal, so as to output the first write clock signal;

[0007] A synchronous gating module is used to connect to a crystal oscillator and to perform synchronous gating processing on the received write signal according to a second clock signal provided by the crystal oscillator, so as to output a first node signal and a second write clock signal.

[0008] An enable control module is used to connect to the crystal oscillator and to receive a primary enable signal and perform a delay on the primary enable signal to output a second node signal and a target enable signal; the target enable signal is used to control the on / off state of the crystal oscillator.

[0009] A clock gating module is connected to the clock gating module, the synchronization gating module, and the enable control module, respectively. It is used to connect to the configuration register and to output a trigger clock signal based on the first node signal, the second node signal, the third clock signal, the first write clock signal, and the second write clock signal. The trigger clock signal includes either the first write clock signal or the second write clock signal, and the trigger clock signal is used to trigger the configuration register to perform a write operation.

[0010] In one embodiment, the first node signal is a delayed version of the write signal, the second node signal is a delayed version of the primary enable signal, the target enable signal is related to the second node signal, and the second clock signal has the opposite level to the third clock signal; wherein...

[0011] The clock gating module is also used to output the first write clock signal when the second node signal is invalid and the third clock signal is valid;

[0012] The clock gating module is also used to switch from outputting the first write clock signal to outputting the second write clock signal when both the second node signal and the third clock signal are at valid levels, and when the first node signal switches from valid level to invalid level for the first time during the crystal oscillator turn-on process.

[0013] When the target enable signal is at an invalid level, the crystal oscillator is in the off state; when the target enable signal is at an active level, the crystal oscillator is in the on state.

[0014] In one embodiment, the clock strobe module includes:

[0015] The signal generation module has multiple input terminals connected to the first target node in the synchronization gating module, the second target node in the enable control module, and the output terminal of the signal generation module, respectively. Another input terminal of the signal generation module is used to receive the third clock signal. The signal generation module is used to perform gating delay processing on the first node signal, the second node signal, the third clock signal, and the historical clock gating signal, and output the target clock gating signal.

[0016] The clock gating module has two input terminals connected to the output terminals of the clock gating module and the synchronization gating module, respectively. The control terminal of the clock gating module is connected to the output terminal of the signal generation module. The output terminal of the clock gating module is used to connect to the clock input terminal of the configuration register. The clock gating module is used to output a trigger clock signal according to the target clock gating signal, the first write clock signal, and the second write clock signal.

[0017] In one embodiment, the signal generation module includes: a first gating submodule and a first triggering submodule;

[0018] The first gating submodule has multiple input terminals connected to the first target node, the second target node, and a third input terminal connected to the data output terminal of the first trigger submodule. The first gating submodule performs gating processing on the first node signal, the second node signal, and the historical clock gating signal to output an initial gating signal.

[0019] The data input terminal of the first trigger submodule is connected to the output terminal of the first gating submodule; the clock input terminal of the first trigger submodule is used to receive a third clock signal; the first trigger submodule is used to delay the initial gating signal according to the third clock signal OSC_N and output the target clock gating signal.

[0020] In one embodiment, the synchronization gating module includes:

[0021] The signal synchronization module is used to receive the second clock signal and the write signal, and to perform synchronization gating processing on the write signal according to the second clock signal to output the first node signal and the gating signal.

[0022] The clock gating module, connected to the signal synchronization module and the clock gating module, is used to receive the gating signal and the second clock signal to output the second write clock signal.

[0023] In one embodiment, the signal synchronization module includes:

[0024] A signal synchronization submodule, wherein the input terminal of the signal synchronization submodule is used to receive the second clock signal and the write signal; the signal synchronization submodule is used to perform synchronization processing on the write signal according to the second clock signal and output the first node signal;

[0025] The second gating submodule has an input terminal for receiving the first node signal and the second clock signal; its output terminal is connected to the clock gating module; and it performs gating processing on the first node signal and the second clock signal to output the gating signal.

[0026] In one embodiment, the second gating submodule includes:

[0027] The first trigger unit has a data input terminal for receiving the first node signal and a clock input terminal for receiving a second clock signal. The first trigger unit is used to perform delay processing on the first node signal according to the second clock signal OSC and output the third node signal.

[0028] The first gating unit has a first input terminal connected to the data input terminal of the first trigger unit, a second input terminal connected to the data output terminal of the first trigger unit, and an output terminal connected to the clock gating module. The first gating unit is used to generate a gating signal based on the first node signal and the third node signal.

[0029] In one embodiment, the enable control module includes:

[0030] The first trigger module is used to receive the primary start enable signal, the second clock signal and the third clock signal, and to perform delay processing on the primary start enable signal according to the second clock signal and the third clock signal;

[0031] The first gating module, connected to the first triggering module, is used to output a target enable signal based on the primary enable signal and the primary enable signal after the delay processing.

[0032] In one embodiment, the first triggering module includes: a plurality of cascaded first triggers; wherein,

[0033] The data input terminal of the first stage first flip-flop is used to receive the primary enable signal, and the data output terminal of the i-th stage first flip-flop is connected to the data input terminal of the (i+1)-th stage first flip-flop; and the clock input terminal of the first n stages first flip-flops is used to receive the second clock signal, and the clock input terminal of the last m stages first flip-flops is used to receive the third clock signal; where n, m and i are all positive integers.

[0034] The first n-stage first flip-flops are used to delay the primary start enable signal; the last m-stage first flip-flops are used to delay the primary start enable signal after the delay processing of the first n-stage first flip-flops, and are used to control the target enable signal to switch from an active level to an inactive level on the transition edge of the second clock signal.

[0035] Secondly, this application provides a chip, the chip including a crystal oscillator, a configuration register, and the trigger clock generation circuit described in any of the above embodiments.

[0036] The aforementioned trigger clock generation circuit and chip include a clock gating module, a synchronization gating module, an enable control module, and a clock gating module. The clock gating module is connected to the clock gating module, the synchronization gating module, the enable control module, and the configuration register, respectively. The enable control module can delay the primary enable signal and output a second node signal and a target enable signal. By delaying the primary enable signal, the start and stop of the crystal oscillator can be precisely controlled. The clock gating module can output a first write clock signal based on the received first clock signal and write signal; the synchronization gating module can perform synchronous gating processing on the write signal based on the second clock signal and output a first node signal and a second write clock signal. By processing the first clock signal and the second clock signal respectively through the clock gating module and the synchronization gating module, and dynamically selecting the output of the first write clock signal or the second write clock signal by the clock gating module, dynamic switching between the first write clock signal and the synchronized second write clock signal can be realized. This ensures that the configuration register can be triggered to perform a write operation regardless of whether the crystal oscillator is turned on or off. At the same time, since the crystal oscillator does not need to be dynamically switched on or off when triggering the configuration register to perform a write operation, it is also beneficial to reduce power consumption. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a circuit diagram of a configuration register;

[0039] Figure 2 This is a timing diagram of a configuration register;

[0040] Figure 3 A circuit diagram for another configuration register;

[0041] Figure 4 A timing diagram for another configuration register;

[0042] Figure 5 This is a circuit diagram for yet another type of configuration register;

[0043] Figure 6 This is a schematic diagram of a trigger clock generation circuit provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0045] Figure 8 A schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0046] Figure 9 A schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0047] Figure 10 A schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0048] Figure 11 A schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0049] Figure 12 A schematic diagram of another trigger clock generation circuit provided in an embodiment of this application;

[0050] Figure 13 This is a circuit diagram of a trigger clock generation circuit provided in an embodiment of this application.

[0051] Explanation of reference numerals in the attached figures:

[0052] 10-Clock gating module, 20-Synchronization gating module, 21-Signal synchronization module, 211-Signal synchronization submodule, 212-Second gating submodule, 2121-First trigger unit, 2122-First gating unit, 22-Clock gating module, 30-Enable control module, 31-First trigger module, 32-First gating module, 40-Clock strobe module, 41-Signal generation module, 411-First gating submodule, 412-First trigger submodule, 42-Clock strobe module, 50-Crystal oscillator, 60-Configuration register. Detailed Implementation

[0053] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0055] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0056] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0057] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0058] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0059] As described in the background section, by connecting to external communication pins, it is possible to write to the chip's internal configuration registers, such as I2C communication pins. The read / write signals are in the I2C clock domain, meaning they are asynchronous with the chip's internal clock signal. In applications, asynchronous signals typically cannot be directly identified and used, otherwise metastability risks may arise. Please refer to [link to relevant documentation]. Figure 1 and Figure 2 ,exist Figure 1 In this configuration, SCL is the clock line, SDA is the data line, and the trigger clock for configuration register D1 is the external clock SCL. Configuration register D1 outputs the reg_sig1 signal. The internal clock OSC and the external clock SCL are asynchronous. If configuration register D2, triggered by the internal clock OSC, directly identifies the reg_sig1 signal output by configuration register D1, configuration register D2 may sample an intermediate level, resulting in a metastability risk in the reg_sig2 signal output by configuration register D2, which may lead to unpredictable anomalies.

[0060] In applications, to avoid metastability risks, an internal clock (OSC) is typically used to synchronize the output signal reg_sig1 of configuration register D1, which is triggered by the asynchronous clock (SCL). Generally, the internal oscillator frequency is required to be higher than the external oscillator frequency; for example, the internal oscillator frequency should be at least twice the external oscillator frequency. Please refer to [link to relevant documentation]. Figure 3 and Figure 4Configuration register D3, triggered by the internal clock OSC, latches the reg_sig2 signal output from configuration register D2, and configuration register D3 outputs the reg_sig3 signal for internal clock domain identification processing. Figure 4 As can be seen, the reg_sig3 signal is relatively stable, which can reduce the risk of metastability. However, this synchronization mechanism requires that the chip's internal clock be turned on in order to successfully write the configuration data into the configuration register.

[0061] Furthermore, in related technologies, to enable writing to the configuration register via the internal clock OSC even when the internal clock is off, the internal clock enable OSC_EN is typically dynamically controlled based on the external communication timing. Please refer to [link to relevant documentation]. Figure 5 The trigger clocks of configuration registers D2 and D3 are connected to the internal clock OSC. The internal clock enable (OSC_EN) is dynamically controlled according to the external communication timing. When the internal clock is enabled, configuration register write operations are performed. The internal clock synchronizes with the write nodes of the communication, completing the configuration register write operation. The internal clock can directly identify and use the configuration values ​​without clock glitches or metastability risks. When the internal clock is disabled, it is enabled at certain early nodes of external communication (e.g., the communication start node or the node with matching device addresses). After the internal clock outputs, it synchronizes with the write nodes of the communication signals, completing the configuration register write operation. The internal clock can directly identify and use the configuration values ​​without clock glitches or metastability risks. However, this design has certain limitations. On the one hand, there are certain requirements for the external communication rate and the output delay of the clock after it is enabled. If the external communication rate is too fast or the output delay of the clock after it is enabled is too large, the start clock of the output may miss the write node of the external communication, resulting in data writing failure. On the other hand, when the clock is off, the write operation will enable the internal clock, which will increase the power consumption, which is very unfavorable for products with low power consumption requirements.

[0062] For the reasons stated above, in an exemplary embodiment, please refer to... Figure 6 This application provides a trigger clock generation circuit, including: a clock gating module 10, a synchronization gating module 20, an enable control module 30, and a clock gating module 40.

[0063] The clock gating module 10 is used to perform gating processing on the received write signal wen according to the received first clock signal scl, so as to output the first write clock signal wck_scl.

[0064] The synchronous gating module 20 is connected to the crystal oscillator 50 and is used to perform synchronous gating processing on the received write signal wn according to the second clock signal osc provided by the crystal oscillator 50, so as to output the first node signal S1 and the second write clock signal wck_osc.

[0065] The enable control module 30 is connected to the crystal oscillator 50 and is used to receive the primary enable signal en_tmp and perform delay processing on the primary enable signal en_tmp to output the second node signal S2 and the target enable signal en; the target enable signal en is used to control the on and off state of the crystal oscillator 50.

[0066] The clock strobe module 40 is connected to the clock gating module 10, the synchronization gating module 20, and the enable control module 30, respectively. The clock strobe module 40 is also connected to the configuration register 60 and is used to output a trigger clock signal wck based on the first node signal S1, the second node signal S2, the third clock signal osc_n, the first write clock signal wck_scl, and the second write clock signal wck_osc. The trigger clock signal wck includes the first write clock signal wck_scl or the second write clock signal wck_osc. The trigger clock signal wck is used to trigger the configuration register 60 to perform a write operation.

[0067] Taking a chip including the trigger clock generation circuit of this application as an example, for this chip, the first clock signal scl is an external clock signal, the second clock signal osc is an internal clock signal, and the third clock signal osc_n is the inverted signal of the second clock signal osc.

[0068] It is understandable that when the crystal oscillator 50 is turned off, in order to avoid generating internal clock glitches, the primary enable signal en_tmp is often delayed by the enable control module 30. That is, the rising and falling edges of the second clock signal osc are used to delay for a few clock cycles, generally using the falling edge of the last stage or several stages, before the crystal oscillator 50 is turned off. In this application, in order to safely switch the trigger clock of the configuration register 60 from the second write clock signal wck_osc to the first write clock signal wck_scl when the crystal oscillator 50 is turned off, a certain delay node can be selected from the enable control module 30 as a safe node. The clock gating module 40 can safely switch the trigger clock according to the second node signal S2 and the third clock signal osc_n at the safe node.

[0069] It should be noted that the clock gating module 10 of this application outputs a first write clock signal wck_scl based on the received first clock signal scl and write signal wen, that is, the write signal wen serves as the gate for the clock gating module 10. By using the write signal wen as the gate for the clock gating module 10, when the first write clock signal wck_scl is the trigger clock signal wck, the clock gating module 10 will output the first write clock signal wck_scl to the configuration register when the write signal wen is active, i.e., when data needs to be written to the configuration register; when the write signal wen is inactive, i.e., when data does not need to be written to the configuration register, the clock gating module 10 will not output the first write clock signal wck_scl to the configuration register. Therefore, the configuration register can be triggered according to actual needs, thereby reducing power consumption.

[0070] In the application, when the crystal oscillator 50 is turned on, to prevent the second clock signal osc from missing the external communication write node and causing data write failure, this application chooses to switch the trigger clock of the configuration register from the first write clock signal wck_scl in the external clock domain to the second write clock signal wck_osc in the internal clock domain at a safe node during the power-on process. The safe node during the power-on process can be the communication write node or a node other than the combinational logic of the write node and its delay. That is, when the crystal oscillator 50 is turned on, if there is data being written and the write signal wen just changes from an invalid level to an active level, the first write clock signal wck_scl is still used to trigger the configuration register. When the data writing is completed and the write signal wen changes from an active level to an invalid level, the clock gating module 10 then safely switches the trigger clock signal wck from the first write clock signal wck_scl to the second write clock signal wck_osc according to the first node signal S1, the second node signal S2, and the third clock signal osc_n.

[0071] With the trigger clock generation circuit of this application, the configuration register can be written without dynamically switching the crystal oscillator 50 when the crystal oscillator 50 is off, saving circuit resources and further saving power consumption.

[0072] The aforementioned trigger clock generation circuit includes a clock gating module, a synchronization gating module, an enable control module, and a clock gating module. The clock gating module is connected to the clock gating module, the synchronization gating module, the enable control module, and the configuration register, respectively. The enable control module can delay the primary enable signal and output a second node signal and a target enable signal. By delaying the primary enable signal, the start and stop of the crystal oscillator can be precisely controlled. The clock gating module can output a first write clock signal based on the received first clock signal and write signal; the synchronization gating module can perform synchronous gating processing on the write signal based on the second clock signal and output a first node signal and a second write clock signal. By processing the first clock signal and the second clock signal respectively through the clock gating module and the synchronization gating module, and dynamically selecting the output of the first write clock signal or the second write clock signal by the clock gating module, dynamic switching between the first write clock signal and the synchronized second write clock signal can be realized. This ensures that the configuration register can be triggered to perform a write operation regardless of whether the crystal oscillator is turned on or off. At the same time, since the crystal oscillator does not need to be dynamically switched on or off when triggering the configuration register to perform a write operation, it is also beneficial to reduce power consumption.

[0073] In an exemplary embodiment, the first node signal S1 is the delayed version of the write signal wen, the second node signal S2 is the delayed version of the primary enable signal en_tmp, the target enable signal en is related to the second node signal S2, and the second clock signal osc and the third clock signal osc_n have opposite level states. When the target enable signal en is invalid, the crystal oscillator 50 is in the off state; when the target enable signal en is active, the crystal oscillator 50 is in the on state.

[0074] The clock strobe module 40 is also used to output the first write clock signal wck_scl when the second node signal S2 is invalid and the third clock signal osc_n is valid.

[0075] In this embodiment, when the enable control module 30 receives the invalid primary enable signal en_tmp, it does not immediately control the crystal oscillator 50 to shut down. Instead, it performs multi-stage tapping delays on the invalid primary enable signal en_tmp. Only when the signals after each tapping delay are all invalid will the invalid target enable signal en be output. The second node signal S2 is a certain delay signal in the enable control module 30. When the second node signal S2 is invalid, it indicates that the crystal oscillator 50 is about to shut down. Furthermore, when the third clock signal osc_n is valid, that is, when the second clock signal osc is invalid, the clock gating module 40 controls the trigger clock signal wck to safely switch from the second write clock signal wck_osc to the first write clock signal wck_scl. During the subsequent shutdown of the crystal oscillator 50, the first write clock signal wck_scl is continuously selected as the trigger clock for the configuration register.

[0076] The clock gating module 40 is also used to switch from outputting the first write clock signal wck_scl to outputting the second write clock signal wck_osc when both the second node signal S2 and the third clock signal osc_n are at valid levels and the first node signal S1 switches from valid level to invalid level for the first time during the crystal oscillator 50 is turned on.

[0077] In the application, when the enable control module 30 receives the valid primary enable signal en_tmp, it can control the crystal oscillator 50 to turn on. After a tap delay, the second node signal S2 also changes from invalid to valid. When the first node signal S1 changes from valid to invalid, it indicates that a data write is complete. At this time, when the third clock signal osc_n is valid (i.e., the second clock signal osc is invalid), the clock gating module 40 controls the trigger clock signal wck to safely switch from the first write clock signal wck_scl to the second write clock signal wck_osc. During the subsequent crystal oscillator 50 startup process, the second write clock signal wck_osc is continuously selected as the trigger clock for the configuration register.

[0078] In this embodiment, when the second node signal S2 is invalid and the third clock signal osc_n is valid, the clock gating module 40 outputs the first write clock signal wck_scl. This ensures that the system can use a stable first write clock signal wck_scl when the crystal oscillator is not fully started or is in a turned-off state. When both the second node signal S2 and the third clock signal osc_n are valid, and the first node signal S1 switches from valid to invalid for the first time during the crystal oscillator startup process, the clock gating module switches from outputting the first write clock signal wck_scl to outputting the second write clock signal wck_osc. This switching mechanism ensures that the system can switch to the more accurate second clock signal in a timely manner after the crystal oscillator is operating stably, while avoiding unnecessary switching during crystal oscillator startup. This reduces potential glitches and instabilities during clock switching and improves system stability.

[0079] In one exemplary embodiment, please refer to Figure 7 The clock gating module 40 includes a signal generation module 41 and a clock gating module 42.

[0080] Multiple input terminals of the signal generation module 41 are respectively connected to the first target node in the synchronous gating module, the second target node in the enable control module, and the output terminal of the signal generation module 41. Another input terminal of the signal generation module 41 is used to receive the third clock signal. The signal generation module is used to perform gating delay processing on the first node signal S1 at the first target node, the second node signal S2 at the second target node, the third clock signal osc_n, and the historical clock gating signal, and output the target clock gating signal.

[0081] The two input terminals of the clock gating module 42 are connected to the output terminals of the clock gating module 10 and the synchronous gating module 20, respectively. The control terminal of the clock gating module 42 is connected to the output terminal of the signal generation module 41. The output terminal of the clock gating module 42 is used to connect to the clock input terminal of the configuration register 60. The clock gating module is used to output a trigger clock signal according to the target clock gating signal, the first write clock signal wck_scl, and the second write clock signal wck_osc.

[0082] Among them, the historical clock strobe signal and the target clock strobe signal are both clock strobe signals wck_sel, but they differ in timing. That is, the signal generation module 41 will output the current clock strobe signal wck_sel (target clock strobe signal) based on the first node signal S1, the second node signal S2, the third clock signal osc_n, and the clock strobe signal wck_sel (i.e., the historical clock strobe signal) of the previous moment.

[0083] Upon receiving the clock strobe signal wck_sel, the clock strobe module 42 can control the output of a trigger clock signal wck from the first write clock signal wck_scl and the second write clock signal wck_osc. Specifically, when the clock strobe signal wck_sel is at the first level, the trigger clock signal wck is the second write clock signal wck_osc; when the clock strobe signal wck_sel is at the second level, the trigger clock signal wck is the first write clock signal wck_scl. In one example, the first level is high and the second level is low. That is, when the clock strobe signal wck_sel is high, the clock signal wck is triggered as the second write clock signal wck_osc, and when the clock strobe signal wck_sel is low, the clock signal wck is triggered as the first write clock signal wck_scl. In another example, the first level is low and the second level is high. When the clock strobe signal wck_sel is high, the clock signal wck is triggered as the first write clock signal wck_scl, and when the clock strobe signal wck_sel is low, the clock signal wck is triggered as the second write clock signal wck_osc.

[0084] In this embodiment, the signal generation module 41 generates a precise target clock strobe signal wck_sel by performing gating and delay processing on the first node signal S1, the second node signal S2, the third clock signal osc_n, and the historical clock strobe signal. The gating process logically combines and filters the input signals, removing unnecessary interference signals; the delay processing ensures the consistency between the target enable signal en and the clock strobe signal wck_sel. The clock strobe module selects between the first write clock signal wck_scl and the second write clock signal wck_osc based on the target clock strobe signal wck_sel, thereby achieving precise control of the clock signal.

[0085] In one exemplary embodiment, please refer to Figure 8 The signal generation module 41 includes a first gating submodule 411 and a first triggering submodule 412.

[0086] The multiple input terminals of the first gating submodule 411 are respectively connected to the data output terminals of the first target node, the second target node, and the first trigger submodule 412; the first gating submodule 411 performs gating processing on the first node signal S1, the second node signal S2, and the historical clock gating signal to output the initial gating signal sel.

[0087] The data input terminal of the first trigger submodule 412 is connected to the output terminal of the first gating submodule 411; the clock input terminal of the first trigger submodule is used to receive the third clock signal osc_n; the first trigger submodule 412 is used to delay the initial strobe signal sel according to the third clock signal osc_n and output the target clock strobe signal.

[0088] In this embodiment, when the crystal oscillator 50 is about to be turned off, the first gating submodule 411 can output a second-level initial strobe signal sel when the second node signal S2 switches from an active level to an inactive level. The first trigger submodule 412 will delay the initial strobe signal sel to ensure that the second-level clock strobe signal wck_sel is output at the rising edge of the third clock signal osc_n, i.e., the falling edge of the second clock signal osc. This allows the trigger clock of the configuration register to be switched from the second write clock signal wck_osc in the internal clock domain to the first write clock signal wck_scl in the external clock domain at the falling edge of the second clock signal osc. After the crystal oscillator 50 is turned off, the second node signal S2 remains at an inactive level. The first gating submodule 411 continues to output the second-level initial strobe signal sel, and the first trigger submodule 412 continues to output the second-level clock strobe signal wck_sel to ensure that the configuration register 60 can be triggered by the external first write clock signal wck_scl throughout the entire process of the crystal oscillator 50 being turned off.

[0089] In another embodiment, assume the second level is an invalid level (low level) and the first level is an active level (high level). When the crystal oscillator 50 is first turned on, the clock strobe signal wck_sel is still at the second level, and the primary enable signal en_tmp and the target enable signal en change from invalid to active levels. The second node signal S2 also changes from invalid to active level after a tap delay and remains active throughout the entire process of the crystal oscillator 50 being turned on. After the write signal changes from active to invalid, the first node signal S1 changes to invalid.

[0090] When the crystal oscillator 50 is first turned on, the second node signal S2 is active, the first node signal S1 is inactive, and the historical clock strobe signal is inactive. The first gating module outputs an initial strobe signal sel at the first level. The first trigger submodule 412 delays the initial strobe signal sel to ensure that the first-level clock strobe signal wck_sel is output at the rising edge of the third clock signal osc_n, i.e., the falling edge of the second clock signal osc. This allows the trigger clock of the configuration register to be switched from the second write clock signal wck_osc in the internal clock domain to the first write clock signal wck_scl in the external clock domain at the falling edge of the second clock signal osc. After the clock switching is complete, during the subsequent start-up of the crystal oscillator 50, since the clock strobe signal wck_sel has been switched to an active level, the first gating module can continuously output the initial strobe signal sel at the first level, and the first trigger submodule 412 will also continuously output the clock strobe signal wck_sel at the first level, regardless of the level of the first node signal S1, until the crystal oscillator 50 is turned off.

[0091] In one example, the first trigger submodule 412 may include at least one second flip-flop. When the first trigger submodule 412 includes only one second flip-flop, the data input of the second flip-flop is used to receive the initial strobe signal sel, the clock input of the second flip-flop is used to receive the third clock signal osc_n, and the data output of the second flip-flop is used to output the clock strobe signal wck_sel. When the first trigger submodule 412 includes multiple second flip-flops, the clock input of each stage of the second flip-flop is used to receive the third clock signal osc_n, the data input of the first stage of the second flip-flop is used to receive the initial strobe signal sel, the data inputs of the remaining stages of the second flip-flop are respectively connected to the data output of the previous stage of the second flip-flop, and the data output of the last stage of the second flip-flop is used to output the clock strobe signal wck_sel.

[0092] In this embodiment, the first gating submodule performs gating processing on the first node signal S1, the second node signal S2, and the historical clock gating signal wck_sel to generate an initial gating signal. The gating processing can combine and filter the input signals according to different logical relationships, ensuring that a valid initial gating signal is generated only when specific conditions are met. The first triggering submodule performs delay processing on the initial gating signal based on the third clock signal osc_n, outputting the target clock gating signal wck_sel. The delay processing makes the signal changes smoother, avoiding sudden signal jumps, thereby reducing jitter and interference during signal transmission. Through this dual processing of gating and delay, precise control of the clock gating signal is achieved, ensuring the stability and reliability of clock switching.

[0093] In one exemplary embodiment, please refer to Figure 9 The synchronization gating module 20 includes a signal synchronization module 21 and a clock gating module 22.

[0094] The signal synchronization module 21 is used to receive the second clock signal osc and the write signal wen, and to perform synchronous gating processing on the write signal wen according to the second clock signal osc, so as to output the first node signal S1 and the gate signal gate.

[0095] The clock gating module 22 is connected to the signal synchronization module 21 and the clock gating module 40, and is used to receive the gating signal gate and the second clock signal osc to output the second write clock signal wck_osc.

[0096] In this application, with the crystal oscillator enabled, the internal second write clock signal is preferentially used to trigger the configuration register for write operations. Therefore, the signal synchronization module 21 synchronizes the write signal wn according to the second clock signal osc to obtain the first node signal S1, and generates the gate signal gate of the clock gating module 22 based on the first node signal S1. When the gate signal gate is active, the clock gating module 22 outputs the second write clock signal wck_osc according to the second clock signal osc. When the gate signal gate is inactive, the clock gating module 22 is disabled and does not output the second write clock signal wck_osc.

[0097] In this embodiment, the signal synchronization module performs synchronization gating processing on the write signal wn based on the second clock signal osc, outputting the first node signal S1 and the gate signal gate. Synchronization processing ensures that the write signal is in phase with the second clock signal, avoiding metastability risks; gating processing filters and controls the write signal, ensuring that a valid gate signal is generated only at the appropriate time. The clock gating module outputs the second write clock signal wck_osc based on the gate signal gate and the second clock signal osc. This design ensures the synchronization of the second write clock signal wck_osc with the second clock signal osc, and also allows for flexible control of the output of the second write clock signal wck_osc based on the state of the gate signal gate, improving the accuracy and reliability of data writing.

[0098] In one exemplary embodiment, please refer to Figure 10 The signal synchronization module 21 includes: a signal synchronization submodule 211 and a second gating submodule 212.

[0099] The input terminal of the signal synchronization submodule 211 is used to receive the second clock signal osc and the write signal wen; the signal synchronization submodule 211 is used to perform synchronization processing on the write signal wen according to the second clock signal osc and output the first node signal S1.

[0100] The input terminal of the second gate control submodule 212 is used to receive the first node signal S1 and the second clock signal osc; the output terminal of the second gate control submodule 212 is connected to the clock gate control module 22; the second gate control submodule 212 is used to perform gate control processing on the first node signal S1 and the second clock signal osc to output the gate control signal gate.

[0101] It is understandable that the write signal wen belongs to the external clock source, while the second clock signal osc belongs to the internal clock source. In order to eliminate metastability, the second clock signal osc needs to be used to synchronize the write signal wen. Thus, when the configuration register is triggered by the second write clock signal wck_osc, the signal output by the configuration register is synchronized with the second clock signal osc, and can be directly recognized and used without the risk of metastability.

[0102] In one example, the signal synchronization submodule 211 may include multiple stages of third flip-flops. The clock input of each stage of the third flip-flop is used to receive the second clock signal osc; the data input of the first stage of the third flip-flop is used to receive the write signal wen; the data inputs of the remaining stages of the third flip-flop are respectively connected to the data output of the previous stage of the third flip-flop; and the data output of the last stage of the third flip-flop is used to output the first node signal S1.

[0103] In this embodiment, the signal synchronization submodule synchronizes the write signal wc_osc according to the second clock signal osc, and outputs the first node signal S1. Synchronization processing eliminates the phase difference between the write signal and the second clock signal, thus eliminating metastability. The second gating submodule performs gating processing on the first node signal S1 and the second clock signal osc, and outputs a gating signal gate. Gating processing can generate appropriate gating signals based on the states of the first node signal and the second clock signal to control the operation of subsequent circuits. This two-stage processing structure improves the accuracy and reliability of signal processing, ensures signal time consistency through synchronization processing, and achieves precise control of the second write clock signal wck_osc through gating processing.

[0104] In one exemplary embodiment, please refer to Figure 11 The second gating submodule 212 may include: a first triggering unit 2121 and a first gating unit 2122.

[0105] The data input terminal of the first trigger unit 2121 is used to receive the first node signal S1, the clock input terminal of the first trigger unit 2121 is used to receive the second clock signal osc, and the first trigger unit 2121 is used to perform delay processing on the first node signal S1 according to the second clock signal osc and output the third node signal S3.

[0106] The first input terminal of the first gating unit 2122 is connected to the data input terminal of the first trigger unit 2121, the second input terminal of the first gating unit 2122 is connected to the data output terminal of the first trigger unit 2121, and the output terminal of the first gating unit is connected to the clock gating module. The first gating unit 2122 is used to generate a gating signal gate based on the first node signal S1 and the third node signal S3.

[0107] In the application, the first triggering unit 2121 can delay the first node signal S1 once to generate the third node signal S3. That is, the first node signal S1 and the third node signal S3 are separated by one cycle of the second clock signal osc in terms of timing. Therefore, the first gating unit 2122 can generate a gating signal gate with a pulse width of one cycle of the second clock signal osc based on the first node signal S1 and the third node signal S3.

[0108] In one example, the first trigger unit 2121 may include a fourth trigger, the data input terminal of which is used to receive the first node signal S1, the clock input terminal of which is used to receive the second clock signal osc, and the fourth trigger can delay the first node signal S1 once.

[0109] In this embodiment, the first triggering unit 2121 delays the first node signal S1 according to the second clock signal osc and outputs the third node signal S3. The first gating unit generates a gating signal gate based on the first node signal S1 and the third node signal S3. By delaying the first node signal S1 once, the pulse width of the gating signal gate is one period of the second clock signal osc, thereby ensuring that the pulse width of the second write clock signal wck_osc is consistent with the second clock signal osc, improving the accuracy and stability of the second write clock signal wck_osc.

[0110] In one exemplary embodiment, please refer to Figure 12 The enable control module 30 includes a first trigger module 31 and a first gating module 32.

[0111] The first trigger module 31 is used to receive the primary start enable signal en_tmp, the second clock signal osc, and the third clock signal osc_n, and to perform delay processing on the primary start enable signal according to the second clock signal osc and the third clock signal osc_n.

[0112] The first gating module 32 is connected to the first triggering module 31 and is used to output the target enable signal based on the primary enable signal, en_tmp and the primary enable signal en_tmp after multi-level delay processing.

[0113] Specifically, when the first trigger module 31 receives an invalid primary enable signal en_tmp, the first gating module 32 does not immediately control the crystal oscillator 50 to shut down. Instead, the first trigger module 31 performs multi-stage beat delays on the invalid primary enable signal en_tmp. Only when the signals after each beat delay are all invalid will the first gating module 32 output the invalid target enable signal en. When the first trigger module 31 receives a valid primary enable signal en_tmp, the first gating module 32 can synchronously control the crystal oscillator 50 to turn on.

[0114] In this embodiment, the first triggering module 31 includes multiple cascaded first flip-flops. The data input terminal of the first-stage first flip-flop is used to receive the primary enable signal en_tmp, and the data output terminal of the i-th stage first flip-flop is connected to the data input terminal of the (i+1)-th stage first flip-flop. Furthermore, the clock input terminals of the first n stages of first flip-flops are used to receive the second clock signal osc, and the clock input terminals of the last m stages of first flip-flops are used to receive the third clock signal osc_n; where n, m, and i are all positive integers.

[0115] In this example, the first n-stage first flip-flops are used to delay the primary start enable signal en_tmp, and the last m-stage first flip-flops are used to delay the primary start enable signal after the delay processing of the first n-stage first flip-flops. Since the last m-stage first flip-flops receive the third clock signal osc_n, which is inverted from the second clock signal osc, the delay of the last m-stage first flip-flops can ensure that the target enable signal en output by the first gating module 12 switches from an active level to an inactive level at the rising edge of the third clock signal osc_n, which is the falling edge of the second clock signal osc. This ensures that the second clock signal osc is turned off at the falling edge, avoiding clock glitches.

[0116] In this embodiment, the primary enable signal `en_tmp` is delayed by the first n-stage first flip-flops, and the signal after the first n-stage delay is further delayed by the subsequent m-stage first flip-flops. The target enable signal `en` is then controlled to switch from an active level to an inactive level on the transition edge of the second clock signal `osc`. This multi-stage delay processing and precise switching control make the change in the target enable signal smoother and more accurate, reducing interference and instability during clock switching and improving the reliability and stability of the system. In applications, by reasonably setting the values ​​of `n` and `m`, the delay length and switching timing can be adjusted according to actual needs to achieve flexible control of the target enable signal.

[0117] In a detailed embodiment, please refer to Figure 13 , Figure 13 This is a detailed circuit diagram of a trigger clock generation circuit in one example.

[0118] In this example, the trigger clock generation circuit includes a clock gating module 10, a synchronization gating module 20, an enable control module 30, and a clock strobe module 40. The explanation will use a high level as the active level and a low level as the inactive level.

[0119] The enable control module 30 includes a first trigger module 31 and a first gating module 32. The first trigger module 31 includes multiple cascaded first flip-flops (DFF1~DFF5) and a first NOT gate. The first gating module 32 includes a first OR gate. The data input terminal of the first flip-flop DFF1 is used to receive the primary enable signal en_tmp. The data input terminals of the remaining first flip-flops are connected to the data output terminals of the previous stage's first flip-flops. The clock input terminals of the first flip-flops DFF1, DFF2, and DFF3 are used to receive the second clock signal osc. The clock input terminals of the first flip-flops DFF4 and DFF5 are used to receive the third clock signal osc_n, which is the inverted version of the second clock signal osc. Multiple input terminals of the first gating module 32 are connected to the data output terminals of the subsequent first flip-flops, and one input terminal of the first gating module 32 is used to receive the primary enable signal en_tmp. It is understandable that, since the first gate module 32 is an OR gate, the target enable signal en is only invalid when the primary enable signal en_tmp is invalid and the signals output by each stage of the first flip-flop are invalid; the target enable signal en is valid as long as the signal at any input terminal of the first gate module 32 is valid.

[0120] The clock gating module 40 includes a signal generation module 41 and a clock gating module 42. The signal generation module 41 further includes a first gating submodule 411 and a first trigger submodule 412. The first gating submodule 411 includes a second NOT gate, a second OR gate, and a first AND gate. The input of the second NOT gate is used to receive the first node signal S1. The first input of the second OR gate is connected to the output of the second NOT gate. The second input of the second OR gate is used to receive the clock gating signal wck_sel. The first input of the first AND gate is connected to the output of the second OR gate. The second input of the first AND gate is used to receive the second node signal. The output of the first AND gate is used to output the initial gating signal sel. The first trigger submodule 412 includes a second flip-flop DFF6. The data input of the second flip-flop DFF6 is used to receive the initial gating signal sel. The clock input of the second flip-flop DFF6 is used to receive the third clock signal osc_n. The data output of the second flip-flop DFF6 is used to output the clock gating signal wck_sel.

[0121] The synchronization gating module 20 includes a signal synchronization module 21 and a clock gating module 22. The signal synchronization module 21 includes a signal synchronization submodule 211 and a second gating submodule 212. The second gating submodule 212 includes a first trigger unit 2121 and a first gating unit 2122. The signal synchronization submodule 211 includes a third flip-flop DFF7 and a third flip-flop DFF8. The clock inputs of the third flip-flops DFF7 and DFF8 are used to receive a second clock signal osc. The data input of the third flip-flop DFF7 is used to receive a write signal wen. The data input of the third flip-flop DFF8 is connected to the data output of the third flip-flop DFF7, and the data output of the third flip-flop DFF8 is used to output a first node signal S1. The first trigger unit 2121 includes a fourth flip-flop DFF9. The clock input of the third flip-flop DFF9 is used to receive the second clock signal osc, and the data input of the fourth flip-flop DFF9 is connected to the data output of the third flip-flop DFF8. The first gating unit 2122 includes a third NOT gate and a second AND gate. The input of the third NOT gate is connected to the data output of the fourth flip-flop DFF9. The first input of the second AND gate is connected to the output of the third NOT gate. The second input of the second AND gate is connected to the data output of the third flip-flop DFF8. The output of the second AND gate is used to output the gating signal gate.

[0122] First, we will explain the case where the trigger clock signal wck is switched from the second write clock signal wck_osc to the first write clock signal wck_scl. When the crystal oscillator 50 needs to be turned off, the first trigger module 31 receives the primary start enable signal en_tmp with an invalid level. The first three stages of the first flip-flops (DFF1~DFF3) perform three delay processing on the primary start enable signal en_tmp. The last two stages of the first flip-flops (DFF4~DFF5) perform two more delays on the primary start enable signal after the delay processing of the first three stages of the first flip-flops (DFF1~DFF3). Since the last two stages of the first flip-flops (DFF4~DFF5) receive the third clock signal osc_n, which is inverted from the second clock signal osc, the delay of the last two stages of the first flip-flops (DFF4~DFF5) can ensure that the target enable signal en output by the first gate module 12 switches from an effective level to an invalid level at the rising edge of the third clock signal osc_n, which is the falling edge of the second clock signal osc. This ensures that the second clock signal osc is turned off at the falling edge, avoiding clock glitches.

[0123] When the second node signal output by the first flip-flop DFF4 changes from an active level to an inactive level, the second input of the first AND gate receives an inactive signal. Therefore, the initial strobe signal sel output by the first AND gate changes from an active level to an inactive level. After a delay by the second flip-flop DFF6, the clock strobe signal wck_sel output by the second flip-flop DFF6 changes from an active level to an inactive level. Simultaneously, while the second flip-flop DFF6 outputs the inactive clock strobe signal wck_sel, the second node signal, after a delay by the first flip-flop DFF5, changes from an active level to an inactive level. Consequently, the target enable signal en changes from an active level to an inactive level. That is, the target enable signal en and the clock strobe signal wck_sel simultaneously change from an active level to an inactive level, thus achieving the switching of the trigger clock signal wck from the second write clock signal wck_osc to the first write clock signal wck_scl while simultaneously turning off the crystal oscillator 50.

[0124] Next, the case where the trigger clock signal wck switches from the first write clock signal wck_scl to the second write clock signal wck_osc will be explained. When the crystal oscillator 50 needs to be turned on, the first trigger module 31 receives the primary start enable signal en_tmp with an effective level. At the same time that the first trigger module 31 receives the primary start enable signal en_tmp with an effective level, the target enable signal en switches from an invalid level to an effective level. After four delays, the second node signal output by the first flip-flop DFF4 jumps from an invalid level to an effective level.

[0125] After the second node signal S2, output by the first flip-flop DFF4, transitions from an invalid to an active level, and the write signal transitions from an active to an invalid level, the first node signal S1 transitions to an invalid level after a two-stage delay. At this time, the third node signal remains active. Meanwhile, the second node signal S2 is active, the first node signal S1 is invalid, the historical clock strobe signal is invalid, and the first gating module outputs an active initial strobe signal sel. After a one-stage delay by the second flip-flop DFF6, the clock strobe signal wck_sel output by the second flip-flop DFF6 transitions from an invalid to an active level. This completes the switching of the trigger clock signal wck from the first write clock signal wck_scl to the second write clock signal wck_osc. During the subsequent start-up of the crystal oscillator 50, since the clock strobe signal wck_sel has been switched to an effective level, the first gate module 411 can continuously output the initial strobe signal sel at the first level, regardless of the level of the first node signal S1. The first trigger submodule 412 will also continuously output the clock strobe signal wck_sel at the first level until the crystal oscillator 50 is turned off.

[0126] In summary, the trigger clock generation circuit of this application has no special requirements for the output delay of the communication protocol frequency and the second clock signal (i.e., the internal clock) after they are enabled. It will not cause any missing writes or clock glitches, and is safe and reliable. After the configuration register trigger clock switches to the second write clock signal, the second write clock signal can directly identify and use the value of the configuration register without generating metastability risks. This application uses only one set of configuration registers. When the crystal oscillator is off, configuration can be performed without dynamically switching the crystal oscillator, saving circuit resources and further saving power consumption.

[0127] In one exemplary embodiment, this application provides a chip including a crystal oscillator, a configuration register, and a trigger clock generation circuit as described in any of the above embodiments.

[0128] In one exemplary embodiment, this application provides an electronic device including the chip described in the above embodiments.

[0129] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A trigger clock generation circuit, characterized in that, include: A clock gating module is used to perform gating processing on the received write signal according to the received first clock signal, so as to output the first write clock signal; A synchronous gating module is used to connect to a crystal oscillator and to perform synchronous gating processing on the received write signal according to a second clock signal provided by the crystal oscillator, so as to output a first node signal and a second write clock signal. An enable control module is used to connect to the crystal oscillator and to receive a primary enable signal and perform a delay on the primary enable signal to output a second node signal and a target enable signal. The target enable signal is used to control the on / off state of the crystal oscillator; The clock gating module is connected to the clock gating module, the synchronization gating module and the enable control module respectively, and is used to connect to the configuration register and output a trigger clock signal according to the first node signal, the second node signal, the third clock signal, the first write clock signal and the second write clock signal; The trigger clock signal includes either the first write clock signal or the second write clock signal, and the trigger clock signal is used to trigger the configuration register to perform a write operation.

2. The trigger clock generation circuit according to claim 1, characterized in that, The first node signal is the delayed version of the write signal; the second node signal is the delayed version of the primary enable signal; the target enable signal is related to the second node signal; and the second clock signal has the opposite level to the third clock signal. The clock gating module is also used to output the first write clock signal when the second node signal is invalid and the third clock signal is valid; The clock gating module is also used to switch from outputting the first write clock signal to outputting the second write clock signal when both the second node signal and the third clock signal OSC_N are at valid levels, and when the first node signal switches from valid level to invalid level for the first time during the crystal oscillator turn-on process. When the target enable signal is at an invalid level, the crystal oscillator is in the off state; when the target enable signal is at an active level, the crystal oscillator is in the on state.

3. The trigger clock generation circuit according to claim 1 or 2, characterized in that, The clock gating module includes: The signal generation module has multiple input terminals connected to the first target node in the synchronization gating module, the second target node in the enable control module, and the output terminal of the signal generation module, respectively. Another input terminal of the signal generation module is used to receive the third clock signal. The signal generation module is used to perform gating delay processing on the first node signal, the second node signal, the third clock signal, and the historical clock gating signal, and output the target clock gating signal. The clock gating module has two input terminals connected to the output terminals of the clock gating module and the synchronization gating module, respectively. The control terminal of the clock gating module is connected to the output terminal of the signal generation module. The output terminal of the clock gating module is used to connect to the clock input terminal of the configuration register. The clock gating module is used to output a trigger clock signal according to the target clock gating signal, the first write clock signal, and the second write clock signal.

4. The trigger clock generation circuit according to claim 3, characterized in that, The signal generation module includes: a first gating submodule and a first triggering submodule; The first gating submodule has multiple input terminals connected to the first target node, the second target node, and the data output terminal of the first trigger submodule, respectively; the first gating submodule is used to perform gating processing on the first node signal, the second node signal, and the historical clock gating signal to output an initial gating signal; The data input terminal of the first trigger submodule is connected to the output terminal of the first gating submodule; the clock input terminal of the first trigger submodule is used to receive a third clock signal; the first trigger submodule is used to perform delay processing on the initial gating signal according to the third clock signal and output the target clock gating signal.

5. The trigger clock generation circuit according to claim 1 or 2, characterized in that, The synchronous gating module includes: The signal synchronization module is used to receive the second clock signal and the write signal, and to perform synchronization gating processing on the write signal according to the second clock signal to output the first node signal and the gating signal. The clock gating module, connected to the signal synchronization module and the clock gating module, is used to receive the gating signal and the second clock signal to output the second write clock signal.

6. The trigger clock generation circuit according to claim 5, characterized in that, The signal synchronization module includes: A signal synchronization submodule, wherein the input terminal of the signal synchronization submodule is used to receive the second clock signal and the write signal; the signal synchronization submodule is used to perform synchronization processing on the write signal according to the second clock signal and output the first node signal; The second gating submodule has an input terminal for receiving the first node signal and the second clock signal; its output terminal is connected to the clock gating module; and it performs gating processing on the first node signal and the second clock signal to output the gating signal.

7. The trigger clock generation circuit according to claim 6, characterized in that, The second gating submodule includes: The first trigger unit has a data input terminal for receiving the first node signal and a clock input terminal for receiving a second clock signal. The first trigger unit is used to perform delay processing on the first node signal according to the second clock signal and output the third node signal. The first gating unit has a first input terminal connected to the data input terminal of the first trigger unit, a second input terminal connected to the data output terminal of the first trigger unit, and an output terminal connected to the clock gating module. The first gating unit is used to generate a gating signal based on the first node signal and the third node signal.

8. The trigger clock generation circuit according to claim 1 or 2, characterized in that, The enabling control module includes: The first trigger module is used to receive the primary start enable signal, the second clock signal and the third clock signal, and to perform delay processing on the primary start enable signal according to the second clock signal and the third clock signal; The first gating module, connected to the first triggering module, is used to output a target enable signal based on the primary enable signal and the primary enable signal after the delay processing.

9. The trigger clock generation circuit according to claim 8, characterized in that, The first triggering module includes: multiple cascaded first triggers; wherein, The data input terminal of the first stage first flip-flop is used to receive the primary enable signal, and the data output terminal of the i-th stage first flip-flop is connected to the data input terminal of the (i+1)-th stage first flip-flop; and the clock input terminal of the first n stages first flip-flops is used to receive the second clock signal, and the clock input terminal of the last m stages first flip-flops is used to receive the third clock signal; where n, m and i are all positive integers. The first n-stage first flip-flops are used to delay the primary start enable signal; the last m-stage first flip-flops are used to delay the primary start enable signal after the delay processing of the first n-stage first flip-flops, and are used to control the target enable signal to switch from an active level to an inactive level on the transition edge of the second clock signal.

10. A chip, characterized in that, The chip includes a crystal oscillator, a configuration register, and a trigger clock generation circuit as described in any one of claims 1-9.

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