Data reading method and device, chip product and electronic equipment
By optimizing the data reading method, the problem of low subinstruction access efficiency caused by bank conflicts in the GPU was solved, achieving more efficient multi-subinstruction processing, reducing the number of register reads, and improving processor performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-14
AI Technical Summary
When GPUs execute instructions, bank conflicts in the general-purpose register file lead to inefficient access to consecutive subinstructions, making it difficult for existing technologies to efficiently process multiple subinstructions.
By acquiring multiple sub-instructions from a batch instruction, a read request is sent for the first sub-instruction, and the target data is read based on the request. The data storage location of consecutive sub-instructions is determined, and data reading is optimized using a cache unit to reduce repeated requests to the target register.
It improves the efficiency of processing multiple subinstructions, reduces the number of reads of the target register, reduces the probability of bank conflicts and latency, and improves processor performance.
Smart Images
Figure CN121858162A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a data reading method, apparatus, chip product, electronic device, and computer program product. Background Technology
[0002] When executing instructions, the current Graphics Processing Unit (GPU) needs to break down a main instruction into several sub-instructions, and each sub-instruction reads the source register independently.
[0003] Internally, the GPU divides the General Purpose Register File (GPR File) into multiple memory banks, and each bank can only serve a read port once per clock cycle. When consecutive sub-instructions access the same bank, a bank conflict occurs. Summary of the Invention
[0004] This application provides a data reading method, apparatus, chip product, electronic device, and computer program product. The technical solutions provided by this application include the following aspects.
[0005] According to one aspect of the embodiments of this application, a data reading method is provided, the method comprising: Retrieve multiple sub-instructions contained in a batch instruction; Send a first read request to the target register for the first of the plurality of sub-instructions; Based on the first read request, read the target read data of the first sub-instruction from the target register; The target read data of all subsequent sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register. The target read data of the other sub-instructions is determined based on the target read data read by the first read request.
[0006] According to one aspect of the embodiments of this application, a data reading device is provided, the device comprising: The acquisition module is used to acquire multiple sub-instructions contained in a batch instruction; The sending module is used to send a first read request to the target register in response to the first sub-instruction among the plurality of sub-instructions; The read module is configured to read the target read data of the first sub-instruction from the target register based on the first read request; The determining module is used to determine that the target read data of all other sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register, and to determine the target read data of the other sub-instructions based on the target read data read by the first read request.
[0007] In one possible implementation, the determining module is configured to determine, based on preset parameters, that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0008] In one possible implementation, the preset parameters include at least one of the following: the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions among the plurality of sub-instructions, and the storage format of the target read data.
[0009] In one possible implementation, the determining module is configured to determine the register offset of the target read data of the other sub-instructions based on the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions in the plurality of sub-instructions, and the storage format of the target read data; In response to the fact that the register offsets of the target read data corresponding to the first sub-instruction and the other sub-instructions are all consistent, it is determined that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0010] In one possible implementation, the reading module is further configured to: store the target read data of the first sub-instruction read based on the first read request into a preset cache unit; The preset cache identifier in the cache unit is set as the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
[0011] In one possible implementation, the determining module is used to detect the cache identifier in a preset cache unit; In response to the cache identifier being set to the first identifier, the target read data of the first read request is read from the cache unit as the target read data of the other sub-instructions; The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
[0012] In one possible implementation, the other sub-instructions include a second sub-instruction. The determining module is further configured to determine that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, and to set the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to a second identifier. The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction. In response to the second sub-instruction, a second read request is sent to the register containing the target data to be read from the second sub-instruction.
[0013] According to one aspect of the embodiments of this application, a chip product is provided, the chip product comprising: The acquisition module is used to acquire multiple sub-instructions contained in a batch instruction; The sending module is used to send a first read request to the target register in response to the first sub-instruction among the plurality of sub-instructions; The read module is configured to read the target read data of the first sub-instruction from the target register based on the first read request; The determining module is used to determine that the target read data of all other sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register, and to determine the target read data of the other sub-instructions based on the target read data read by the first read request.
[0014] In one possible implementation, the determining module is configured to determine, based on preset parameters, that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0015] In one possible implementation, the preset parameters include at least one of the following: the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions among the plurality of sub-instructions, and the storage format of the target read data.
[0016] In one possible implementation, the determining module is configured to determine the register offset of the target read data of the other sub-instructions based on the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions in the plurality of sub-instructions, and the storage format of the target read data; In response to the fact that the register offsets of the target read data corresponding to the first sub-instruction and the other sub-instructions are all consistent, it is determined that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0017] In one possible implementation, the reading module is further configured to: store the target read data of the first sub-instruction read based on the first read request into a preset cache unit; The preset cache identifier in the cache unit is set as the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
[0018] In one possible implementation, the determining module is used to detect the cache identifier in a preset cache unit; In response to the cache identifier being set to the first identifier, the target read data of the first read request is read from the cache unit as the target read data of the other sub-instructions; The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
[0019] In one possible implementation, the other sub-instructions include a second sub-instruction. The determining module is further configured to determine that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, and to set the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to a second identifier. The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction. In response to the second sub-instruction, a second read request is sent to the register containing the target data to be read from the second sub-instruction.
[0020] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising: one or more processors; A memory having stored one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the data reading method described above; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.
[0021] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, which, when executed by a processor, implements the above-described data reading method.
[0022] The technical solution provided in this application can bring the following beneficial effects: This application obtains multiple sub-instructions contained in a batch instruction; sends a first read request to the target register for the first sub-instruction among the multiple sub-instructions; reads the target read data of the first sub-instruction from the target register based on the first read request; determines that the target read data of the other consecutive sub-instructions following the first sub-instruction are stored in the target register, and determines the target read data of the other sub-instructions based on the target read data read based on the first read request. In the process of processing multiple sub-instructions, there is no need to repeatedly and frequently request data from the target register. The target read data read directly based on the first read request can be used to process the other consecutive sub-instructions following the first sub-instruction, reducing the number of read requests to the target register and improving the efficiency of processing multiple sub-instructions. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the structure of a processor provided in one embodiment of this application; Figure 2 This is a flowchart of a data reading method provided in one embodiment of this application; Figure 3 This is an overall flowchart of a data reading method provided in one embodiment of this application; Figure 4 This is a schematic diagram of the structure of a data reading device provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of a chip provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of a server provided in one embodiment of this application. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0025] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0026] First, a brief introduction to the terms used in the embodiments of this application: Registers: Fast storage units inside the processor, directly accessed by the processor, used to store data and instructions. Each register has a fixed size, such as 32 bits or 64 bits, and the register number (register address in this application) must be explicitly specified each time it is accessed.
[0027] Operand Cache: Operand cache unit, accessed indirectly by the processor, without the processor needing to explicitly specify the cache location.
[0028] Register offset: Represents the offset from the beginning of a register. It helps the processor quickly locate and access data in the register without having to search from the beginning every time.
[0029] BurstSize: The number of data elements that a Burst instruction needs to process consecutively during one execution. For example, the 4 in cvt.burst4 is BurstSize.
[0030] Data type conversion (Cvt) instruction: Converts the source operand from one numeric format to another and outputs it to a register.
[0031] A bank in a register is a physical structure that horizontally divides a register file into several smaller storage units.
[0032] Arithmetic-specific pipeline (Convert Pipeline, CVT Pipeline): A processing unit in the GPU used to perform data format conversion operations.
[0033] In related technologies, shader code will have the following instruction pattern: CVT.F32.FP8R1, R0.E0 CVT.F32.FP8R2,R0.E1 CVT.F32.FP8R3, R0.E2 CVT.F32.FP8R4, R0.E3 The shader pattern described above means converting the lower 8 bits of R0 from FP8 format to FP32 format and storing the result in register R1. Similarly, it converts the second 8 bits of R0 from FP8 to FP32 format and stores the result in register R2, and so on. In instruction encoding, this can be compressed into a single instruction: CVT.F32.FP8.BURST4, R1, R0, by adding BURST to the instruction encoding. The CVT instruction encoding has only one source code (src). The number of bits in the source code (fmt) varies depending on the format conversion. Some fmts are less than a single dword, so the source code of the burst instruction sequence is packed into a single dword. Different instructions within a burst require different source code locations within a register. Currently, modern GPUs use a multi-bank storage architecture for their general-purpose registers, with access restrictions for each bank: only one general-purpose register read operation can be completed within the same cycle. This can become a performance bottleneck in instruction-intensive scenarios.
[0034] To further illustrate the technical solutions provided in the embodiments of this application, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on conventional or non-inventive effort. For steps that do not logically have a necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. In actual processing or when the control device executes the method, it may be executed sequentially or in parallel according to the method shown in the embodiments or drawings.
[0035] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0036] Figure 1This illustration shows a schematic diagram of a processor according to an embodiment of this application. The cache identifier is represented by "reuseflag", with the first identifier being 1 and the second identifier being 0. The data format required for processing sub-instruction 1 and sub-instruction 2 is 'a' bits. The processor is used to process data with a bit count less than or equal to 'b', where 'a' and 'b' are powers of 2. For example, the processor includes: an instruction issuing unit 101, an instruction processing unit 102, an operand cache unit 103, and at least one register 104. The instruction issuing unit 101 is used to split a burst instruction into four sub-instructions: sub-instruction 1, sub-instruction 2, sub-instruction 3, and sub-instruction 4, and to issue the four sub-instructions sequentially to the instruction processing unit 102. The four sub-instructions include at least two sub-instructions (e.g., sub-instruction 1 and sub-instruction 2) that use different data in the same register. The instruction processing unit 102 is used to, when processing sub-instruction 1, since reuse... When the flag value is 0, it means that the operand cache unit 103 does not cache the data for processing subinstruction 1. A first read request for processing data is sent to the first register in at least one register. The processing data is the data required to process subinstruction 1. The first register is a register in at least one register that stores the processing data. The operand cache unit 103 is used to temporarily cache the processing data read from the first register during the process of subinstruction 1 by the instruction processing unit 102. Subinstruction 1 is processed according to the processing data cached in the operand cache unit 103.
[0037] The instruction processing unit 102 is configured to, during the processing of subinstruction 1, calculate the first product of the burst-id corresponding to subinstruction 1 and a; determine the first ratio of the first product to b; round down the first ratio to obtain a first rounding ratio; sum the rounding ratio with the start register number to obtain the register offset of the target read data corresponding to the first subinstruction, wherein the start register number is the number of the start register in at least one register, and the start register is used to store the data required for processing the start subinstruction in the burst instruction; calculate the second product of the burst-id corresponding to subinstruction 2 and a; determine the second ratio of the second product to b; round down the second ratio to obtain a second rounding ratio; sum the second rounding ratio with the start register number to obtain the register offset of the target read data corresponding to other subinstructions; if the register offset of the target read data corresponding to the first subinstruction is the same as the register offset of the target read data corresponding to other subinstructions, set the reuse flag to 1; when processing subinstruction 2, since the reuse flag is set to 1, subinstruction 2 is processed according to the processing data cached in the operand cache unit 103.
[0038] like Figure 1As shown, this application embodiment provides a data reading method, which can be executed by a computer device, which can be a terminal device or a server; this application embodiment does not limit the specific type of computer device. Figure 2 As shown, the data reading method provided in this application embodiment may include the following steps 201 to 204.
[0039] In step 201, the batch instruction contains multiple sub-instructions.
[0040] In this embodiment of the application, obtaining multiple sub-instructions contained in a batch instruction includes: splitting the batch instruction into multiple sub-instructions based on data such as predicates and resource table entries; and obtaining the multiple sub-instructions in sequence without interruption.
[0041] Among them, batch commands include the burst command.
[0042] In this embodiment of the application, the batch instruction is split into multiple sub-instructions, including: splitting the batch instruction into multiple sub-instructions according to the Burst Size.
[0043] For example, suppose there is a CVT instruction of the form: cvt.burst4.F32.FP6, R1, R0. If the source data format of the burst instruction has less than 32 bits, it means that the original data before conversion of adjacent CVT burst instructions is packed together. The number of instructions packed depends on the number of bits in the source data format. If the source data format has 16 bits, the original data before conversion can only be packed into two instructions. If the source data format has 8 bits or 6 bits, the original data before conversion can be packed into four CVT instructions. If the source data format has 4 bits, the original data before conversion can be packed into eight CVT instructions. However, the maximum burst size supported by CVT is burst4. When splitting a burst instruction, it is divided into multiple sub-instructions according to the number of packed instructions.
[0044] Retrieve multiple sub-instructions in sequence without interruption, that is, retrieve multiple sub-instructions according to the element labels corresponding to the order in which they were split.
[0045] For example, multiple sub-instructions are sequentially defined as 0, 1, 2...x. During the process of obtaining multiple sub-instructions, the multiple sub-instructions are obtained in the order of 0, 1, 2...x, and no other instructions can be inserted in between.
[0046] Fetching multiple subinstructions sequentially and without interruption ensures that the order of the subinstructions is not disrupted, reducing bank conflicts in registers.
[0047] In this embodiment of the application, the method further includes: determining that the obtained sub-instruction belongs to a batch instruction if the burst-id corresponding to the obtained sub-instruction is not 0.
[0048] If the burst-id corresponding to the obtained sub-instruction is not 0, it can be understood that the process first determines whether the obtained sub-instruction is derived from a batch instruction. If the burst-id corresponding to the obtained sub-instruction is not 0, it proves that the obtained sub-instruction is derived from a batch instruction. If the burst-id corresponding to the obtained sub-instruction is 0, it proves that the obtained sub-instruction is not derived from a batch instruction.
[0049] In step 202, a first read request is sent to the target register for the first of a plurality of subinstructions.
[0050] The first subinstruction is any subinstruction other than the last subinstruction among multiple subinstructions.
[0051] The target register stores instruction-related data for processing the first subinstruction.
[0052] The first read request is a control signal used to trigger a target register read operation. After the instruction is decoded, the decoding unit will send the first read request to the register file according to the register index in the instruction.
[0053] In step 203, the target read data of the first sub-instruction is read from the target register based on the first read request.
[0054] The target read data is the data content extracted from the target register.
[0055] In this embodiment of the application, reading the target read data of the first sub-instruction from the target register based on the first read request includes: reading the target read data of the first sub-instruction from the target register in stages based on the first read request; or, reading the target read data of the first sub-instruction from the target register in batches based on the first read request.
[0056] In step 204, it is determined that the target read data of all subsequent sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register. The target read data of the other sub-instructions is determined based on the target read data read by the first read request.
[0057] The subsequent subinstructions following the first subinstruction can be understood as the other subinstructions that are adjacent to and consecutive to the first subinstruction among multiple subinstructions.
[0058] In a multi-subinstruction system, the target data for all subsequent subinstructions following the first subinstruction is stored in the same target register as the target data for the first subinstruction. This means that in multiple subinstructions, adjacent instructions use the same data in the target register, thereby optimizing and saving the number of requests. In other words, a single read request can process multiple subinstructions.
[0059] It should be noted that the target data read by subsequent sub-instructions can be the same as the target data read by the first sub-instruction, which is stored in the target register, or it can be different from the target data read by the first sub-instruction, as long as they are all stored in the target register.
[0060] For example, the first subinstruction is the i-th subinstruction among multiple subinstructions, and the other subinstructions are the (i+1)-th subinstructions among multiple subinstructions, where i is a positive integer. The target data to be read from the i-th subinstruction is stored in the first 8 bits of register 6 (i.e., the target register), and the target data to be read from the (i+1)-th subinstruction is stored in the last 8 bits of register 6. In this case, it can be understood that the target data to be read from the i-th subinstruction and the target data to be read from the (i+1)-th subinstruction are different data in the same register (register 6).
[0061] In a set of multiple subinstructions, the target read data of all subsequent subinstructions following the first subinstruction are stored in the target register, so that at least two of the subinstructions do not need to issue multiple read requests to the target register during processing. When processing other subinstructions, the data read from the target register based on the first read request can be used directly.
[0062] In the process of processing multiple sub-instructions, the embodiments of this application do not need to repeatedly request data from the target register. Based on the target read data directly read from the first read request, the continuous other sub-instructions after the first sub-instruction can be processed, which reduces the number of read requests to the target register and improves the efficiency of processing multiple sub-instructions.
[0063] The method for reading target data in other sub-instructions.
[0064] In some embodiments, after reading the target read data of the first sub-instruction from the target register based on the first read request, the method further includes: storing the target read data of the first sub-instruction read based on the first read request into a preset cache unit; setting a preset cache identifier in the cache unit to a first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports reuse of other sub-instructions.
[0065] A cache identifier is a single-bit status flag used to indicate whether the register data corresponding to that entry can be reused in the currently processed subinstruction without needing to request data from other registers. Specifically, the first identifier indicates that the target read data for processing other subinstructions can be directly obtained from the cache unit.
[0066] In embodiments of this application, determining the target read data for other sub-instructions based on the target read data read by the first read request includes: detecting a cache identifier in a preset cache unit; in response to the cache identifier being set to a first identifier, reading the target read data read by the first read request from the cache unit as the target read data for other sub-instructions; wherein the first identifier is used to indicate that the cache unit stores target read data that supports reuse of other sub-instructions.
[0067] The first identifier indicates that the data in the register corresponding to this identifier has been fully loaded into the cache unit by the preceding sub-instruction (the first sub-instruction) in the previous clock cycle. When processing other sub-instructions, the data can be read directly from the cache unit's reuse target without having to occupy the register read port again to request data from the register.
[0068] By reading the target read data from the first read request from the cache unit as the target read data for other sub-instructions, it is possible to avoid repeatedly and frequently requesting data from the target register. Based on the target read data from the first read request, the target read data is directly reused in the cache unit to process other consecutive sub-instructions after the first sub-instruction, thus reducing the number of read requests to the target register.
[0069] When the cache identifier is the first identifier, data loading and cache filling can be completed with only one register port access. Subsequent sub-instructions reuse the cached data, which significantly reduces the register port occupancy rate and the probability of bank conflicts.
[0070] In embodiments of this application, the method further includes: determining that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register; setting the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to a second identifier, wherein the second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction; and sending a second read request to the register where the target read data of the second sub-instruction is located for the second sub-instruction.
[0071] The second identifier indicates that the cache unit does not store the target read data for other sub-instructions to be processed. In other words, the target read data corresponding to the first sub-instruction read in the target register is not reusable and data needs to be requested from other registers besides the target register. That is, the data in the register corresponding to the second identifier has not yet been loaded into the cache unit, or although it was loaded, it has been invalidated due to a write-back operation.
[0072] For example, taking the data cache unit as the operand cache, the cache identifier is represented by the operand cache, and the first identifier is 1 and the second identifier is 0. If consecutive sub-instructions need to access the same register, when the register is read for the first time, the data is cached in the cache line and the reuse flag is set to 1. If other subsequent sub-instructions hit the same register and the cache identifier is 1, the cache content is directly reused without having to access other registers except the target register again, thereby reducing the number of register read port requests (Burst Size) and significantly reducing latency and power consumption.
[0073] In embodiments of this application, the method further includes: if the cache identifier is a second identifier, determining, in at least one register, the register where the target read data of the second sub-instruction is located.
[0074] It should be noted that the method for determining the register where the target data of the second sub-instruction is located in at least one register will be explained in detail in the following section on "Register Offset of Target Data for the First Sub-instruction", and will not be repeated here.
[0075] When processing the second subinstruction, whether the data is obtained by reading the register where the target data is located through the second subinstruction and then cached in the cache unit, or the target data is read directly from the cache unit by the first read request, the cache unit needs to be marked with a cache identifier when the first subinstruction is completed. This is so that when processing other subinstructions, the cache identifier can be used to determine whether the data in the cache unit can be directly reused.
[0076] In the embodiments of this application, determining that the target read data of all other sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register includes: determining, based on preset parameters, that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0077] The preset parameters are pre-set parameters used to determine the register to which the target data of other sub-instructions belongs, and the register to which the target data of the first sub-instruction belongs is the target register.
[0078] In the embodiments of this application, the preset parameters include at least one of the following: the register offset of the target read data of the first sub-instruction, the sorting identifier of other sub-instructions in multiple sub-instructions, and the storage format of the target read data.
[0079] The register offset of the target data read by the first subinstruction can be understood as the register offset corresponding to the register of the target data read by the first subinstruction. For example, the register offset is the address or identifier of the register of the target data read by the first subinstruction.
[0080] The sorting identifier of other sub-instructions in multiple sub-instructions can be understood as the burst_id of other sub-instructions in multiple sub-instructions.
[0081] The storage format of the target read data can be understood as the data format in which the target read data is stored in a register.
[0082] In this embodiment, determining that the target read data of other sub-instructions and the target read data of the first sub-instruction are both stored in the target register based on preset parameters includes: determining the register offset of the target read data of other sub-instructions based on the register offset of the target read data of the first sub-instruction, the sorting identifier of other sub-instructions in multiple sub-instructions, and the storage format of the target read data; and determining that the target read data of other sub-instructions and the target read data of the first sub-instruction are both stored in the target register in response to the fact that the register offsets of the target read data corresponding to the first sub-instruction and the other sub-instructions are consistent.
[0083] The register offset of the target data read by other sub-instructions can be understood as the address or identifier of the register of the target data read by other sub-instructions; the register offset of the target data read by the first sub-instruction can be understood as the address or identifier of the register of the target data read by the first sub-instruction.
[0084] The address of a register is used to uniquely address the value of any register in at least one register. The address of a register is fixed before the burst instruction is issued and remains unchanged throughout the lifetime of the subinstruction.
[0085] Register identifiers are symbols or numbers used to uniquely identify any register in assembly language or machine code. For example, register identifiers R0, R1, ..., Rx.
[0086] The process of calculating the register offset of the target data to be read for the first subinstruction and the register offset of the target data to be read for the other subinstructions is as follows: If the register offset of the target data to be read for the first subinstruction is the same as the register offset of the target data to be read for the other subinstructions, it proves that the data of the cache unit can be reused during the processing of other subinstructions, reducing the number of accesses to the register port; if the register offset of the target data to be read for the first subinstruction is different from the register offset of the target data to be read for the other subinstructions, it proves that the register offset of the target data to be read for the other subinstructions needs to be located in at least one register in advance, and a read request needs to be made.
[0087] It should be noted that the register offset of the target data read for the first subinstruction is the same as the register offset of the target data read for the other subinstructions. This can be understood as the address or identifier of the register of the target data read for the first subinstruction being the same as the address or identifier of the register of the target data read for the other subinstructions. That is, the data of the register of the target data read for the first subinstruction temporarily cached in the cache unit can be reused when processing other subinstructions without having to send a data request to the register again.
[0088] If the register offset of the target data read by the first subinstruction is the same as the register offset of the target data read by other subinstructions, the cache identifier is marked as the first identifier. Multiple subinstructions can be served with only one register port, which significantly reduces port occupancy and bank conflict probability, while maintaining data correctness.
[0089] The register offset of the target data read by the first subinstruction is different from the register offset of the target data read by the other subinstructions. This can be understood as the address or identifier of the register of the target data read by the first subinstruction being different from the address or identifier of the register of the target data read by the other subinstructions. That is, the register of the target data read by the first subinstruction is two registers. The target data read by the first read request temporarily cached in the cache unit cannot be reused when processing other subinstructions. It is necessary to send a data request to the register of the target data read by the other subinstructions in at least one register, and then cache it in the cache unit to process other subinstructions.
[0090] If the register offset of the target data read by the first subinstruction is different from the register offset of the target data read by other subinstructions, the cache flag is marked as the second flag. This can be understood as follows: after processing the first subinstruction, the target data read by the first read request temporarily cached in the cache unit has become invalid. It is necessary to request data from the register of the target data read by other subinstructions and cache it in the cache unit. After caching, the cache flag is marked as the first flag again for use by subsequent subinstructions that may hit.
[0091] By calculating the register offset of the target data read by the first subinstruction and the register offset of the target data read by other subinstructions, it intelligently determines whether the target data read by other subinstructions is the same as the target data read by the first subinstruction, and whether they are all stored in the same 32-bit register (dword).
[0092] The following explains how to calculate the register offset of the target data read for the first subinstruction and the register offset of the target data read for other subinstructions.
[0093] It should be noted that when the first subinstruction is the first of a set of subinstructions, the register offset of the target data to be read from the first subinstruction can be understood as the starting register number among the multiple registers. In this case, the register offsets of the target data to be read from the other subinstructions can be determined directly based on the register offset of the target data to be read from the first subinstruction, the order identifier of the other subinstructions among the multiple subinstructions, and the storage format of the target data to be read. The starting register number refers to the starting position of the data in the general-purpose register. In the batch instruction sequence, the cvtburst instruction code specifies the initial register offset of the target data to be read from the first subinstruction.
[0094] When the first subinstruction is not the first subinstruction among multiple subinstructions, it is necessary to first calculate the register offset of the target data to be read from the first subinstruction. This is done by determining the register offset of the target data to be read from the first subinstruction based on the starting register number, the order identifier of the first subinstruction among the multiple subinstructions, and the storage format of the target data. Then, based on the register offset of the target data to be read from the first subinstruction, the order identifier of the other subinstructions among the multiple subinstructions, and the storage format of the target data, the register offsets of the target data to be read from the other subinstructions are determined. Therefore, this application does not restrict whether the first subinstruction is the first subinstruction among multiple subinstructions.
[0095] The following section uses the example of the first subinstruction being the first among multiple subinstructions to explain in detail how to calculate the register offset for the target data read by other subinstructions.
[0096] In this embodiment, the storage format of the target read data corresponding to other sub-instructions is 'a' bits. The processor is used to process data with a bit count less than or equal to 'b', where 'a' and 'b' are both powers of 2. The processor calculates the first product of the sorting identifier of other sub-instructions among multiple sub-instructions and 'a'. It determines the first ratio of the first product to 'b'. The processor rounds down the first ratio to obtain a first rounding ratio. The processor sums the rounding ratio with the register offset of the target read data of the first sub-instruction to obtain a first value.
[0097] When processing burst instructions, the storage format of the target data to be read for each subinstruction, as well as the number of bits of data that the processor uses to process, are predetermined.
[0098] The storage format of the target read data is the bit width and encoding method of the target read data.
[0099] For example, the storage format of the target read data corresponding to other sub-instructions is represented by "src_fmt", where src_fmt = 16 bits, indicating that the storage format of the target read data corresponding to other sub-instructions occupies 16 bits.
[0100] burst-id is the sorting identifier in a burst instruction (i.e., batch instruction) sequence: In a burst instruction (such as burst4), there are multiple sub-instructions (e.g., burst0, burst1, burst2, burst3). burst-id is the sorting identifier of these sub-instructions.
[0101] A double word (Dword) is a 32-bit double word, typically the size of a full register. For example, in the 16-bit era, 1 word = 16 bits, therefore 1 Dword = 32 bits = 4 bytes.
[0102] burst0 occupies the lower 16 bits of a dword: the first 16 bits of data are placed in the lower 16 bits of the register. burst1 occupies the higher 16 bits of a dword: the second 16 bits of data are immediately placed in the higher 16 bits of the same register. Thus, a 32-bit register can store exactly two 16-bit data entries. burst2 occupies the lower 16 bits of the next dword. Since the first 32-bit register (R2) is already full of burst0 and burst1 data, the data for burst2 is placed in the lower 16 bits of the next 32-bit register (R3). burst3 occupies the higher 16 bits of the next dword, and the data for burst3 is also placed in the higher 16 bits of the same register (R3).
[0103] For example, the register offset of the target data read by the first sub-instruction is represented by "Src registeroffset". Src register init offset=2 indicates that the register offset of the target data read by the first sub-instruction in the burst instruction is numbered 2 in at least one register.
[0104] Optionally, the register offset for the target data to be read is calculated using the following formula.
[0105] Src register offset=init_offset+burst_id*src_fmt / 32 formula (1) Wherein, Src register offset represents the register offset of the target data read by other sub-instructions, init_offset represents the register offset of the target data read by the first sub-instruction, burst_id represents the sorting identifier of other sub-instructions among multiple sub-instructions, src_fmt represents the storage format of the target data read, 32 represents the number of bits used by the processor for processing, burst_id*src_fmt represents the first product, and burst_id*src_fmt / 32 represents the first ratio.
[0106] It should be noted that rounding down the first ratio to obtain the rounding ratio can be understood as omitting the decimal part when the first ratio has a decimal part, and only taking the integer part. For example, if the first ratio is 0.5, then the rounding down of the first ratio will result in a rounding ratio of 0.
[0107] For example, taking Src register init offset=2, src_fmt=16bit, and the processor uses 32 bits for processing, that is, the register offset of the target data read by the first sub-instruction is 2, and the storage format a bits of the target data read are 16 bits; the burst_id of the first sub-instruction is 0, the burst_id of the second sub-instruction in the burst instruction is 1, the burst_id of the third sub-instruction in the burst instruction is 2, and the burst_id of the fourth sub-instruction in the burst instruction is 3.
[0108] According to formula (1), the src register offset of Burst0 = 2 + 0 * 16 / 32 = 2; Burst1's src register offset=2+1*16 / 32=2; Burst2's src register offset=2+2*16 / 32=3; Burst3's src register offset=2+3*16 / 32=3.
[0109] Therefore, the data for processing the Burst0 subinstruction corresponds to register 2, the data for processing the Burst1 subinstruction corresponds to register 3, and the data for processing the Burst3 subinstruction corresponds to register 3. That is, after the data for processing the Burst0 subinstruction is cached in the cache unit, the cache flag is marked as 1. When processing the Burst1 subinstruction, data can be directly retrieved from the cache unit. When processing the Burst1 subinstruction, the cache flag needs to be marked as 0. When processing the Burst2 subinstruction, data is requested from register 3, the retrieved data is cached in the cache unit, and then the cache flag is marked as 1. When processing the Burst3 subinstruction, data can be directly retrieved from the cache unit.
[0110] In summary, it should be noted that when the cache identifier is the second identifier, it is necessary to request processing data from any register in at least one register. This application does not restrict the processing after requesting the processing data from any register. The processing data can be temporarily stored in the cache unit, and the processing data can be retrieved from the cache unit to process the current sub-instruction; or, the processing data can be directly used to process the current sub-instruction.
[0111] Optionally, in the last sub-instruction of the currently processed sub-instruction, which is the burst instruction, the cache identifier is marked as the second identifier, regardless of whether the data in the temporary cache register is used up.
[0112] In this application, the software optimizes register read requests, mitigating bank conflicts; it improves the execution efficiency of the burst instruction, eliminating the need to fetch data from registers for all subinstructions, thus reducing the number of register requests; and it shortens the latency of the burst instruction by breaking it down into n subinstructions, completing the execution of each subinstruction in fewer clock cycles. Since the order of subinstructions is fixed, when the cache flag is marked as the first flag, the current subinstruction can directly reuse the data already read from the register by the previous subinstruction, without needing to occupy the register read port again. In this way, the subinstruction shares the same data as the previous subinstruction, equivalent to "directly fetching from the previous instruction," eliminating the latency of a second register read, thereby reducing the overall register read latency.
[0113] See Figure 3 The diagram shows the overall flowchart of a data reading method.
[0114] Step 1: Obtain the multiple sub-instructions contained in the batch instruction.
[0115] Step 2: Send the first read request to the target register for the first subinstruction among multiple subinstructions.
[0116] Step 3: Read the target read data of the first sub-instruction from the target register based on the first read request.
[0117] Step 4: Store the target read data based on the first sub-instruction read from the first read request into a preset cache unit.
[0118] Step 5: Set the preset cache identifier in the cache unit to the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0119] Step 6: Based on the register offset of the target data read by the first sub-instruction, the sorting identifier of other sub-instructions in multiple sub-instructions, and the storage format of the target data read, determine the register offset of the target data read by other sub-instructions.
[0120] Step 7: In response to the fact that the register offsets of the target read data corresponding to the first sub-instruction and the other sub-instructions are consistent, it is determined that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0121] Step 8: Detect the cache identifier in the preset cache unit.
[0122] Step 9: In response to the cache identifier being set to the first identifier, read the target read data from the cache unit for the first read request as the target read data for other sub-instructions.
[0123] The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0124] Step 10: Determine that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, and set the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to the second identifier.
[0125] The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction.
[0126] Step 11: For the second sub-instruction, send a second read request to the register where the target data of the second sub-instruction is located.
[0127] See Figure 4 This application provides a schematic diagram of a data reading device, which includes: The acquisition module 401 is used to acquire multiple sub-instructions contained in a batch instruction; Sending module 402 is used to send a first read request to the target register in response to the first sub-instruction among multiple sub-instructions; Read module 403 is used to read the target read data of the first sub-instruction from the target register based on the first read request; The determination module 404 is used to determine that the target read data of the other sub-instructions following the first sub-instruction in a plurality of sub-instructions are both stored in the target register, and to determine the target read data of the other sub-instructions based on the target read data read by the first read request.
[0128] In one possible implementation, the determining module 404 is used to determine, based on preset parameters, that the target read data of other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0129] In one possible implementation, the preset parameters include at least one of the following: the register offset of the target data to be read by the first subinstruction, the sorting identifier of other subinstructions among multiple subinstructions, and the storage format of the target data to be read.
[0130] In one possible implementation, the determining module 404 is used to determine the register offset of the target read data of other sub-instructions based on the register offset of the target read data of the first sub-instruction, the sorting identifier of other sub-instructions in multiple sub-instructions, and the storage format of the target read data. Since the register offsets of the target read data corresponding to the first subinstruction and the other subinstructions are consistent, it is determined that the target read data of the other subinstructions and the target read data of the first subinstruction are both stored in the target register.
[0131] In one possible implementation, the reading module 403 is further configured to: store the target read data based on the first sub-instruction read from the first read request into a preset cache unit; Set the preset cache identifier in the cache unit to the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0132] In one possible implementation, the determining module 404 is used to detect the cache identifier in a preset cache unit; In response to the cache identifier being set to the first identifier, the target read data for the first read request is read from the cache unit and used as the target read data for other sub-instructions; The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0133] In one possible implementation, the other sub-instructions include a second sub-instruction. The determining module 404 is further configured to determine that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, and to set the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to the second identifier. The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction. For the second subinstruction, a second read request is sent to the register containing the data to be read from the target of the second subinstruction.
[0134] It should be understood that the above-described apparatus is only illustrated by the division of the functional modules described above when implementing its functions. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.
[0135] See Figure 5 This application provides a schematic diagram of a chip structure, which includes: The acquisition module 501 is used to acquire multiple sub-instructions contained in a batch instruction; Sending module 502 is used to send a first read request to the target register in response to the first sub-instruction among multiple sub-instructions; Read module 503 is used to read the target read data of the first sub-instruction from the target register based on the first read request; The determination module 504 is used to determine that the target read data of the other sub-instructions following the first sub-instruction in a plurality of sub-instructions are both stored in the target register, and to determine the target read data of the other sub-instructions based on the target read data read by the first read request.
[0136] In one possible implementation, the determining module 504 is used to determine, based on preset parameters, that the target read data of other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
[0137] In one possible implementation, the preset parameters include at least one of the following: the register offset of the target data to be read by the first subinstruction, the sorting identifier of other subinstructions among multiple subinstructions, and the storage format of the target data to be read.
[0138] In one possible implementation, the determining module 504 is used to determine the register offset of the target read data of other sub-instructions based on the register offset of the target read data of the first sub-instruction, the sorting identifier of other sub-instructions in multiple sub-instructions, and the storage format of the target read data. Since the register offsets of the target read data corresponding to the first subinstruction and the other subinstructions are consistent, it is determined that the target read data of the other subinstructions and the target read data of the first subinstruction are both stored in the target register.
[0139] In one possible implementation, the reading module 503 is further configured to: store the target read data based on the first sub-instruction read from the first read request into a preset cache unit; Set the preset cache identifier in the cache unit to the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0140] In one possible implementation, the determining module 504 is used to detect the cache identifier in a preset cache unit; In response to the cache identifier being set to the first identifier, the target read data for the first read request is read from the cache unit and used as the target read data for other sub-instructions; The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of other sub-instructions.
[0141] In one possible implementation, the other sub-instructions include a second sub-instruction. The determining module 504 is further configured to determine that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, and to set the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction to the second identifier. The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction. For the second subinstruction, a second read request is sent to the register containing the data to be read from the target of the second subinstruction.
[0142] It should be understood that the chip described above is only an example of the division of functional modules to implement its functions. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the chip can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the chip and method embodiments provided above belong to the same concept, and their specific implementation process and beneficial effects are detailed in the method embodiments, and will not be repeated here.
[0143] In an exemplary embodiment, an electronic device is also provided, comprising a processor and a memory storing at least one computer program. The at least one computer program is loaded and executed by one or more processors to enable the electronic device to implement any of the aforementioned data reading methods applied to the processor. The electronic device can be a server or a terminal device. The structures of servers and terminal devices will be described below.
[0144] Figure 6 This is a schematic diagram of a server structure provided in an embodiment of this application. The server can vary significantly due to differences in configuration or performance. It may include one or more Central Processing Units (CPUs) 601 and one or more memories 602. The one or more memories 602 store at least one computer program, which is loaded and executed by the one or more processors 601 to enable the server to implement the data reading methods provided in the various method embodiments described above. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated upon here.
[0145] In an exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program that is loaded and executed by a processor to enable the computer to implement any of the above-described data reading methods applied to the processor.
[0146] In one possible implementation, the aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.
[0147] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions that are loaded and executed by a processor to enable the computer to implement any of the data reading methods applied to the processor described above.
[0148] Optionally, all information (including but not limited to the contents of each sub-instruction), data (including but not limited to data used for analysis, stored data, displayed data), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data shall comply with the relevant laws, regulations, and standards of the relevant countries and regions.
[0149] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0150] The above description is merely an exemplary embodiment of this application and does not limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.
Claims
1. A data reading method, characterized in that, Retrieve multiple sub-instructions contained in a batch instruction; Send a first read request to the target register for the first of the plurality of sub-instructions; Based on the first read request, read the target read data of the first sub-instruction from the target register; The target read data of all subsequent sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register. The target read data of the other sub-instructions is determined based on the target read data read by the first read request.
2. The data reading method according to claim 1, characterized in that, The step of determining that the target read data of all subsequent sub-instructions following the first sub-instruction in the plurality of sub-instructions, along with the target read data of the first sub-instruction, are stored in the target register includes: Based on preset parameters, it is determined that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
3. The data reading method according to claim 2, characterized in that, The preset parameters include at least one of the following: the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions in the plurality of sub-instructions, and the storage format of the target read data.
4. The data reading method according to claim 3, characterized in that, The step of determining, based on preset parameters, that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register includes: Based on the register offset of the target read data of the first sub-instruction, the sorting identifier of the other sub-instructions in the plurality of sub-instructions, and the storage format of the target read data, the register offset of the target read data of the other sub-instructions is determined; In response to the fact that the register offsets of the target read data corresponding to the first sub-instruction and the other sub-instructions are all consistent, it is determined that the target read data of the other sub-instructions and the target read data of the first sub-instruction are both stored in the target register.
5. The data reading method according to any one of claims 1 to 4, characterized in that, After reading the target read data of the first sub-instruction from the target register based on the first read request, the method further includes: The target read data of the first sub-instruction read based on the first read request is stored in a preset cache unit; The preset cache identifier in the cache unit is set as the first identifier; the first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
6. The data reading method according to claim 5, characterized in that, The step of determining the target read data for the other sub-instructions based on the target read data read in the first read request includes: Detect the cache identifier in the preset cache unit; In response to the cache identifier being set to the first identifier, the target read data of the first read request is read from the cache unit as the target read data of the other sub-instructions; The first identifier is used to indicate that the cache unit stores target read data that supports the reuse of the other sub-instructions.
7. The data reading method according to any one of claims 1 to 6, characterized in that, The other sub-instructions include a second sub-instruction, and the method further includes: If it is determined that the target read data of the second sub-instruction and the target read data of the first sub-instruction are not stored in the same target register, the cache identifier in the cache unit corresponding to the target read data of the first sub-instruction is set to the second identifier. The second identifier is used to indicate that the cache unit does not store target read data that supports the reuse of the second sub-instruction. In response to the second sub-instruction, a second read request is sent to the register containing the target data to be read from the second sub-instruction.
8. A data reading device, characterized in that, The device includes: The acquisition module is used to acquire multiple sub-instructions contained in a batch instruction; The sending module is used to send a first read request to the target register in response to the first sub-instruction among the plurality of sub-instructions; The read module is configured to read the target read data of the first sub-instruction from the target register based on the first read request; The determining module is used to determine that the target read data of all other sub-instructions following the first sub-instruction and the target read data of the first sub-instruction are both stored in the target register, and to determine the target read data of the other sub-instructions based on the target read data read by the first read request.
9. A chip product, characterized in that, The chip product is used to perform the data reading method as described in any one of claims 1 to 7.
10. An electronic device, characterized in that, The electronic device includes: one or more processors; A memory having stored one or more programs thereon, which, when executed by one or more processors, cause the one or more processors to implement the data reading method according to any one of claims 1-7; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.
11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the data reading method according to any one of claims 1-7.