Data race detection method and device and related product

Abstract

The invention provides a data race detection method and device and a related product, and relates to the technical field of computers. The data race detection method comprises the steps that a first instruction and a second instruction are determined, memory spaces accessed by the first instruction and the second instruction are overlapped, at least one of the first instruction and the second instruction is an instruction of write operation, and no synchronous operation exists between the first instruction and the second instruction; obtaining a first instruction clock vector of the first instruction and a second instruction clock vector of the second instruction; and according to the first instruction clock vector and the second instruction clock vector, whether data competition exists between the first instruction and the second instruction is determined, and the problems of low running speed and low efficiency of the processor are not caused while data competition detection is realized.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data contention detection method, apparatus, and related products. Background Technology

[0002] Data races refer to data synchronization problems that can occur when at least two threads access the same data object simultaneously, and at least one thread is modifying that object. The consequences of data races can include data inconsistency, program errors, and even program crashes.

[0003] In related technologies, shadow memory is used to record the memory access information of each thread to detect data contention. However, this data contention detection method has a large overhead for concurrent memory access, which leads to slow processor speed and low efficiency. Summary of the Invention

[0004] This application provides a data contention detection method, apparatus, and related products to solve the technical problem that existing data contention detection methods suffer from slow processor speed and low efficiency due to the high overhead of concurrent memory access.

[0005] In a first aspect, this application provides a data contention detection method applied to a first processor, the method comprising:

[0006] The first instruction and the second instruction are identified. The memory spaces accessed by the first instruction and the second instruction overlap. At least one of the first instruction and the second instruction is a write operation instruction. There is no synchronization operation between the first instruction and the second instruction.

[0007] Obtain the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction;

[0008] Based on the first instruction clock vector and the second instruction clock vector, determine whether there is a data race between the first instruction and the second instruction.

[0009] In a second aspect, this application provides a computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the method as described in the first aspect.

[0010] Thirdly, this application provides a data contention detection device, which includes a memory and a processor. The memory is used to store at least one computer instruction, and when the at least one computer instruction is executed by the processor, it implements the method as described in the first aspect.

[0011] The data contention detection method, apparatus, and related products provided in this application determine that a first instruction and a second instruction access memory spaces that overlap, at least one of the first and second instructions is a write operation instruction, and there is no synchronization operation between the first and second instructions; obtain the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction; and determine whether there is a data contention between the first and second instructions based on the first instruction clock vector and the second instruction clock vector. While realizing the detection of data contention, it does not cause the processor to run slowly or have low efficiency. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0013] Figure 1 This is a schematic diagram illustrating an application scenario of the data contention detection method provided in the embodiments of this application;

[0014] Figure 2 A flowchart of a data contention detection method provided in one embodiment of this application;

[0015] Figure 3 A flowchart of a data contention detection method provided in another embodiment of this application;

[0016] Figure 4 This is a structural block diagram of a data contention detection device provided in an embodiment of this application;

[0017] Figure 5 This is a structural diagram of a board according to an embodiment of this application;

[0018] Figure 6 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of this application;

[0019] Figure 7 This is a schematic diagram showing the internal structure of a single-core chip according to an embodiment of this application;

[0020] Figure 8 This is a schematic diagram showing the internal structure of a multi-core chip according to an embodiment of this application;

[0021] Figure 9 This is a schematic diagram illustrating the internal structure of another single-core chip according to an embodiment of this application;

[0022] Figure 10 This is a schematic diagram illustrating the determination of a clock vector provided in one embodiment of this application.

[0023] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0025] To clearly understand the technical solution of this application, the solutions of the prior art will be described in detail first.

[0026] In existing technologies, for the program behavior of data contention access, CPUs (Central Processing Units) use the Valgrind tool's Helgrind or ThreadSanitizer tool to detect data contention, while GPUs (Graphics Processing Units) use the NVIDIA Compute Sanitizer tool to detect data contention.

[0027] Specifically, Valgrind is a software development tool for memory debugging, memory leak detection, and performance analysis. Helgrind, a part of Valgrind, is primarily used to detect concurrency errors in multithreaded programs, such as data races and deadlocks. Helgrind works by simulating program execution to track interactions between threads and detect potential concurrency issues. Helgrind monitors shared memory access between threads and detects data races. A data race occurs when multiple threads simultaneously access shared data, with at least one thread performing a write operation, without proper synchronization. Helgrind can identify this situation and generate a report indicating which threads participated in the data race and where it occurred. However, this data race detection method is only suitable for multithreaded programs on current CPUs and requires the processor being monitored to have high processing power.

[0028] ThreadSanitizer (TSan) is a tool used to detect data races and concurrency errors in multithreaded programs. It is part of Clang (a lightweight compiler) and GCC (a programming language compiler). TSan works by dynamically analyzing program execution to detect potential concurrency problems. ThreadSanitizer uses dynamic detection technology; it doesn't scan and analyze the source code, but rather takes a series of discrete event points generated during program execution as input and analyzes them to find races. The most important events are memory access and synchronization. Memory access includes Read and Write operations, while synchronization events are typically lock events or Happens-before events. Lock events are further divided into WrLock (write lock), RdLock (read lock), WrUnLock (write unlock), and RdUnLock (read unlock). Happens-before events are divided into Signal and Wait events. These events are generated by the running program and handed over to ThreadSanitizer with the help of the underlying binary translation framework (Valgrind).

[0029] NVIDIA Compute Sanitizer is a suite of tools that performs various types of checks on the functional correctness of code. Among them, the racecheck tool is used to detect race conditions in CUDA programs. Race conditions are a common problem in parallel programming, especially when writing GPU-accelerated programs using CUDA; Compute Sanitizer is used to detect race conditions.

[0030] The aforementioned data contention detection methods for CPUs primarily address data access contention issues in multithreaded environments. Thread scheduling is complex, and data contention detection algorithms consume significant CPU processing resources, thus impacting CPU efficiency. Furthermore, GPUs utilize shadow memory for data contention detection, which, within the SIMD (Single Instruction, Multiple Data) architecture, also consumes substantial resources, potentially leading to slower GPU performance and lower efficiency.

[0031] To address the aforementioned problem, one approach is to use shadow memory to record memory access information for each thread, thereby enabling data contention detection. Specifically, for processor instruction Ii, where i ranges from 1 to N, and N is the total number of instructions, and Ii accesses Ci bytes of memory, the algorithm's complexity, without considering complex synchronization, is approximately... Typically, Ci > 1, and is much greater than 1. If the processor does not have a corresponding amount of data... Using threads of the same size to process large amounts of data, detecting data contention on the processor, and using shadow memory to record memory access information for each thread are very costly. Furthermore, using shadow memory to record memory access information for each thread requires the processor to support locking mechanisms to limit concurrent access to shadow memory.

[0032] To address the aforementioned issues, this application provides a data contention detection method. This method determines that a first instruction and a second instruction access overlapping memory spaces, at least one of the first and second instructions is a write operation, and there is no synchronization between the first and second instructions. The method then obtains the first instruction clock vector and the second instruction clock vector. Based on these clock vectors, it determines whether a data contention exists between the first and second instructions. This method allows for direct computation of instruction information, where the overhead of directly computation is significantly less than the overhead of using shadow memory to record memory access information for each thread. Therefore, this application reduces the overhead of data contention detection and does not require the processor to support locking mechanisms, thereby improving the processor's operating speed and efficiency.

[0033] The following describes the application scenarios of the data contention detection method provided in the embodiments of this application.

[0034] Reference Figure 1 This diagram illustrates an application scenario of the data race detection method provided in this application, including a first processor 11 and a second processor 12. The first processor 11 runs a detection tool for data race detection (racecheck). This tool is used to instrument code in the program under test, establish communication between the first processor 11 and the second processor 12, and initiate an analysis process on the first processor 11. The second processor 12 runs the program under test. During execution, the second processor 12 records instruction information and sends this information to the first processor 11. The first processor 11 then uses its initiated analysis process to perform data race detection on the program under test based on the instruction information.

[0035] In the embodiments of this application, for example, the first processor is a CPU and the second processor is an XPU, wherein the XPU may be an artificial intelligence processor or a GPU, etc.

[0036] The data race detection method provided in this application can be applied to scenarios where data race detection is performed on running programs. Specifically, it is executed on a first processor, which can be a CPU or other types of processors, without limitation.

[0037] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0038] Figure 2 A flowchart of a data contention detection method provided in one embodiment of this application is shown below. Figure 2 As shown, the data contention detection method provided in this embodiment includes the following steps:

[0039] Step 201: Determine the first instruction and the second instruction.

[0040] The memory spaces accessed by the first instruction and the second instruction overlap. This overlap can refer to the same memory space, for example, the first instruction and the second instruction accessing the same memory space [0,32]. Alternatively, the memory spaces can partially overlap, for example, the first instruction accessing memory space [0,64] and the second instruction accessing memory space [0,32].

[0041] In this embodiment, at least one of the first and second instructions is a write operation instruction, and there is no synchronization operation between the first and second instructions. For a data race to occur between the first and second instructions, the following conditions must be met: the accessed memory spaces overlap, at least one instruction is a write operation instruction, and there is no synchronization operation between the first and second instructions.

[0042] It's understandable that if two instructions access memory spaces that don't overlap, there can be no data race between them. Similarly, if both instructions are read operations, there can be no data race between them. Furthermore, if there are synchronization operations between two instructions, there can be no data race between them.

[0043] In this application, both the first instruction and the second instruction are write operation instructions; or the first instruction is a write operation instruction and the second instruction is a read operation instruction; or the first instruction is a read operation instruction and the second instruction is a write operation instruction.

[0044] In one embodiment, reference is made to Figure 1 When the second processor runs the program under test, the program under test will execute multiple instructions. During the execution, instruction information will be generated for multiple instructions. The second processor will send the instruction information of the instruction to the first processor. The first processor will determine the first instruction and the second instruction based on the instruction information.

[0045] Step 202: Obtain the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction.

[0046] In this application, the first instruction clock vector is used to represent the occurrence time of the first instruction, that is, the time when the first instruction is executed. The second instruction clock vector is used to represent the occurrence time of the second instruction, that is, the time when the second instruction is executed.

[0047] In one embodiment, the first processor can acquire instruction information, determine the instruction clock vector for each instruction based on the instruction information, and then store the instruction clock vector. If the first processor determines a first instruction and a second instruction, it can acquire the stored first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction.

[0048] In the embodiments of this application, the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction can also be obtained by other means, which are not limited here.

[0049] Step 203: Determine whether there is a data race between the first instruction and the second instruction based on the first instruction clock vector and the second instruction clock vector.

[0050] It is understandable that if the first instruction clock vector and the second instruction clock vector indicate that the first instruction and the second instruction access the same memory at the same time, then it can be determined that there is a data race between the first instruction and the second instruction.

[0051] If the first instruction clock vector and the second instruction clock vector indicate that the times when the first instruction and the second instruction access the same memory do not overlap, then it can be determined that there is no data race between the first instruction and the second instruction.

[0052] In this embodiment, by first determining the first instruction and the second instruction, and then obtaining the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction; and then determining whether there is a data race between the first instruction and the second instruction based on the first instruction clock vector and the second instruction clock vector, this application does not need to use shadowmemory to record the memory access information of each thread. This application can directly calculate the instruction information of the instruction to determine whether there is a data race between the instructions, reducing the overhead of data race detection, and does not require the processor to support the locking mechanism, thereby improving the processor's running speed and efficiency.

[0053] Figure 3 A flowchart of a data contention detection method provided in another embodiment of this application is applied to... Figure 1 The first processor 11 shown is as follows: Figure 3 As shown, the method may include the following steps:

[0054] Step 301: Receive instruction information from the second processor.

[0055] The instruction information is generated by the second processor when it runs the program under test. This instruction information includes memory access information and other instruction information. The memory access information includes the memory address and size, which are determined based on the opcode and operands; the specific determination method is not limited here. Other instruction information includes the processor core identifier (indicating the instruction originated from the processor core), the process identifier (indicating the instruction originated from the process), the memory access type of the instruction, and indications of whether there are synchronization operations between instructions. The memory access type can include write operation instruction types and read operation instruction types. The second processor sends all instruction information to the first processor.

[0056] Understandable, adopting Figure 1 The testing tool shown performs instrumentation on the program under test to obtain the instrumented program under test, which includes the instrumentation code inserted during the instrumentation operation. When the second processor 12 runs the instrumented program under test, it also runs the instrumentation code in the program under test, which is used to collect instruction information.

[0057] Reference Figure 1The program under test is run on a second processor. The instruction information for each instruction generated by the instrumentation code is as follows: For example, if the second processor is a multi-core processor, each processor core has a core ID. The instruction information for instruction a1 includes: processor core 1, process 1, instruction a1, access address of instruction a1, access size of instruction a1, write operation instruction, and indication that there is no synchronization operation. The instruction information for instruction a2 includes: processor core 1, process 1, instruction a2, access address of instruction a2, access size of instruction a2, write operation instruction, and indication that there is no synchronization operation with instruction b1.

[0058] Furthermore, the second processor sends instruction information to the first processor through its communication port. Specifically, the second processor sends the instruction information in the order of instruction execution, and the first processor receives the instruction information in the same order. After receiving the instruction information, the first processor determines the instruction clock vector based on the instruction information and the order in which the instructions were received. For example, the first processor receives the instruction information for instruction a1 first, and then receives the instruction information for instruction a2.

[0059] Step 302: Determine the first instruction and the second instruction based on the instruction information.

[0060] In this embodiment of the application, when the first processor receives instruction information, it can determine the memory space to be accessed by the instruction based on the instruction's opcode and operands in the instruction information, determine whether the instruction is a write operation or a read operation based on the instruction's memory access type, and determine whether the instruction has synchronous operations with other instructions based on the indication information.

[0061] Furthermore, the first and second instructions can be determined from multiple instructions based on whether they access the same memory space, whether there is at least one instruction that performs a write operation, and whether it is a synchronous operation.

[0062] Step 303: Obtain multiple instruction streams.

[0063] Each instruction stream contains multiple instructions, and the multiple instructions in the same instruction stream are processed by the same process.

[0064] It is understood that this application analyzes multiple instruction information to determine multiple instruction streams. Each instruction stream includes multiple instructions, and each instruction stream corresponds to a process, that is, is processed by the same hardware module of the second processor.

[0065] The program under test can contain multiple instructions, which can be divided into different instruction streams according to their functions. These different instruction streams can be executed in parallel, thus fully utilizing the computing power of the second processor. The second processor can be a multi-core processor, and each processor core can have five instruction streams: I / O instruction stream, MOVE instruction stream, SIMD instruction stream, SIMT instruction stream, and scalar instruction stream. The instructions in the I / O instruction stream are used to move data between the internal and external memory spaces of the second processor; the instructions in the MOVE instruction stream are used to move data between the internal memory spaces of the second processor; the instructions in the SIMD, SIMT, and scalar instruction streams are all arithmetic instructions. The instructions in the SIMD instruction stream are used to perform single-instruction multiple-data operations; the instructions in the SIMT instruction stream are used to perform single-instruction multiple-thread operations; and the instructions in the scalar instruction stream are used to perform scalar arithmetic operations.

[0066] It can be understood that the second processor includes M processor cores, M≥1, and each processor core corresponds to P instruction streams, P≥1; N is the product of M and P, where N is the total number of instruction streams.

[0067] For example, the second processor includes: 5 processor cores, each processor core including 5 instruction streams. The instructions in the first instruction stream are all I / O (Input / Output) instructions, the instructions in the second instruction stream are all MV (Move) instructions, the instructions in the third instruction stream are all SIMD (Single Instruction, Multiple Data) instructions, the instructions in the fourth instruction stream are all SIMT (Single Instruction, Multiple Threads) instructions, and the instructions in the fifth instruction stream are all SCALAR (Scalar Instruction) instructions. Therefore, there are a total of 25 instruction streams, and each instruction stream has a different processing stage, thus the 25 instruction streams correspond to 25 processes.

[0068] Step 304: For each process, determine the instruction clock vector for each instruction.

[0069] In this embodiment, the instruction clock vector is determined on a process-by-process basis. Within the instruction stream processed by the same process, instructions are executed sequentially without data races.

[0070] Specifically, for each process, the instruction clock vector for each instruction is determined, including: for each of the N processes, when the process processes an instruction, the i-th element of Vci is incremented by 1 to determine the process clock vector; the initial vector of each process's process clock vector is: Vci = [0,…,0], where Vci represents the process clock vector of the i-th process, where i ranges from 1 to N, and N is an integer greater than 1, and the length of the process clock vector is N; the current Vci is determined as the instruction clock vector of the instruction currently being processed by the process. It can be understood that the total number of instruction streams N and the length N of the process clock vector are the same.

[0071] Furthermore, if the instruction processed by the first process and the instruction processed by the second process are synchronous instructions, the process clock vectors of the first process and the second process are updated according to the process clock vectors of the first process and the second process; wherein the updated process clock vectors of the first process and the second process are the same, the first process is any one of the N processes, and the second process is any one of the N processes.

[0072] The process clock vectors of the first process and the second process are updated based on their respective process clock vectors. This includes: obtaining the j-th element of the first process's process clock vector as x; obtaining the j-th element of the second process's process clock vector as y; and updating the j-th element of both the first and second process clock vectors to be the larger of x and y. Here, j ranges from 1 to N.

[0073] Furthermore, if the instruction processed by the first process is a synchronization instruction, then the first process can receive synchronization information sent by other processes. This synchronization information may carry the clock information of the other processes. After receiving the synchronization information sent by other processes, the first process can first update its own clock vector according to the clock vector carried in the synchronization information, and then increment the i-th element of the Vci corresponding to the first process by 1. Similarly, if the instruction processed by the second process is a synchronization instruction, then the second process can receive synchronization information sent by other processes. This synchronization information may carry the clock information of the other processes. After receiving the synchronization information sent by other processes, the second process first updates its own clock vector according to the clock vector carried in the synchronization information, and then increments the i-th element of the Vci corresponding to the second process by 1. Figure 10 As shown, process A sends synchronization information carrying clock vector [2,0] to process B. After receiving the message at instruction c, process B updates its clock vector to [2,2].

[0074] In one example, the second processor has one processor core, which includes two instruction streams. The total number of instruction streams is two, corresponding to two processes: process 1 and process 2. Process 1 corresponds to process clock vector Vc1, and process 2 corresponds to process clock vector Vc2. Here, N = 2, and i takes values ​​of 1 and 2. The initial vectors of the process clock vectors for both processes are Vci = [0,0]. Referring to Table 1, the instruction stream processed by process 1 includes instructions a1 to a6, and the instruction stream processed by process 2 includes instructions b1 to b6. Instructions a2 and b1 are synchronized using a synchronization instruction, and instructions a3 and b5 are synchronized using a synchronization instruction.

[0075] Table 1

[0076]

[0077]

[0078] In this embodiment, for each instruction executed by process 1, the first element of Vc1 is incremented by 1, and for each instruction executed by process 2, the second element of Vc2 is incremented by 1. If the instruction executed by process 1 and the instruction executed by process 2 are synchronous instructions, processes 1 and 2 can send messages to each other to update Vc1 and Vc2. Specifically, when process 1 sends a message to process 2, the message carries process 1's Vc1. After receiving the message, process 2 takes the maximum value between Vc1 and Vc2 for each element in Vc2 to update Vc2; further, the second element of Vc2 is incremented by 1. Similarly, when process 2 sends a message to process 1, the message carries process 2's Vc2. After receiving the message, process 1 takes the maximum value between Vc1 and Vc2 for each element in Vc1 to update Vc1; further, the first element of Vc1 is incremented by 1.

[0079] Referring to Table 1, the initial vector of the process clock vector of process 1 is Vc1 = [0,0], and the initial vector of the process clock vector of process 2 is Vc2 = [0,0]. After process 1 processes instruction a1, the first element of the corresponding process clock vector Vc1 is incremented by 1, and the corresponding process clock vector Vc1 becomes Vc1 = [1,0]. The current process clock vector Vc1 = [1,0] is determined to be the instruction clock vector Va1 = [1,0] of instruction a1.

[0080] For example, referring to Table 1, after process 1 processes instruction a2, the first element of its corresponding process clock vector Vc1 is incremented by 1, resulting in Vc1 = [2, 0]. After process 2 processes instruction b1, the second element of its corresponding process clock vector Vc2 is incremented by 1, resulting in Vc1 = [0, 1]. Since there is a synchronization operation between instructions a2 and b1, processes 1 and 2 need to perform a synchronization instruction sync1. After synchronization, the process clock vector Vc1 corresponding to instruction a2 and the process clock vector Vc2 corresponding to instruction b1 are the same.

[0081] Specifically, the maximum value of each element in process clock vectors Vc1 and Vc2 is used to synchronize them. For the first element of Vc1 and Vc2 (j=1), the element x=2 in Vc1 and the element y=0 in Vc2. The maximum value of x and y for the first element of Vc1 and Vc2 after the synchronization instruction determines that the value of the first element of Vc1 and Vc2 after the synchronization instruction is 2. Similarly, for the second element of Vc1 and Vc2 (j=2), the element x=0 in Vc1 and the element y=1 in Vc2. The maximum value of x and y for the second element of Vc1 and Vc2 after the synchronization instruction determines that the value of the second element of Vc1 and Vc2 after the synchronization instruction is 1. Therefore, after the synchronization instruction, Vc1 = [2,1] and Vc2 = [2,1]. Furthermore, the first element of Vc1 is incremented by 1 to obtain the updated Vc1 = [3,1]; the second element of Vc2 is incremented by 1 to obtain the updated Vc2 = [2,2].

[0082] Furthermore, in Table 1, after process 2 processes instruction b2, the second element of the corresponding process clock vector Vc2 is incremented by 1, and the process clock vector Vc2 at this time is Vc2 = [2,3]. Therefore, the current process clock vector Vc2 = [2,3] is determined to be the instruction clock vector Vb2 = [2,3] for instruction b2. After process 2 processes instruction b3, the second element of the current process clock vector Vc2 is incremented by 1, and the corresponding process clock vector Vc2 is Vc2 = [2,4]. Therefore, the current process clock vector Vc2 = [2,4] is determined to be the instruction clock vector Vb3 = [2,4] for instruction b3. After process 2 processes instruction b4, the second element of the corresponding process clock vector Vc2 is incremented by 1, and the process clock vector Vc2 is now Vc2 = [2,5]. It is determined that the current process clock vector Vc2 = [2,5] is the instruction clock vector Vb4 = [2,5] of instruction b4. After process 2 processes instruction b5, the second element of the corresponding process clock vector Vc2 is incremented by 1, and the process clock vector Vc2 is now Vc2 = [2,6].

[0083] In this process, process 1 processes instruction a3. The first element of the process clock vector Vc1 is incremented by 1, resulting in Vc1 = [4,1]. Since there is a synchronization instruction sync2 between instructions a3 and b5, Vc1 and Vc2 are synchronized according to Vc1 = [4,1] and Vc2 = [2,6]. After synchronization, Vc1 = Vc2 = [4,6]. Further, the first element of Vc1 is incremented by 1, resulting in the updated Vc1 = [5,6]; the second element of Vc2 is incremented by 1, resulting in the updated Vc2 = [4,7].

[0084] Further, process 1 processes instruction a4, and the first element of the process clock vector Vc1 is incremented by 1, resulting in Vc1 = [6,6]. This process clock vector Vc1 = [6,6] is determined to be the instruction clock vector Va4 = [6,6] for instruction a4. Process 1 processes instruction a5, and the first element of the process clock vector Vc1 is incremented by 1, resulting in Vc1 = [7,6]. This process clock vector Vc1 = [7,6] is determined to be the instruction clock vector Va5 = [7,6] for instruction a5. Process 1 processes instruction a6, and the first element of the process clock vector Vc1 is incremented by 1, resulting in Vc1 = [8,6]. This process clock vector Vc1 = [8,6] is determined to be the instruction clock vector Va5 = [8,6] for instruction a5. After process 2 processes instruction b6, the second element of the corresponding process clock vector Vc2 is incremented by 1. At this time, the process clock vector Vc2 is Vc2 = [4,8]. It is determined that the current process clock vector Vc2 = [4,8] is the instruction clock vector Vb6 = [4,8] of instruction b6.

[0085] Step 305: Determine the first instruction clock vector and the second instruction clock vector from among the multiple instruction clock vectors.

[0086] In this embodiment, a first instruction and a second instruction are first determined from multiple instructions. Referring to Table 1, for example, if the first instruction is instruction a1 and the second instruction is instruction b3, then the first instruction clock vector is Va1 = [1,0] and the second instruction clock vector is Vb3 = [2,4]. Another example is that if the first instruction is instruction a2 and the second instruction is instruction b1, then the first instruction clock vector is Va2 = [2,0] and the second instruction clock vector is Vb1 = [0,1]. Yet another example is that if the first instruction is instruction a6 and the second instruction is instruction b6, then the first instruction clock vector is Va6 = [8,6] and the second instruction clock vector is Vb6 = [4,8].

[0087] Step 306: If the value of the m-th element of the first instruction clock vector is greater than the value of the m-th element of the second instruction clock vector, and the value of the n-th element of the first instruction clock vector is less than the value of the n-th element of the second instruction clock vector, it is determined that there is a data race between the first instruction and the second instruction.

[0088] If the j-th element of the first instruction clock vector is less than the j-th element of the second instruction clock vector, then it can be determined that the first instruction clock vector is less than the second instruction clock vector. This leads to the conclusion that the time periods when the first instruction and the second instruction access the same memory space do not overlap, and that the first instruction is executed before the second instruction. Furthermore, it can be determined that there is no data race between the first instruction and the second instruction. For example, if the first instruction clock vector is Va1 = [1,0] and the second instruction clock vector is Vb3 = [2,4], and Va1 < Vb3, then there is no data race between the first instruction a1 and the second instruction b3.

[0089] Similarly, if the j-th element of the first instruction clock vector is equal to the j-th element of the second instruction clock vector, then it can be determined that the first instruction clock vector is equal to the second instruction clock vector, and further, it can be determined that there is no data race between the first instruction and the second instruction.

[0090] Furthermore, if the value of the m-th element of the first instruction clock vector is greater than the value of the m-th element of the second instruction clock vector, and the value of the n-th element of the first instruction clock vector is less than the value of the n-th element of the second instruction clock vector, it is determined that there is a data race between the first instruction and the second instruction. For example, if the first instruction is instruction a6 and the second instruction is instruction b6, then the first instruction clock vector is Va6 = [8,6] and the second instruction clock vector is Vb6 = [4,8], where m = 1 and n = 2; then the value 8 of the first element of Va6 = [8,6] is greater than the value 4 of the first element of Vb6 = [4,8], and the value 6 of the second element of Va6 = [8,6] is less than the value 8 of the second element of Vb6 = [4,8]. This can be represented as Va6||Vb6, indicating that the first instruction a6 and the second instruction b6 are operating concurrently. Since the memory spaces accessed by the first instruction Va6 and the second instruction Vb6 overlap, it can be determined that there is a data race between the first instruction and the second instruction.

[0091] In summary, the data race detection method provided in this application, on the one hand, uses a second processor to run the program under test while the first processor detects whether data races exist during the execution of the program under test. This reduces the computational resources occupied by the second processor during data detection, thereby avoiding impacting the computational efficiency of the second processor. On the other hand, this application determines the instruction clock vector for each instruction and determines whether data races exist based on the determined instruction clock vector, achieving high efficiency and high accuracy in data race detection.

[0092] Reference Figure 4 This application also provides a data contention detection device 40, including a memory 41 and a processor 42. The memory 41 is used to store at least one computer instruction. When the at least one computer instruction is executed by the processor 42, it implements the method of any of the above embodiments. For details, please refer to the description of the method steps above, which will not be repeated here.

[0093] In one possible implementation, Figure 1 The second processor in the process can be a chip, the structure of which can be found in [reference needed]. Figures 7-9 As shown. This second processor can also be a board. Figure 5 This is a structural diagram of a board according to an embodiment of this application, such as... Figure 5As shown, board 500 includes chip 501, which is a system-on-chip (SoC) for artificial intelligence. It integrates one or more combined processing units, which are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large amount of input data, placing high demands on the platform's storage and computing capabilities. Board 500 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and substantial computing power.

[0094] Chip 501 is connected to external device 503 via external interface device 502. External device 503 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Optionally, in this embodiment, it may be various vision sensors. Data to be processed can be transmitted from external device 503 to chip 501 via external interface device 502. The calculation results of chip 501 can be transmitted back to external device 503 via external interface device 502. Depending on the application scenario, external interface device 502 may have different interface forms, such as a PCIe interface.

[0095] The board 500 also includes a storage device 504 for storing data, which includes one or more memory cells 505. The storage device 504 is connected to and transmits data with the controller 506 and the artificial intelligence chip 501 via a bus. The controller 506 in the board 500 is configured to regulate the state of the artificial intelligence chip 501. Therefore, in one application scenario, the controller 506 may include a microcontroller (MCU).

[0096] In one possible implementation, a combined processing device is also provided. Figure 6 A structural diagram of the combined processing device in chip 501 of this embodiment is shown. Figure 6 As shown, the combined processing device 60 includes a computing device 601, an interface device 602, a processing device 603, and a storage device 604.

[0097] The computing device 601 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 603 through the interface device 602 to jointly complete the user-specified operations.

[0098] Interface device 602 is used to transmit data and control commands between computing device 601 and processing device 603. For example, computing device 601 can obtain input data from processing device 603 via interface device 602 and write it to on-chip storage device of computing device 601. Further, computing device 601 can obtain control commands from processing device 603 via interface device 602 and write them to on-chip control cache of computing device 601. Alternatively or optionally, interface device 602 can also read data from storage device of computing device 601 and transmit it to processing device 603.

[0099] The processing device 603, as a general-purpose processing device, performs basic controls including but not limited to data transfer and starting / stopping the computing device 601. Depending on the implementation, the processing device 603 may be one or more types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), or other general-purpose and / or special-purpose processors. These processors include, but are not limited to, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing device 601 of this application can be considered as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 601 and the processing device 603 are considered together, they are considered to form a heterogeneous multi-core structure.

[0100] Storage device 604 is used to store data to be processed. It may be DRAM 604, which is DDR memory, typically 16G or larger in size, and is used to store data of computing device 601 and / or processing device 603.

[0101] Figure 7 The image shows a schematic diagram of the internal structure of a single-core chip. Chip 700 is used to process input data for computer vision, speech, natural language processing, and data mining. Chip 700 includes three main modules: a control module 701, a processing module 702, and a storage module 703.

[0102] The control module 701 coordinates and controls the operation of the computation module 702 and the storage module 703 to complete the deep learning task. It includes an instruction fetch unit (IFU) 7011 and an instruction decode unit (IDU) 7012. The instruction fetch unit 7011 fetches instructions from the processing device, while the instruction decode unit 7012 decodes the fetched instructions and sends the decoding result as control information to the computation module 702 and the storage module 703.

[0103] The computation module 702 includes a vector operation unit 7021 and a matrix operation unit 7022. The vector operation unit 7021 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 7022 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0104] The storage module 703 is used to store or move relevant data, including a neuron RAM (NRAM) 7031, a weight RAM (WRAM) 7032, and a direct memory access (DMA) module 7033. The NRAM 7031 stores the input neurons, output neurons, and intermediate results after computation; the WRAM 7032 stores the convolution kernels, i.e., weights, of the deep learning network; and the DMA 7033 is connected to the DRAM 604 via bus 704, responsible for data transfer between the single-core chip 700 and the DRAM 604.

[0105] Figure 8 The diagram shows the internal structure of the multi-core chip. The multi-core chip 800 adopts a hierarchical structure design. As a system-on-a-chip, the multi-core chip 800 includes at least one cluster, and each cluster includes multiple processor cores. In other words, the multi-core chip 800 is composed of a system-on-a-chip-cluster-processor core hierarchy.

[0106] From the perspective of system-on-a-chip hierarchy, such as Figure 8 As shown, the multi-core chip 800 includes an external memory controller 801, a peripheral communication module 802, an on-chip interconnect module 803, a synchronization module 804, and multiple clusters 805.

[0107] There can be multiple external storage controllers 801; two are shown as an example in the figure. These controllers are used to respond to access requests from the processor core to access external storage devices, such as… Figure 8The DRAM 604 in the chip allows for reading data from external sources or writing data. The peripheral communication module 802 receives control signals from the processing device via the interface device 602 to initiate chip task execution. The on-chip interconnect module 803 connects the external memory controller 801, the peripheral communication module 802, and multiple clusters 805 to transmit data and control signals between modules. The synchronization module 804 is a global barrier controller (GBC) used to coordinate the working progress of each cluster and ensure information synchronization. The multiple clusters 805 are the computing cores of the multi-core chip 800. Four are shown exemplary in the figure; however, with hardware development, the multi-core chip 800 of this application can also include 8, 16, 64, or even more clusters 805. The clusters 805 are used to efficiently execute deep learning algorithms.

[0108] From the perspective of cluster hierarchy, such as Figure 8 As shown, each cluster 805 includes multiple processor cores (IPU cores) 806 and one memory core (MEM core) 807. For example, each cluster 805 includes four processor cores and one memory, which can be DRAM 604.

[0109] Four processor cores 806 are shown in the figure as an example, but this application does not limit the number of processor cores 806. Each processor core 806 is similar to Figure 9 The single-core chip also includes three main modules: a control module 901, an arithmetic module 902, and a storage module 903. The functions and structures of the control module 901, arithmetic module 902, and storage module 903 are largely the same as those of the control module 701, arithmetic module 702, and storage module 703. The control module 901 includes an instruction fetch unit 9011 and an instruction decode unit 9012. The arithmetic module 902 includes a vector operation unit 9021 and a matrix operation unit 9022. Further details are omitted. It should be noted that the storage module 903 includes an input / output direct memory access (IODMA) module 9033 and a move direct memory access (MVDMA) module 9034. The IODMA 9033 controls the memory access of NRAM 9031 / WRAM 9032 and DRAM 604 via the broadcast bus 809; the MVDMA 9034 is used to control the memory access of NRAM 9031 / WRAM 9032 and SRAM 808.

[0110] Back Figure 8The storage core 807 is primarily used for storage and communication, namely storing shared data or intermediate results among processor cores 806, and performing communication between cluster 805 and DRAM 604, communication between clusters 805, and communication between processor cores 806. In other embodiments, the storage core 807 has scalar operation capabilities and is used to perform scalar operations.

[0111] The storage core 807 includes an SRAM 808, a broadcast bus 809, a cluster direct memory access (CDMA) module 810, and a global direct memory access (GDMA) module 811. The SRAM 808 acts as a high-performance data relay station. Data multiplexed between different processor cores 806 within the same cluster 805 does not need to be obtained from the DRAM 604 by each processor core 806. Instead, it is relayed between processor cores 806 via the SRAM 808. The storage core 807 only needs to quickly distribute the multiplexed data from the SRAM 808 to multiple processor cores 806 to improve inter-core communication efficiency and greatly reduce on-chip and off-chip input / output access.

[0112] Broadcast bus 809, CDMA 810, and GDMA 811 are used to perform communication between processor cores 806, communication between clusters 805, and data transfer between cluster 805 and DRAM 604, respectively. These will be explained below.

[0113] The broadcast bus 809 is used to complete high-speed communication between the processor cores 806 within the cluster 805. In this embodiment, the broadcast bus 809 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point (e.g., single processor core to single processor core) data transmission. Multicast is a communication method that transmits a piece of data from SRAM 808 to several specific processor cores 806. Broadcast is a communication method that transmits a piece of data from SRAM 808 to all processor cores 806, and is a special case of multicast.

[0114] CDMA 810 is used to control SRAM 808 access between different clusters 805 within the same chip.

[0115] The GDMA 811 works in conjunction with the external memory controller 801 to control memory access from the SRAM 808 to the DRAM 604 of the cluster 805, or to read data from the DRAM 604 into the SRAM 808. As mentioned above, communication between the DRAM 604 and the NRAM 9031 or WRAM 9032 can be achieved through two channels. The first channel is a direct connection between the DRAM 604 and the NRAM 9031 or WRAM 9032 via the IODAM 9033; the second channel involves first transferring data between the DRAM 604 and SRAM 808 via the GDMA 811, and then transferring data between the SRAM 808 and the NRAM 9031 or WRAM 9032 via the MVDMA 9034. Although the second channel appears to require more components and has a longer data flow, in some embodiments, the bandwidth of the second channel is actually much greater than that of the first channel. Therefore, communication between the DRAM 604 and the NRAM 9031 or WRAM 9032 may be more efficient through the second channel. Embodiments of this application may select the data transmission channel based on their own hardware capabilities.

[0116] In other embodiments, the functions of GDMA 811 and IODMA 9033 can be integrated into the same component. For ease of description, this application treats GDMA 811 and IODMA 9033 as different components. For those skilled in the art, any component that implements functions and achieves technical effects similar to this application falls within the scope of protection of this application. Furthermore, the functions of GDMA 811, IODMA 9033, CDMA 810, and MVDMA 9034 can also be implemented by the same component.

[0117] This application also provides a computer-readable storage medium storing a computer program, which, when executed by at least one processor, implements the data race detection method provided in any of the above embodiments.

[0118] This application also provides an electronic device, which includes: an off-chip memory and the chip provided in the above embodiment.

[0119] The foregoing may be better understood in view of the following clauses:

[0120] Clause 1. A data contention detection method, applied to a first processor, the method comprising:

[0121] The first instruction and the second instruction are identified. The memory spaces accessed by the first instruction and the second instruction overlap. At least one of the first instruction and the second instruction is a write operation instruction. There is no synchronization operation between the first instruction and the second instruction.

[0122] Obtain the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction;

[0123] Based on the first instruction clock vector and the second instruction clock vector, determine whether there is a data race between the first instruction and the second instruction.

[0124] Clause 2. Obtaining the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction according to the method of Clause 1, including:

[0125] Acquire multiple instruction streams, each containing multiple instructions, and the multiple instructions within the same instruction stream are processed by the same process;

[0126] For each process, determine the instruction clock vector for each instruction;

[0127] Among multiple instruction clock vectors, determine the first instruction clock vector and the second instruction clock vector.

[0128] Clause 3. In accordance with the method of Clause 2, for each process, determine the instruction clock vector for each instruction, including;

[0129] For each of the N processes, when the process processes an instruction, the i-th element of Vci is incremented by 1 to determine the process clock vector of the process; where the initial vector of the process clock vector of each process is: Vci = [0,…,0], where Vci represents the process clock vector of the i-th process, where i takes the value from 1 to N, N is an integer greater than 1, and the length of the process clock vector is N.

[0130] Determine the current Vci as the instruction clock vector of the instruction currently being processed by the process.

[0131] Clause 4, before determining the current Vci as the instruction clock vector of the instruction currently being processed by the process according to the method of Clause 3, also includes:

[0132] If the instruction processed by the first process and the instruction processed by the second process are synchronous instructions, update the process clock vectors of the first process and the second process according to the process clock vectors of the first process and the second process.

[0133] In this process, the updated process clock vector of the first process is the same as that of the second process. The first process is any one of the N processes, and the second process is any one of the N processes.

[0134] Clause 5. According to the method in Clause 4, update the process clock vectors of the first process and the second process based on the process clock vectors of the first process and the second process, including:

[0135] Get the j-th element of the process clock vector of the first process as x;

[0136] Get the j-th element y from the process clock vector of the second process;

[0137] Update the process clock vector of the first process to the larger of x and y for the j-th element of the process clock vector of the second process;

[0138] Where j ranges from 1 to N.

[0139] Clause 6. Using any one of Clauses 1 to 5, determine whether a data race exists between the first instruction and the second instruction based on the first instruction clock vector and the second instruction clock vector, including:

[0140] If the value of the m-th element of the first instruction clock vector is greater than the value of the m-th element of the second instruction clock vector, and the value of the n-th element of the first instruction clock vector is less than the value of the n-th element of the second instruction clock vector, it is determined that there is a data race between the first instruction and the second instruction.

[0141] Where m and n are both positive integers, and m and n are different.

[0142] Article 7. The first and second directives shall be determined in accordance with any one of Articles 3 to 5, including:

[0143] The instruction information received from the second processor is generated by the instrumentation code in the program under test when the second processor runs the program under test.

[0144] Based on the instruction information, determine the first instruction and the second instruction.

[0145] Clause 8. According to the method of Clause 7, the second processor includes a number of processor cores of M, M≥1, and the number of instruction streams corresponding to each processor core is P, P≥1; N is the product of M and P.

[0146] Clause 9. A computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the method of any one of Clauses 1-8.

[0147] Clause 10. A data contention detection apparatus, comprising: the data contention detection apparatus including a memory and a processor, the memory being used to store at least one computer instruction, wherein when the at least one computer instruction is executed by the processor, it implements the method of any one of Clauses 1-8.

[0148] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0149] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0150] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0151] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0152] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, an AI processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, storage units can be any suitable magnetic or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0153] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0154] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

Claims

1. A data contention detection method, characterized in that, Applied to a first processor, the method includes: The first instruction and the second instruction are identified. The memory spaces accessed by the first instruction and the second instruction overlap. At least one of the first instruction and the second instruction is a write operation instruction. There is no synchronization operation between the first instruction and the second instruction. Obtain the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction; Based on the first instruction clock vector and the second instruction clock vector, determine whether there is a data race between the first instruction and the second instruction.

2. The method according to claim 1, characterized in that, The step of obtaining the first instruction clock vector of the first instruction and the second instruction clock vector of the second instruction includes: Multiple instruction streams are acquired, each instruction stream comprising multiple instructions, and the multiple instructions within the same instruction stream are processed by the same process; For each process, determine the instruction clock vector for each instruction; Among multiple instruction clock vectors, the first instruction clock vector and the second instruction clock vector are determined.

3. The method according to claim 2, characterized in that, The determination of the instruction clock vector for each instruction for each process includes: For each of the N processes, when the process processes an instruction, the i-th element of Vci is incremented by 1 to determine the process clock vector of the process; wherein, the initial vector of the process clock vector of each process is: Vci = [0,…,0], where Vci represents the process clock vector of the i-th process, where i takes values ​​from 1 to N, N is an integer greater than 1, and the length of the process clock vector is N; The current Vci is determined to be the instruction clock vector of the instruction currently being processed by the process.

4. The method according to claim 3, characterized in that, Before determining the current Vci as the instruction clock vector of the instruction currently being processed by the process, the method further includes: If the instruction processed by the first process and the instruction processed by the second process are synchronous instructions, update the process clock vectors of the first process and the second process according to the process clock vectors of the first process and the second process. The updated process clock vector of the first process is the same as that of the second process. The first process is any one of the N processes, and the second process is any one of the N processes.

5. The method according to claim 4, characterized in that, The step of updating the process clock vectors of the first process and the second process based on the process clock vectors of the first process and the second process includes: Obtain x as the j-th element in the process clock vector of the first process; Get the j-th element y from the process clock vector of the second process; Update the process clock vector of the first process and the process clock vector of the second process so that the j-th element is the larger of x and y; Wherein, j ranges from 1 to N.

6. The method according to any one of claims 1 to 5, characterized in that, The step of determining whether there is a data race between the first instruction and the second instruction based on the first instruction clock vector and the second instruction clock vector includes: If the value of the m-th element of the first instruction clock vector is greater than the value of the m-th element of the second instruction clock vector, and the value of the n-th element of the first instruction clock vector is less than the value of the n-th element of the second instruction clock vector, it is determined that there is a data race between the first instruction and the second instruction. Wherein, m and n are both positive integers, and m and n are different.

7. The method according to any one of claims 3 to 5, characterized in that, The determination of the first instruction and the second instruction includes: The instruction information received is the instruction sent by the second processor, wherein the instruction information is generated by the instrumentation code in the program under test when the second processor runs the program under test; Based on the instruction information, the first instruction and the second instruction are determined.

8. The method according to claim 7, characterized in that, The second processor includes M processor cores, M≥1, and each processor core corresponds to P instruction streams, P≥1; N is the product of M and P.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by at least one processor, implements the method as described in any one of claims 1-8.

10. A data contention detection device, characterized in that, The data contention detection device includes a memory and a processor. The memory is used to store at least one computer instruction, which, when executed by the processor, implements the method as described in any one of claims 1-8.

Images