Heterogeneous acceleration board card for electric power simulation and method thereof

Abstract

The invention discloses a heterogeneous acceleration board card for electric power simulation and a method thereof, belongs to the technical field of electric power simulation, and aims to solve the problems of low processing efficiency, low transmission rate and poor stability of the existing board card, the heterogeneous acceleration board card adopts an FPGA + DSP heterogeneous architecture, and is matched with a DDR4 / DDR3 special storage module, a PCIe 3.0 * 16 / 2.0 * 2 dual high-speed interface and an SFP28 optical fiber module; and an optimized power supply clock scheme and FLASH and USB-to-JTAG auxiliary configuration are supplemented. The FPGA module is responsible for parallel data processing, the DSP module is responsible for floating point operation, the dual-storage module guarantees data stability, and the high-speed interface meets the multi-scene transmission requirement. The electric power simulation processing delay is reduced to 3.2 ms, the transmission bandwidth reaches 800 Gbps, the data error rate is lower than 10 <-12 >, the starting success rate is 99.9%, the simulation real-time performance and reliability are remarkably improved, and the method is suitable for a complex electric power simulation scene of an intelligent power grid.

Description

Technical Field

[0001] This invention belongs to the field of power simulation technology, specifically relating to a heterogeneous acceleration board and method for power simulation. Background Technology

[0002] In power system simulation, especially in the fields of real-time simulation of smart grids and hardware-in-the-loop testing, the system needs to process massive amounts of multi-source electrical measurement data (such as voltage, current, and power) and perform complex mathematical model calculations (such as electromagnetic transient and electromechanical transient analysis). This places extremely stringent requirements on the parallel computing capabilities, floating-point arithmetic accuracy, data transmission bandwidth, and real-time performance of the data processing unit.

[0003] In existing technologies, data processing mainly relies on the following methods, which have significant drawbacks: Centralized processing based on general-purpose CPUs: Its serial execution architecture is difficult to cope with the massive parallel computing requirements inherent in simulation tasks, resulting in processing bottlenecks, limited simulation step size, and inability to meet the strong real-time requirements at the microsecond or even nanosecond level, affecting the simulation accuracy and the realism of system dynamic response analysis.

[0004] Using a single type of accelerated processor (such as pure FPGA or pure DSP): Pure FPGA solution: Although it has strong parallel capabilities, it is difficult to develop and relatively inefficient in implementing complex floating-point algorithms (such as matrix inversion and differential equation solving).

[0005] Pure DSP solution: strong floating-point computing power, but limited data throughput and parallelism, which can easily become a bottleneck when dealing with high-density data streams.

[0006] General data transmission interfaces: Data exchange is carried out using interfaces such as Gigabit Ethernet or low-speed PCIe. The bandwidth is insufficient, the transmission delay is high and uncertain, and it is difficult to achieve high-fidelity, low-latency data interaction between the simulation system and external controllers or power hardware, which restricts the scale and accuracy of hardware-in-the-loop simulation.

[0007] Storage and System Architecture: Storage bandwidth and capacity are not matched with processor computing power, and there is a lack of efficient, dedicated interconnect channels between heterogeneous processors, resulting in high data migration overhead and low overall system collaboration efficiency. Furthermore, the power supply of the boards is not optimized for high-performance computing chips, affecting the long-term stable operation of the system.

[0008] In summary, existing technical solutions suffer from bottlenecks in three aspects: computing power structure, data pathways, and system collaboration, making it difficult for power simulation systems to achieve breakthroughs in processing speed, real-time performance, reliability, and system scale. This invention aims to systematically solve these problems through an innovative heterogeneous acceleration board architecture. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a heterogeneous acceleration board and method for power simulation, which addresses the shortcomings of the prior art and solves the technical problems of low processing efficiency and slow transmission speed of smart grid data processing boards in the prior art.

[0010] The present invention adopts the following technical solution: A heterogeneous acceleration board for power simulation includes a power supply circuit, and also includes an FPGA module, a DSP module, a DDR4 memory module, a DDR3 memory module, an SFP28 fiber optic module, a PCIe 3.0 x16 interface, and a PCIe 2.0 x2 interface. The PCIe 3.0 x16 interface is connected to the GTY interface of the FPGA module to realize real-time data interaction between the external processor and the FPGA module. It uses a dedicated PCIE IP core for FPGA as the controller and the transmission protocol is the standard PCIE 3.0 protocol. The SFP28 fiber optic module is connected to the FPGA module for data interaction in external hardware-in-the-loop simulation, and its transmission protocol with the FPGA module is 64B / 66B. The DDR4 storage module is connected to the FPGA module and is used to store data transmitted from an external processor, SFP28 fiber optic module or DSP module and to process it by the FPGA module. The PCIe 2.0x2 interface is connected to the dedicated PCIe interface of the DSP module to realize data interaction between the external processor and the DSP module. It adopts the function interface provided by the DSP and the transmission protocol is the standard PCIe 2.0 protocol. The DDR3 storage module is connected to the DSP module to store data transmitted from the external processor or FPGA module for processing by the DSP module. The FPGA module and the DSP module are connected through the SRIO interface for communication and data interaction between them.

[0011] Preferably, the FPGA module uses an FPGA chip model of XCVU13P-FHGB2104.

[0012] Preferably, the system also includes a FLASH chip and a USB-to-JTAG chip. The FLASH chip is an MT25QU02GCBB8E12-0SIT, which stores the bit file required for the FPGA chip to operate and is connected to the dedicated pin of the FPGA chip in the FPGA module. The FPGA chip is configured to boot in Master SPI Dual Quad (x8) mode. The USB-to-JTAG chip is an FT4232HL, whose JTAG signal pin is connected to the dedicated JTAG pin of the FPGA chip in the FPGA module. The USB 2.0 differential signal line is connected to the electrostatic discharge protection diode array of the transient voltage suppressor, and the power supply is taken from the 5V power supply provided by the USB interface.

[0013] Preferably, the DDR4 storage module includes two sub-modules, each sub-module containing multiple DDR4 chips. Each sub-module has a bit width of 16x5bit, a capacity of 4GB, and ECC functionality. Each sub-module is connected to three consecutive banks of the FPGA module. The address and control bus of all DDR4 chips are matched at the VTT terminal through matching resistors. The model of the DDR4 chip is MT40A512M16LY-062E IT.

[0014] Preferably, the DSP module uses a TMS320C6678 DSP chip.

[0015] Preferably, the DDR3 storage module includes multiple DDR3 chips, with a module width of 16x5bit, a capacity of 2GB, and ECC functionality. The DDR3 storage module is connected to a dedicated interface of the DSP module, and the addresses and control buses of all DDR3 chips are matched at the VTT terminal through matching resistors. The model of the DDR3 chip is MT41K256M16HA-125IT.

[0016] Preferably, the PCIe 3.0x16 interface and the PCIe 2.0x2 interface are connected to the FPGA module and the DSP module respectively through AC coupling capacitors.

[0017] Preferably, the SFP28 fiber optic module supports a 28Gbps electrical interface and an actual data transmission rate of 25Gbps. A total of 32 optical modules are configured. Each optical module is connected to the GTY BANK of the FPGA module via a 1X high-speed serial bus. All configuration and control signals are pulled up and then converted from 3.3V to 1.8V through a level conversion chip and connected to the HP Bank of the FPGA module. The I2C interface of the SFP28 fiber optic module is expanded through a multi-segment I2C chip.

[0018] Another technical solution of the present invention is a method for using a heterogeneous acceleration board for power simulation, comprising the following steps: S1. Power the board through the power supply circuit. The power supply circuit is taken from the 12V power supply of the PCIE interface standard or an external 12V power supply. It provides working power to the FPGA module, DSP module and various peripherals according to the preset power-on sequence. S2 and FPGA modules receive data from external processors via PCIe 3.0x16 interface or external hardware-in-the-loop simulation data via SFP28 fiber optic module. The received data is stored in DDR4 storage module. S3 and FPGA modules call their own parallel processing resources to process the data in the DDR4 memory module. During the processing, the data that needs to be interacted with the DSP module is transmitted to the DSP module through the SRIO interface. The data received by the DSP module is stored in the DDR3 memory module. The S4 and DSP modules use their own floating-point computing resources to process the data in the DDR3 memory module. After processing, the results are fed back to the FPGA module through the SRIO interface. The S5 and FPGA modules integrate their own processing results with the feedback results from the DSP module, and feed them back to an external processor through the PCIe 3.0x16 interface, or to an external hardware-in-the-loop simulation system through the SFP28 fiber optic module, to complete the real-time processing of power simulation data.

[0019] Preferably, in step S1, the power supply circuit outputs 0.85V core power to the FPGA module through three LTM4650 chips, with a total output current of 150A; two LTM4630 chips provide CVDD power to the DSP module, MGTAVTT power to the GTY of the FPGA module, and 1.8V and 3.3V power to the entire board; two LTM4644 chips provide power to the MGTAVCC of the FPGA module, CVDD1 of the DSP module, and corresponding voltage power to the DDR4 memory module, DDR3 memory module and related I / O. In step S2, the base clock of the board is provided by a temperature-compensated crystal oscillator. The LVDS differential clock output by the crystal oscillator is fanned out by the clock buffer chip and used as the startup clock of the FPGA module, the reference clock of the PL terminal DDR, the DDR clock and PASS clock of the DSP module, and the reference clock of the SFP28 fiber optic module serdes. In step S3, the FPGA module performs parallel processing of matrix operations and FFT digital signal processing tasks, while the DSP module performs floating-point operations on high-computing-power, low-latency real-time signal processing tasks. In step S4, the SRIO interface adopts a point-to-point transmission mode with a data transmission rate of 5Gbps, and the data interaction delay between the FPGA module and the DSP module is in the microsecond range.

[0020] Compared with the prior art, the present invention has at least the following beneficial effects: A heterogeneous acceleration board for power simulation utilizes the hardware parallelism of an FPGA to handle high-throughput data acquisition, preprocessing, and highly parallel algorithm modules; it leverages the powerful floating-point capabilities of a DSP to handle complex control algorithms and mathematical model calculations; and it achieves low-latency, high-bandwidth data interaction between the two via SRIO, forming a collaborative computing pipeline. Simultaneously, the FPGA is configured with high-speed PCIe 3.0 x16 and SFP28 fiber optic interfaces, while the DSP is configured with an independent PCIe 2.0 x2 interface, achieving decoupling and optimized matching of data input / output with the processor, thus solving the data path bottleneck at the system level. This claim lays the hardware foundation for solving the problem of highly real-time power simulation, and its scope of protection is broad and necessary.

[0021] Furthermore, the XCVU13P-FHGB2104 FPGA chip is used, providing up to 3.78 million logic units and 12,288 DSP slices. Its superior parallel processing resources and powerful single-precision floating-point capability (peak INT8 computing power of 38.3 TOP / s) are the key physical guarantees for achieving microsecond-level real-time processing in this invention. The massive logic resources allow for the deployment of more complex and larger-scale parallel computing circuits, while the massive number of DSP slices makes it possible to efficiently execute digital signal processing tasks such as FFT, filter banks, and matrix operations within the FPGA, significantly improving the board's processing efficiency and flexibility for common algorithms in power simulation.

[0022] Furthermore, the FPGA configuration and debugging circuitry employs a high-capacity NOR Flash (MT25QU02GCBB8E12-0SIT) and boots in Master SPI Dual Quad mode, ensuring reliable and rapid loading of complex bitstream files from the FPGA and guaranteeing system startup stability. An integrated USB-to-JTAG chip (FT4232HL) with ESD protection greatly facilitates online debugging, program updates, and fault diagnosis, improving development efficiency and ease of maintenance. This claim protects the specific implementation details for achieving reliable FPGA startup and convenient development.

[0023] Furthermore, the DDR4 memory module architecture includes two 4GB modules with ECC, connected to the FPGA via specific impedance matching. This design provides the FPGA with ultra-high bandwidth (through parallel access from multiple banks) and a large-capacity data buffer, effectively mitigating the mismatch between external data flow and FPGA processing speed. The ECC function enhances data storage reliability, which is crucial for long-term, high-reliability power simulations. This claim protects key memory design solutions for optimizing data buffering and processing performance.

[0024] Furthermore, the TMS320C6678 DSP chip integrates eight high-performance C66x cores, achieving a total floating-point computing power of 160 GFLOPS, and natively supports high-speed interfaces such as SRIO and PCIe. Its powerful centralized floating-point computing capabilities and specialized optimization for real-time signal processing tasks make it an ideal unit for executing complex algorithms in power systems (such as state estimation and stability control algorithms), perfectly complementing FPGAs.

[0025] Furthermore, the DDR3 memory module features ECC and impedance matching, providing a dedicated high-speed data cache for the DSP. This ensures the DSP core can efficiently access data to be processed and intermediate results, reducing waiting time. Impedance matching and ECC also guarantee the integrity and reliability of data transmission. This claim protects the memory subsystem supporting the DSP's efficient operation.

[0026] Furthermore, the PCIe interface is connected via an AC coupling capacitor. This AC coupling capacitor filters out the DC component between the FPGA or DSP chip and the external interface, and achieves voltage level isolation. This is a crucial and necessary circuit design to ensure the quality of high-speed serial signal transmission and prevent damage caused by DC potential differences between chips. This claim protects the fundamental circuit features for the stable and reliable operation of the board's high-speed interface.

[0027] Furthermore, the SFP28 fiber optic module includes 32 optical modules, level conversion, I2C expansion, etc. This elevates the board's data exchange capabilities to a new level (total bandwidth up to 800Gbps), enabling it to simultaneously connect a large number of external power hardware or sensors, greatly expanding the scale and complexity of hardware-in-the-loop simulation. Level conversion and signal processing design ensure reliable interfacing between high-speed optical signals and FPGA logic levels.

[0028] A method for using a heterogeneous acceleration board for power simulation is presented. Step S1 involves power-on timing design to avoid module startup conflicts. Step S2 involves data classification and storage, enabling the FPGA and DSP to process data from different sources in parallel. Steps S3-S4 involve collaborative computation to maximize the advantages of the heterogeneous architecture. Step S5 involves dual-path feedback to adapt to different application scenarios. This process optimization increases board resource utilization to over 90%, reduces total simulation latency by 60% compared to existing disordered processing flows, ensures strong real-time performance in power simulation, simplifies operational logic, and improves board usability.

[0029] Furthermore, the power supply circuit employs multiple LTM series chips to provide each module with precise voltage (accuracy ±2%) and sufficient current (150A total current for the FPGA core power supply), avoiding a decrease in computing power due to voltage fluctuations. Temperature-compensated crystal oscillators and LMK00301 clock buffer chips reduce clock signal phase noise to -120dBc / Hz, improving frequency stability by 80% and ensuring synchronous operation of the FPGA and DSP (coordination delay ≤100ns). The clear division of module functions (FPGA parallel processing, DSP floating-point operations) avoids resource waste, reducing the long-term failure rate of the board by 40% and improving processing accuracy by 30%, further enhancing its practical value.

[0030] In summary, this invention systematically solves the problems of insufficient computing power, high latency, bandwidth bottlenecks, and low system collaboration efficiency in power simulation through a heterogeneous collaborative architecture of FPGA parallel processing, DSP floating-point computing, SRIO high-speed interconnection, and multi-channel high-bandwidth I / O.

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the following description of the relative embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a block diagram of the heterogeneous acceleration board of the present invention; Figure 2 Configure the schematic for the FPGA; Figure 3 Schematic diagram of the FPGA-side PCIe interface; Figure 4 The schematic diagram of the GTY on the FPGA side corresponding to the PCIe interface; Figure 5 Schematic diagram for GPIO configuration on the DSP side; Figure 6 Schematic diagram of other configuration pins on the DSP side; Figure 7 Schematic diagram of the PCIe interface on the DSP side; Figure 8 This is the schematic diagram of the high-speed interface on the DSP side corresponding to PCIe; Figure 9 This is the schematic diagram of DDR3 on the DSP side; Figure 10 This is the schematic diagram of the DSP side of the SRIO interface.

[0034] The components include: 1. FPGA module; 2. PCIe 3.0 x16 interface; 3. SFP28 fiber optic module; 4. DDR4 memory module; 5. DSP module; 6. PCIe 2.0 x2 interface; 7. DDR3 memory module; and 8. power supply circuit. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0039] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0040] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0041] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] This invention provides a heterogeneous acceleration board and method for power simulation. It employs a heterogeneous collaborative architecture of FPGA and DSP modules, combined with SRIO high-speed interconnect, to achieve complementary advantages of parallel computing and high-precision floating-point computing, thereby significantly improving overall computing performance and algorithm flexibility. The PCIe 3.0 x16 interface and SFP28 fiber optic module configured for the FPGA, along with the PCIe 2.0 x2 interface independent of the DSP, jointly construct an ultra-high bandwidth, low-latency internal and external data path, completely eliminating data input / output bottlenecks. The use of large-capacity DDR4 and DDR3 memory modules with ECC function provides a high-speed and reliable data buffer for the processor, ensuring computational continuity. The selection of specific high-performance FPGA and DSP chips provides the physical computing power foundation required for microsecond-level real-time processing. Precise power management circuitry and clock schemes ensure long-term stable operation and high-speed signal transmission quality. AC coupling, impedance matching, and other circuit designs further guarantee signal integrity. Ultimately, through the optimized data reception-collaborative processing-result output method and process, efficient scheduling was achieved, resulting in a comprehensive breakthrough in processing speed, real-time performance, computational accuracy, system reliability, and application scale, providing a solid hardware foundation for strong real-time power simulation.

[0043] Please see Figure 1 The present invention provides a heterogeneous acceleration board for power simulation, which can provide strong real-time processing capabilities for power electronics simulation, including: FPGA module 1, DSP module 5, DDR3 storage module 7, DDR4 storage module 4, SFP28 fiber optic module 3, PCIe 3.0x16 interface 2, PCIe 2.0x2 interface 6, and power supply circuit 8.

[0044] FPGA module 1 utilizes an FPGA chip to process data from an external processor. The FPGA chip's peripheral interfaces include: a DDR4 storage module 4, an SFP28 fiber optic module 3, and a PCIe 3.0 x16 interface 2. The DDR4 storage module 4 stores data from the external processor, optical module, or DSP, awaiting processing by the FPGA. The PCIe 3.0 x16 interface 2 is primarily used for real-time data exchange between the external processor and the FPGA, while the SFP28 fiber optic module 3 is used for data exchange in external hardware-in-the-loop simulation.

[0045] Preferably, the FPGA chip used in this heterogeneous accelerator card is an AMD Xilinx Virtex UltraScale+ FPGA, specifically the XCVU13P-FHGB2104. It has 3.78 million logic cells, including 1.728 million lookup tables (LUTs) and 3.456 million flip-flops, and is equipped with 12,288 DSP slices. It boasts strong single-precision floating-point arithmetic capabilities, with a peak INT8 computing power of 38.3 TOP / s, enabling efficient processing of matrix operations, FFT, and other digital signal processing tasks. These ample resources and multiple interface protocols allow the XCVU13P-FHGB2104 to perform real-time processing more effectively.

[0046] Figure 2 This section describes the configuration bank for the selected FPGA chip XCVU13P-FHGB2104. Pins M1, M2, and M3 of the FPGA are configured during power-on reset. The design will use pull-up resistors by default and DIP switches for pull-down selection, allowing for flexible mode selection. INIT_B, DONE, and PROGRAM_B are pulled up by resistors. PUDC_B and POR_OVERRIDE have reserved pull-up and pull-down resistors to accommodate different selections; the default state is the manual recommended state.

[0047] In this embodiment, the selected FLASH chip is the one recommended by the FPGA manufacturer. The FLASH stores the bit file required for the FPGA chip to operate. The selected FPGA chip's default boot configuration is Master SPI Dual Quad (x8) mode, and it needs to be connected to a dedicated pin of the FPGA. The CS, DQ2, DQ3, and CLK signals of the FLASH chip are all pulled up to 1.8V through pull-up resistors.

[0048] Preferably, the NOR FLASH chip used is model MT25QU02GCBB8E12-0SIT, with a single chip capacity of 2Gbit and a total capacity of 4Gbit.

[0049] In this embodiment, the selected FPGA debugging includes JTAG configuration, which is brought out to the TYPE C physical interface via a USB-to-JTAG protocol conversion chip. The PC can then debug the FPGA chip through the TYPE C interface. The dedicated JTAG pin of the FPGA chip is connected to the JTAG signal pin of the protocol conversion chip; the USB 2.0 differential signal line is connected to the electrostatic discharge (ESD) protection diode array of the transient voltage suppressor (TVS) for electrostatic protection. The conversion chip is powered by the 5V power supply provided by the USB interface.

[0050] Preferably, the USB to JTAG chip used is model FT4232HL.

[0051] Figure 1 In this embodiment, the DDR4 interface uses four common DDR4 chips capable of storing data from external processors, optical modules, or DSPs, and awaiting processing by the FPGA. The schematic design includes two sets of DDR4 modules: each set consists of five DDR4 chips, with a 16x5-bit width, 4GB capacity, and ECC functionality. Each DDR4 module is connected to three consecutive banks on the FPGA, with the connection method strictly adhering to the Xilinx chip datasheet specifications. Simultaneously, all DDR4 address and control buses are matched at the VTT terminal using 39.2Ω matching resistors to ensure the stability and reliability of the address and control signals.

[0052] Preferably, the DDR4 chip used is model MT40A512M16LY-062E IT.

[0053] The PCIe 3.0 x16 interface 2 connects to the FPGA's GTY interface. PCIe 3.0 x16 interface 2 uses a dedicated PCIe IP core in the FPGA as the PCIe controller, employing the standard PCIe 3.0 protocol with a data transmission width of 16 x lanes (16 transmit and 16 receive channels). The PCIe 3.0 standard increases the single-channel data transmission rate to 8 GT / s, with a single-channel unidirectional bandwidth approaching 1 GB / s. With an x16 (16 lanes) configuration, the total bidirectional bandwidth reaches 32 GB / s, and the unidirectional bandwidth reaches 16 GB / s, representing a significant leap compared to the 5 GT / s rate of PCIe 2.0, fully meeting the bandwidth requirements of hardware in power simulation. PCIe 3.0 innovatively introduces 128b / 130b encoding, requiring only 2 bits of overhead to transmit 128 bits of effective data, achieving a transmission efficiency close to 100%. Compared to the previous PCIe 2.0 which used 8b / 10b encoding, PCIe 3.0 can transmit more effective data at the same speed. Therefore, the PCIe interface of this heterogeneous accelerator card can also meet the needs of high-bandwidth data transmission.

[0054] Figure 3 For the PCIe 3.0x16 interface schematic design, the WAKE and PCIE reset signals are converted from 3.3V to 1.8V through a level conversion chip and then connected to the dedicated pin of the HP Bank on the FPGA chip.

[0055] Figure 4 The schematic diagram shows four consecutive GTY banks of the FPGA chip. Each GTY bank has four pairs of high-speed transceiver serial channel interfaces. The DC signal is filtered out between the PCIe 3.0x16 interface and the FPGA through AC coupling capacitors. The PCB traces have a characteristic impedance difference of 85Ω.

[0056] Figure 1In this design, the SFP28 fiber optic module 3 is used for data interaction in external hardware-in-the-loop simulation. Data is transmitted to the FPGA chip for further processing via the SFP28 fiber optic module. The SFP28 fiber optic module supports a 28Gbps electrical interface, with an actual data transmission rate of 25Gbps, a significant improvement over the 10Gbps rate of the SFP+. The heterogeneous accelerator card schematic design of this invention uses 32 optical modules, each connected to the FPGA's GTY BANK via a 1X high-speed serial bus. A total of 8 high-speed serial lines connect to two adjacent MGT Banks of the FPGA. All configuration and control signals are pull-up processed and converted from 3.3V to 1.8V using a level conversion chip, connecting to the FPGA chip's HP Bank. The I2C interface used in the SFP28 fiber optic module is expanded using a multi-segment I2C chip.

[0057] Please see Figure 1 In this embodiment, DSP module 5 is implemented using a DSP chip to process computational tasks issued from an external processor. The DSP has an external DDR3 memory module for storing data issued by the processor or data used during interaction with the FPGA. It also has an external PCIe 2.0x2 interface for data interaction with the external processor and transmission of related instructions. An on-board communication interface, SRIO, is used for communication between the FPGA and the DSP, as well as for data exchange.

[0058] Please see Figure 5 This diagram illustrates the configuration circuit principle of the general purpose input / output (GPIO) pins on side 5 of the DSP module. The diagram details the external connections of multiple GPIO pins (such as GPIO00, GPIO01, GPIO02, GPIO03, GPIO05, GPIO10, etc.) of the DSP chip (model TMS320C6678). These pins are connected to power or ground via pull-up or pull-down resistors, and some pins are also connected to DIP switches. The core function of this configuration circuit is to implement the hardware boot mode and function configuration of the DSP chip. By setting pull-up / pull-down resistor combinations controlled by DIP switches for specific GPIO pins (such as GPIO01, GPIO02, etc.), different logic level combinations can be input to the DSP chip when the system powers on, thereby instructing the chip to boot from different storage devices (such as SPI Flash, I2C EEPROM, etc.) or interfaces (such as PCIe, SRIO). This design provides flexible boot configuration capabilities, allowing the same accelerator board to adapt to different application scenarios and program loading requirements, enhancing the system's versatility and maintainability.

[0059] Please see Figure 7The PCIe reset signal from the external motherboard or backplane first passes through a level conversion chip, converting the signal level from 3.3V to 1.8V before being connected to the dedicated configuration pin (e.g., GPIO00) of the DSP chip. The diagram also includes the power filtering and decoupling circuitry related to this interface. The key to this design lies in signal level compatibility and system stability management. The PCIe standard commonly uses a 3.3V signal level, while the I / O voltage of the DSP chip used in this embodiment may be 1.8V. The introduction of the level conversion chip ensures correct and reliable communication between signals in different voltage domains, preventing signal errors or chip damage. Introducing the PCIe reset signal to the DSP's GPIO pin allows the DSP to sense reset events from the host system, thereby performing corresponding state initialization and synchronization, enhancing the reliability and controllability of the entire board as a PCIe slave device working in conjunction with the host system.

[0060] Please see Figure 8 This diagram illustrates the physical layer connection principle of the high-speed differential signal lines (including transmit pairs PCIEP / PCIEN and receive pairs PCIERP / PCIERN) of the PCIe 2.0 x2 interface 6 of a DSP chip. The diagram clearly shows that AC coupling capacitors are connected in series between the DSP chip pins and the connectors. The PCB traces are labeled with the differential impedance requirements (typically 85Ω or 100Ω). This part of the circuit is the physical foundation and quality assurance for achieving high-speed PCIe data transmission.

[0061] AC coupling capacitors: Their core function is to isolate the DC bias voltage of the chips on both sides of the communication, allowing only AC signals (i.e., high-speed data) to pass through. This prevents damage to the chips caused by potential ground potential differences between the FPGA, DSP, and the host, making them an essential and critical protection and coupling component in high-speed serial interface design.

[0062] Differential routing and impedance control: PCIe signals use differential transmission, which has the advantages of strong anti-interference capability and low noise. During PCB design, the trace width and spacing of differential pairs are strictly controlled to achieve the target characteristic impedance (e.g., 85Ω). This aims to achieve impedance matching, minimize signal reflection and distortion during transmission, ensure signal integrity, and thus guarantee data transmission stability and low bit error rate at speeds up to 5.0GT / s.

[0063] Preferably, the selected chip is the TI TMS320C6678, which is based on the KeyStone I architecture and is designed for high-performance, low-latency real-time signal processing scenarios. This chip features eight C66x VLIW DSP cores, each supporting eight threads in parallel (VLIW8 architecture), with a maximum clock speed of 1.25GHz. Each core delivers 40 GMACS (fixed-point) / 20 GFLOPS (floating-point), for a total of 320 GMACS / 160 GFLOPS across all eight cores. Each core has 32KB L1P + 32KB L1D, 1MB shared L2, and 4GB addressable external DDR3 (ECC supported). Supported peripherals include 2×SRIO (6.25Gbps / link), 2×PCIe Gen2, 1×Gigabit Ethernet, and 2×HyperLink. All GPIO pins of the DSP have pre-installed pull-up / pull-down resistors; except for GPIO00 which is pulled up by default, all other GPIO interfaces are in pull-down mode by default. By configuring the GPIO01, GPIO02, GPIO03, GPIO05, and GPIO10 pins, the default pull-down resistors can be used, and pull-up switches can be used to select the pull-up pins, thus enabling flexible selection of multiple startup modes. Figure 6 All configurations include pre-installed pull-up and pull-down resistors, allowing for the selection of different pull-up and pull-down resistors based on the needs of different scenarios.

[0064] The PCIe 2.0 x2 interface connects to the DSP's dedicated PCIe interface. The PCIe 2.0 x2 interface uses the function interface provided by the DSP, and the transmission protocol is the standard PCIe 2.0 protocol, with a data transmission width of 2 x Lanes. It increases the single-channel data transmission rate from 2.5GT / s in PCIe 1.0 to 5GT / s, with a single-channel unidirectional bandwidth of approximately 500MB / s. In a common x2 configuration, PCIe 2.0 can achieve a total bidirectional bandwidth of up to 2GB / s. It continues the 8b / 10b encoding scheme of its predecessor. This method requires an additional 2 bits of bandwidth for every 8 bits of valid data transmitted, resulting in a 20% transmission overhead, but the technology is mature and stable, ensuring reliable data transmission. It also uses a point-to-point transmission mode, with each device having a dedicated transmission line, avoiding the bandwidth contention problem in traditional shared buses, and supports full-duplex operation, allowing simultaneous data transmission and reception. The PCIe 2.0 x2 interface and the DSP use AC coupling capacitors to filter out DC signals, and the PCB traces have a differential impedance of 85Ω.

[0065] Please see Figure 3 This is a schematic design for a PCIe 2.0 x16 interface. The PCIe reset signal is converted from a 3.3V signal to a 1.8V signal through a level conversion chip and then connected to the GPIO00 pin of the DSP chip.

[0066] Please see Figure 1In this embodiment, the DDR3 interface 7 used is a common DDR3 chip, capable of storing data from an external processor or FPGA and waiting for processing by the DSP. The specific schematic design includes one DDR3 module: this module consists of five DDR3 chips, each with a 16x5-bit width, a 2GB capacity, and ECC functionality. The DDR3 memory modules are connected to the dedicated DSP interface. All DDR3 address and control buses are matched at the VTT terminal using a 39.2Ω matching resistor to ensure the stability and reliability of the address and control signals.

[0067] Preferably, the DDR3 chip used is the MT41K256M16HA-125IT.

[0068] Please see Figure 9 and Figure 10 The DSP and FPGA modules are connected via the SRIO interface. It is primarily used for data exchange between the DSP and FPGA. The SRIO (Serial RapidIO) interface is its core high-speed interconnect interface, designed for multi-DSP cascading and heterogeneous interconnection between DSP and FPGA / ARM. It supports high bandwidth in point-to-point transmission mode with latency in the microsecond range, supporting speeds of up to 5Gbps. It connects to the FPGA using AC coupling, and the PCB traces have 100Ω impedance matching for the SRIO differential pair.

[0069] The power supply scheme of the accelerator card of this invention meets the voltage requirements of the entire board, provides the working power required by the FPGA module, DSP module and peripherals, meets the power-on sequence, and the power supply circuit can be obtained from the 12V power supply of the PCIe interface standard or from an external 12V power supply.

[0070] Please see Figure 1The power supply circuit 8 provides suitable power for the entire board, and establishes the FPGA and DSP power-on sequences. The 0.85V core power supply in the FPGA is output from three onboard LTM4650 chips, with a total output current of 150A. Two onboard LTM4630 chips are provided; the first chip's first output of 18A provides CVDD power to the DSP. The first chip's second output of 18A provides power to the FPGA's GTY's MGTAVTT. The second chip's first output of 18A provides 1.8V power to the entire board. The second chip's second output of 18A provides 3.3V power to the entire board. Two onboard LTM4644 chips are also provided; the first LTM4644's two power outputs, at 0.9V@8A and 1.0V@8A respectively, power the FPGA's MGTAVCC and the DSP's CVDD1. The second LTM4644 outputs three power supplies: 1.2V@8A, 1.5V@4A, and 2.5V@4A. The 1.2V@8A supply powers DDR4 and related I / O, while the 1.5V@4A supply powers DDR3 and related I / O.

[0071] The overall clocking scheme for the board is as follows: the base clock is provided by the board's crystal oscillator. The digital clock section mainly provides the FPGA's startup clock, the PL's DDR clock, and the SERDES reference clock. To ensure high-quality output clocks and avoid temperature-induced offsets, all crystals are temperature-compensated (TCC) oscillators. The crystal oscillator outputs a 100MHz LVDS differential clock, which, after being fanned out by a clock buffer chip, is primarily used as the FPGA's startup clock, the PL's DDR reference clock, and the DSP's DDR and PASS clocks. Two crystal oscillators each output 125MHz and 156.25MHz LVDS differential clocks, which, after being fanned out by a clock buffer chip, provide the reference clock for the SERDES used in fiber optic cables. These two clocks are optional to meet the line rate requirements of 10.3125Gbps and 10Gbps.

[0072] Preferably, the clock buffer chip uses the LMK00301 chip model.

[0073] This invention also provides a method for using a heterogeneous acceleration board for power simulation, comprising the following steps: S1. Power supply circuit 8 supplies power to the board. Power supply circuit 8 is taken from the 12V power supply of the PCIE interface standard or an external 12V power supply. It provides working power to FPGA module 1, DSP module 5 and various peripherals according to the preset power-on sequence. The power supply circuit 8 outputs 0.85V core power to FPGA module 1 through three LTM4650 chips, with a total output current of 150A; it provides CVDD power to DSP module 5 and MGTAVTT power to FPGA module 1's GTY through two LTM4630 chips, and provides 1.8V and 3.3V power to the entire board; it provides power to FPGA module 1's MGTAVCC and DSP module 5's CVDD1 through two LTM4644 chips, and provides corresponding voltage power to DDR4 memory module 4, DDR3 memory module 7 and related I / O.

[0074] S2, FPGA module 1 receives data from an external processor through PCIe 3.0x16 interface 2, or receives external hardware-in-the-loop simulation data through SFP28 fiber optic module 3, and stores the received data in DDR4 storage module 4. In step S2, the base clock of the board is provided by a temperature-compensated crystal oscillator. The LVDS differential clock output by the crystal oscillator is fanned out by the clock buffer chip and used as the startup clock of FPGA module 1, the reference clock of PL terminal DDR, the DDR clock and PASS clock of DSP module 5, and the reference clock of SFP28 fiber optic module 3 serdes.

[0075] S3, FPGA module 1 calls its own parallel processing resources to process the data in DDR4 storage module 4. During the processing, the data that needs to be interacted with DSP module 5 is transmitted to DSP module 5 through SRIO interface. The data received by DSP module 5 is stored in DDR3 storage module 7. FPGA module 1 performs parallel processing of matrix operations and FFT digital signal processing tasks, while DSP module 5 performs floating-point operations on high-performance, low-latency real-time signal processing tasks.

[0076] S4 and DSP module 5 call their own floating-point computing resources to process the data in DDR3 storage module 7, and after processing, feed the result back to FPGA module 1 through SRIO interface; The SRIO interface adopts a point-to-point transmission mode with a data transmission rate of 5Gbps. The data interaction delay between FPGA module 1 and DSP module 5 is in the microsecond range.

[0077] The S5 and FPGA modules 1 integrate their own processing results with the feedback results from the DSP module 5, and feed them back to the external processor through the PCIe 3.0x16 interface 2, or to the external hardware-in-the-loop simulation system through the SFP28 fiber optic module 3, to complete the real-time processing of power simulation data.

[0078] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0079] To verify the actual performance of the heterogeneous acceleration board described in this invention, a comparative experiment was designed to compare and test the board of this invention with two existing typical solutions: Solution A (software simulation based on high-end multi-core CPU), Solution B (acceleration board based on pure FPGA), and Solution C (heterogeneous acceleration board of this invention).

[0080] The testing platform is uniformly connected to the same real-time simulation model of the power system (containing 200 simulation nodes, 500 branches, and adopting an electromagnetic transient model).

[0081] Key performance indicator comparison test data

[0082] Through the above simulation and experimental data, the advantages of this invention compared to the prior art can be quantitatively confirmed: A qualitative breakthrough has been achieved in performance: the power simulation step size has been advanced from the mainstream 10-50 microsecond level to the 1 microsecond level, and ultra-real-time simulation has been realized. This makes it possible to study faster electromagnetic transient processes and test more sensitive protection devices.

[0083] In terms of efficiency, system-level optimization has been achieved: through heterogeneous division of labor (FPGA parallelism, DSP floating-point) and high-speed interconnect (SRIO), the overall computation latency (2.5µs) is much lower than the simple sum of the individual work of each part, resulting in a synergistic acceleration effect of 1+1>2.

[0084] In terms of reliability, it meets the "industrial grade" requirements: 72 hours of trouble-free operation, extremely low data error and good temperature control performance, proving that it is not a laboratory prototype, but a mature solution that can be directly applied to a high-reliability simulation and testing system in industrial settings.

[0085] In terms of applications, it expands the boundaries of "possibilities": extremely low data interaction latency (<5µs) and high determinism (jitter ±15ns) make it possible to perform large-scale, high-precision hardware-in-the-loop testing of power electronic devices, which was previously difficult to achieve, thus expanding the scope of power system simulation testing.

[0086] Therefore, the heterogeneous acceleration board provided by this invention is not a simple hardware stacking, but a deep architectural innovation targeting the core pain points in the field of power simulation. Experimental data fully demonstrate that it has achieved significant improvements in key indicators such as processing speed, real-time performance, accuracy, reliability, and system bandwidth, providing a crucial hardware foundation for building a next-generation high-precision, high-real-time, and highly reliable smart grid simulation and testing platform.

[0087] In summary, the present invention provides a heterogeneous acceleration board and method for power simulation, achieving significant technical effects: Significantly improves processing performance and real-time performance: By combining the advantages of parallel computing and high-precision floating-point computing through heterogeneous collaboration between FPGA and DSP, the data processing speed is increased by tens of times compared with traditional general-purpose processor solutions. It can support strong real-time power system simulation with microsecond-level steps, meeting the needs of smart grids for high-precision dynamic analysis.

[0088] Completely eliminates data bandwidth bottlenecks: Integrating PCIe 3.0 x16, SFP28 (25Gbps) fiber optic interfaces and on-board SRIO high-speed interconnects, an ultra-high bandwidth, low-latency data path is formed from the external to the internal processing unit. This enables the non-blocking real-time throughput of massive simulation data, which is especially suitable for large-scale hardware-in-the-loop simulation and realizes high-fidelity data interaction with a large number of power hardware and controllers.

[0089] Enhancing system reliability and stability: Comprehensive reliability design was implemented, from chip selection (such as ECC-enabled memory) to circuit design (AC coupling, impedance matching, and power timing management). Dedicated power supply and clocking solutions ensure long-term stable operation of high-performance chips in complex electromagnetic environments, guaranteeing the continuity and reliability of power simulation system tests, especially for critical control and protection systems.

[0090] Enhancing Development Flexibility and System Integration: This invention highly integrates heterogeneous computing, high-speed I / O, and large-capacity storage onto a single board, connecting to the host via a standard PCIe interface. This greatly simplifies the system architecture and reduces integration difficulty. Furthermore, the programmability of the FPGA and the software programmability of the DSP allow the board to flexibly adapt to various power simulation algorithms and application scenarios, offering strong scalability.

[0091] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A heterogeneous acceleration board for power simulation, comprising a power supply circuit (8), characterized in that, It also includes an FPGA module (1), a PCIe 3.0x16 interface (2), an SFP28 fiber optic module (3), a DDR4 storage module (4), a DSP module (5), a PCIe 2.0x2 interface (6), and a DDR3 storage module (7). The PCIe 3.0x16 interface (2) is connected to the GTY interface of the FPGA module (1) to realize real-time data interaction between the external processor and the FPGA module (1). It uses the FPGA dedicated PCIE IP core as the controller and the transmission protocol is the standard PCIE3.0 protocol. The SFP28 fiber optic module (3) is connected to the FPGA module (1) for data interaction in external hardware-in-the-loop simulation. Its transmission protocol with the FPGA module (1) is 64B / 66B. The DDR4 storage module (4) is connected to the FPGA module (1) and is used to store data transmitted from an external processor, SFP28 fiber optic module (3) or DSP module (5) and to process it by the FPGA module (1). The PCIe 2.0x2 interface (6) is connected to the dedicated PCIe interface of the DSP module (5) to realize data interaction between the external processor and the DSP module (5). It adopts the function interface provided by the DSP and the transmission protocol is the standard PCIE2.0 protocol. The DDR3 storage module (7) is connected to the DSP module (5) to store data transmitted from the external processor or FPGA module (1) and to be processed by the DSP module (5). The FPGA module (1) and the DSP module (5) are connected through the SRIO interface for communication and data interaction between the two.

2. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The FPGA module (1) uses an FPGA chip model of XCVU13P-FHGB2104.

3. The heterogeneous acceleration board for power simulation according to claim 1 or 2, characterized in that, It also includes a FLASH chip and a USB to JTAG chip. The FLASH chip is MT25QU02GCBB8E12-0SIT, which stores the bit file required for the FPGA chip to work and is connected to the dedicated pin of the FPGA chip in the FPGA module (1). The FPGA chip is configured to start in Master SPI Dual Quad (x8) mode. The USB to JTAG chip is FT4232HL, and its JTAG signal pin is connected to the dedicated JTAG pin of the FPGA chip in the FPGA module (1). The USB 2.0 differential signal line is connected to the electrostatic discharge protection diode array of the transient voltage suppressor, and the power supply is taken from the 5V power supply provided by the USB interface.

4. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The DDR4 storage module (4) includes two sub-modules. Each sub-module contains multiple DDR4 chips. Each sub-module has a bit width of 16x5bit, a capacity of 4GB, and ECC functionality. Each sub-module is connected to three consecutive banks of the FPGA module (1). The address and control bus of all DDR4 chips are matched at the VTT terminal through matching resistors. The model of the DDR4 chip is MT40A512M16LY-062EIT.

5. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The DSP module (5) uses a TMS320C6678 DSP chip.

6. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The DDR3 storage module (7) contains multiple DDR3 chips. The module has a bit width of 16x5bit, a capacity of 2GB, and ECC functionality. The DDR3 storage module (7) is connected to the dedicated interface of the DSP module (5). The addresses and control buses of all DDR3 chips are matched at the VTT terminal through matching resistors. The model of the DDR3 chip is MT41K256M16HA-125IT.

7. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The PCIe 3.0x16 interface (2) and PCIe 2.0x2 interface (6) are connected to the FPGA module (1) and DSP module (5) respectively through AC coupling capacitors.

8. The heterogeneous acceleration board for power simulation according to claim 1, characterized in that, The SFP28 fiber optic module (3) supports a 28Gbps electrical interface and has an actual data transmission rate of 25Gbps. A total of 32 optical modules are set up. Each optical module is connected to the GTY BANK of the FPGA module (1) through a 1X high-speed serial bus. All configuration and control signals are pulled up and then converted from 3.3V to 1.8V through a level conversion chip and connected to the HP Bank of the FPGA module (1). The I2C interface of the SFP28 fiber optic module (3) is expanded through a more than 1-point I2C chip.

9. A method of using the heterogeneous acceleration board for power simulation as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Power the board through the power supply circuit (8). The power supply circuit (8) is taken from the 12V power supply of the PCIE interface standard or the external 12V power supply. It provides working power to the FPGA module (1), DSP module (5) and various peripherals according to the preset power-on sequence. S2, FPGA module (1) receives data sent by external processor through PCIe 3.0x16 interface (2), or receives external hardware-in-the-loop simulation data through SFP28 fiber optic module (3), and stores the received data in DDR4 storage module (4). S3, FPGA module (1) calls its own parallel processing resources to process the data in DDR4 storage module (4). During the processing, the data that needs to be interacted with DSP module (5) is transmitted to DSP module (5) through SRIO interface. The data received by DSP module (5) is stored in DDR3 storage module (7). S4, DSP module (5) calls its own floating-point computing resources to process the data in DDR3 storage module (7), and after processing, it feeds back the result to FPGA module (1) through SRIO interface. S5, FPGA module (1) integrates its own processing results with the feedback results of DSP module (5), and feeds them back to the external processor through PCIe 3.0x16 interface (2), or to the external hardware-in-the-loop simulation system through SFP28 fiber optic module (3), to complete the real-time processing of power simulation data.

10. The method of using the heterogeneous acceleration board for power simulation according to claim 9, characterized in that, In step S1, the power supply circuit (8) outputs 0.85V nuclear power to the FPGA module (1) through 3 LTM4650 chips, with a total output current of 150A; it provides CVDD power to the DSP module (5) and MGTAVTT power to the GTY of the FPGA module (1) through 2 LTM4630 chips, and provides 1.8V and 3.3V power to the whole board; it provides power to the MGTAVCC of the FPGA module (1), the CVDD1 of the DSP module (5) through 2 LTM4644 chips, and provides corresponding voltage power to the DDR4 memory module (4), the DDR3 memory module (7) and related IO. In step S2, the base clock of the board is provided by a temperature-compensated crystal oscillator. The LVDS differential clock output by the crystal oscillator is fanned out by the clock buffer chip and used as the startup clock of the FPGA module (1), the reference clock of the DDR of the PL terminal, the DDR clock and PASS clock of the DSP module (5), and the reference clock of the SFP28 fiber optic module (3) serdes. In step S3, the FPGA module (1) performs parallel processing of matrix operations and FFT digital signal processing tasks, and the DSP module (5) performs floating-point operations on high-computing-power, low-latency real-time signal processing tasks. In step S4, the SRIO interface adopts a point-to-point transmission mode with a data transmission rate of 5Gbps. The data interaction delay between the FPGA module (1) and the DSP module (5) is in the microsecond range.

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