Simulation logic system design method and device and storage medium

Abstract

The invention provides a method for simulating logic system design on a hardware simulation tool, and the method comprises the steps: receiving a simulation mode instruction which comprises a first instruction used for enabling the hardware simulation tool to be in a prototype verification mode or a second instruction used for enabling the hardware simulation tool to be in a debugging mode; in response to the received first instruction, enabling the hardware simulation tool to run in the prototype verification mode; and responding to the received second instruction, and enabling the hardware simulation tool to run in the debugging mode.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a method for simulating logic system design, electronic devices, and storage media. Background Technology

[0002] Hardware simulation tools (e.g., prototyping boards or hardware emulators) can prototype and debug a logic system design comprising one or more modules. This logic system design can be, for example, an application-specific integrated circuit (ASIC) or a system-on-a-chip (SoC) design. Therefore, the logic system design being tested in the simulation tool can also be called a design under test (DUT). The simulation tool can simulate the DUT using one or more configurable components (e.g., field-programmable gate arrays (FPGAs), including performing various operations on the DUT, thereby testing and verifying the functionality of each module of the DUT before manufacturing. Furthermore, by connecting various peripheral daughter cards to the simulation tool, the effectiveness of the DUT operating as a complete system with various peripherals can also be tested.

[0003] There are many software programs that accompany hardware simulation tools, such as compilers, synthesizers, and debuggers.

[0004] The compiler compiles the source code of the logic system design, the synthesizer synthesizes the logic system design into a netlist and programs it into the FPGA, and the debugger implements some simple debugging functions. It is understood that the above software runs on the host machine connected to the hardware simulation tool.

[0005] Hardware simulation tools can include, for example, prototyping boards and hardware emulators. Typically, prototyping boards focus on the overall operation of the electronic system, emphasizing speed, and usually lack debugging capabilities. Hardware emulators, on the other hand, focus on simulating the chip design itself, emphasizing debugging capabilities, but are slower. Summary of the Invention

[0006] A first aspect of this application provides a method for simulating a logic system design on a hardware emulation tool. The method includes: receiving a simulation mode instruction, the simulation mode instruction including a first instruction for putting the hardware emulation tool into a prototype verification mode or a second instruction for putting the hardware emulation tool into a debug mode; responding to receiving the first instruction, causing the hardware emulation tool to run in the prototype verification mode; and responding to receiving the second instruction, causing the hardware emulation tool to run in the debug mode.

[0007] A second aspect of this application provides an electronic device comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method as described in the first aspect.

[0008] A third aspect of this application provides a non-transitory computer-readable storage medium storing a set of instructions for a computer, which, when executed, causes the computer to perform the method described in the first aspect. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of the structure of an exemplary host according to an embodiment of this application is shown.

[0011] Figure 2 A schematic diagram of a simulation system according to an embodiment of this application is shown.

[0012] Figure 3 The diagram illustrates two modes of simulating a logic system design on a simulation tool according to embodiments of this application.

[0013] Figure 4 A schematic diagram illustrating the operation of the simulation tool according to an embodiment of this application is shown.

[0014] Figure 5 A flowchart illustrating a method for simulating a logic system design on a hardware simulation tool according to an embodiment of this application is shown. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connection" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0017] As mentioned above, both prototype verification boards and hardware emulators are hardware simulation tools and are similar at the hardware level. However, in actual use, while prototype verification boards can continuously provide prototype simulation at a high speed, they cannot record or restore errors that occur during the simulation process, let alone debug them. Hardware emulators can record and restore simulation errors using triggering and other methods, but their running speed is very slow, and hardware emulators themselves are very expensive.

[0018] To address the aforementioned problems, the inventors of this application attempt to provide a hardware simulation tool that simultaneously possesses prototyping and hardware simulation capabilities. Typically, prototyping and hardware simulation cannot be performed concurrently on a single hardware device. However, as mentioned above, prototyping is slow, while hardware simulation is fast. If the hardware simulation tool provided in this application were to operate in both modes at the same clock frequency, the efficiency of the prototyping mode would be significantly reduced. Therefore, how to support both prototyping and hardware simulation capabilities while ensuring the overall operating speed of the hardware simulation tool is a pressing technical problem that needs to be solved.

[0019] In view of this, embodiments of this application provide a method for simulating logic system design on a hardware simulation tool, which effectively improves the overall efficiency of the hardware simulation tool by providing different clock frequencies to different operating modes of the hardware simulation tool.

[0020] Figure 1 A schematic diagram of a host 100 according to an embodiment of this application is shown. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the electronic device via the bus 110.

[0021] Processor 102 may be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. Figure 1 As shown, processor 102 may include multiple processors 102a, 102b and 102c.

[0022] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulation test design can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the techniques of this disclosure) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0023] Network interface 106 can be configured to provide communication with other external devices to host 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0024] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0025] Bus 110 can be configured to transfer information between various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0026] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this application, and does not necessarily include all the components shown in the figures.

[0027] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of this application is shown.

[0028] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202.

[0029] Simulation tool 202 is a hardware system used to simulate a design under test (DUT). Simulation tool 202 can be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test can be combinational logic circuits, sequential logic circuits, or a combination of both. Simulation tool 202 may include one or more configurable circuits (e.g., an FPGA) for simulating the design under test.

[0030] The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 to enable communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 may include one or more interfaces with electrical connectivity. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN port, an optical fiber interface, an IEEE1394 (FireWire) interface, etc. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a Wi-Fi interface, a Bluetooth interface, etc.

[0031] The host 100 can transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 can also transmit simulation data to the host 100 via the interface unit 2022.

[0032] The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values ​​generated by the design under test during the simulation process can be read by the host 100. It is understood that the memory 2024 may also be independent of the simulation tool 202, for example, by using an external memory.

[0033] Simulation tool 202 may also include FPGA 2026 for hardware implementation of the logic system design onto the FPGA. It is understood that simulation tool 202 may include multiple FPGAs; the figure is for illustrative purposes only.

[0034] In addition to connecting to the host 100, the emulation tool 202 can also be connected to one or more daughter cards 204 via the interface unit 2022.

[0035] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using simulation tool 202 for prototype verification. Prototype verification refers to a verification method that, before chip fabrication, aims to reproduce the chip's real-world usage scenario as accurately and completely as possible to verify the chip's functionality. Daughter card 204 may include memory daughter cards (e.g., providing a DDR memory interface), communication daughter cards (e.g., providing multiple network interfaces or wireless network card interfaces), etc.

[0036] Host 100 can be used to configure simulation tool 202 to simulate a design under test (DUT), which can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed using a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). Configuring simulation tool 202 on host 100 can include configuring the simulation environment (e.g., the connection relationships between multiple simulation tools 202 or the connection relationships between simulation tools and daughter cards).

[0037] Host 100 can compile the logical system design in source code form into an executable file. From a design perspective, the logical system design may include the design under test and the corresponding testbench.

[0038] like Figure 2As shown, host 100 can compile logic system design 210 (hereinafter also referred to as design 210) into an executable file for configuration onto FPGA 2026 on simulation tool 202. Simulation tool 202 can be HuaPro P2E simulation tool produced by Xinhuazhang Co., Ltd. FPGA 2026 can simulate design 210. It is understood that simulation tool 202 may include multiple FPGAs, and each FPGA may simulate only a portion of the logic system design (e.g., one or more modules).

[0039] From a comprehensive perspective, a logic system design can include synthesizable and non-synthesizable parts. Synthesizable parts typically correspond to the actual physical design (e.g., a chip), while non-synthesizable parts usually include initialization modules, test benches, etc. The executable file formed after compiling the non-synthesizable parts can usually be run by the host computer. The synthesizable parts, after compilation, still need to be synthesized to form a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable parts to simulate the logic system design.

[0040] The host 100 can receive requests from the user to debug the design under test (DUT). As described above, the DUT may include one or more modules. The description of the DUT can be completed using a hardware description language. The host 100 can perform synthesis based on the description of the DUT to generate, for example, a gate-level circuit netlist (not shown). This gate-level circuit netlist of the DUT can be loaded into a simulation tool 202 and run, thereby forming a circuit structure corresponding to the DUT within the simulation tool 202. Therefore, the circuit structure of the DUT can be obtained based on the description, and correspondingly, the circuit structure of each block in the DUT can be obtained similarly.

[0041] Figure 3 The diagram illustrates two modes of simulating a logic system design on a simulation tool 202 according to embodiments of this application.

[0042] The core function of the prototype verification board is to work in conjunction with daughter card 204 to perform rapid simulation of the electronic system. The core function of the hardware emulator is to debug errors during the simulation process. Debugging functionality typically requires the hardware emulator to record the state of the logic system design over multiple clock cycles and restore the logic system design to a specific clock cycle. In some embodiments, the hardware emulator can store the data that needs to be saved in a database in the memory 104 of the host 100.

[0043] The simulation tool 202 according to the embodiments of this application can, upon request, collaborate with the daughter card 204 in prototype verification mode to perform rapid simulation of the electronic system, and can also, upon request, debug the logic system design in debug mode. That is, the simulation tool 202 according to the embodiments of this application has both prototype verification and hardware simulator functions, thus simultaneously possessing the efficiency of rapid simulation and the function of debugging.

[0044] like Figure 3 As shown, mode 302 is the prototype verification mode, and mode 304 is the debug model. Because the simulation tool 202 calls different external resources in prototype verification mode and debug model, therefore... Figure 3 Different dashed boxes are used to combine different external resources (e.g., daughter card 204 and the database stored in memory 104 on host 100) with hardware emulation tool 202 to more clearly illustrate the embodiments of this application. It is understood that the connection and collaboration between external resources and emulation tool 202 can always exist and is not disconnected because emulation tool 202 is in different modes.

[0045] When simulation tool 202 is in mode 302, it simulates and emulates design 210 through communication with daughter card 204 and configurable components within the simulation tool (e.g., FPGA 2026). In some embodiments, simulation tool 202 and daughter card 204 are connected; simulation tool 202 provides a simulation environment and tools, while daughter card 204 provides the ability to simulate external devices. In mode 302, the system can operate at a higher speed.

[0046] like Figure 3 As shown, mode 304 is the debugging mode. When the simulation tool 202 is in mode 304, it can save the values ​​of key signals in the target time period to be debugged to the database for subsequent debugging steps. In some embodiments, the database may reside in the memory 104 of the host 100. Through interface 2022, the host 100 can read the values ​​of key signals of the design 210 from the simulation tool 202 and store them in the memory 104. Key signals may include the primary inputs of the logic system design and the register outputs of the logic system design. The primary inputs are typically signals that stimulate the DUT to run, and other signals of the DUT can be determined based on the values ​​of the primary inputs and the description of the DUT. For example, the outputs and intermediate signal values ​​of a combinational logic circuit can be calculated based on the input signals of the combinational logic circuit and the structure of the combinational logic circuit. In some embodiments, the register outputs of the logic system design may also affect the behavior of the logic system design and are therefore also included in the key signals.

[0047] The prototype verification board runs faster, while the hardware emulator runs slower. Similarly, the simulation tool 202 can run faster in prototype verification mode (e.g., up to 10 MHz), while the simulation tool 202 runs slower in debug mode (e.g., 1 MHz).

[0048] Typically, in order to implement both modes simultaneously on the simulation tool 202, it is necessary to reduce the running speed of the prototype verification mode to match the running speed of the debug mode. This significantly reduces the overall running speed of the hardware simulation tool.

[0049] Therefore, how to ensure the overall running speed of hardware simulation tools while supporting prototype verification mode and debugging mode is a technical problem that urgently needs to be solved.

[0050] In response to this problem, the inventors of this application have further proposed the following embodiments.

[0051] Figure 4 A schematic diagram showing the operation mode of the simulation tool 202 implemented according to an embodiment of this application is shown.

[0052] It is understood that the two modes of simulation tool 202, prototype verification mode and debugging mode, cannot be run in parallel. In order to improve the overall running speed of the hardware simulation tool, different clock frequencies are provided for the two modes of the hardware simulation tool in this embodiment.

[0053] like Figure 4 As shown, the simulation tool 202 may include an interface 2022, an FPGA 2026, and a clock source 402. Interface 2022 and FPGA 2026 references... Figure 2 Detailed description. The clock source 402 can be used to generate a clock frequency. The clock frequency may include a first clock frequency 404 and a second clock frequency 406. In some embodiments, the clock source 402 may be a crystal oscillator. In other embodiments, the clock source 402 may be a clock signal received from an external device.

[0054] For ease of explanation, here, the first clock frequency 404 is the clock frequency used for prototype verification model, which has a higher frequency (e.g., 10MHz); the second clock frequency 406 is the clock frequency used for debugging model, which has a lower frequency (e.g., 1MHz).

[0055] In some embodiments, clock source 402 may generate a higher frequency (e.g., a first clock frequency 404) and use a frequency divider to generate a lower clock frequency (e.g., a second clock frequency 406) based on the higher frequency. In other embodiments, clock source 402 may generate a lower clock frequency (e.g., a second clock frequency 406) and use a frequency multiplier to generate a higher frequency (e.g., the first clock frequency 404). It is understood that there are many other methods for clock sources to generate clock frequencies, which will not be elaborated on here.

[0056] The simulation mode instruction 401 includes a first instruction 414 for putting the simulation tool 202 into prototype verification mode or a second instruction 416 for putting the simulation tool 202 into debug mode. The simulation mode instruction 401 can be used to instruct the simulation tool 202 to operate in prototype verification mode or debug mode.

[0057] In some embodiments, the simulation mode command 401 can be input by a user via the host 100. For example, the user can send a second command 416 (e.g., type " / debug") to the simulation tool 202 via the host 100 to enable the simulation tool 202 to operate in debug mode. When all debugging tasks in the second command 416 are completed, the user can further send a first command 414 to enable the simulation tool 202 to switch to prototype verification mode.

[0058] In some embodiments, the simulation mode instruction 401 may be generated by the simulation tool 202. For example, the description of the logic system design 210 may include trigger conditions and trigger instructions. When the trigger condition is true, the simulation tool 202 may generate the trigger instruction. In some embodiments, the trigger instruction may be a second instruction 416. For example, the trigger condition may be a Boolean expression including at least one input signal (e.g., a), such as "(a>0 && a<5)". When the trigger condition is true, i.e., when the value of "(a>0 && a<5)" is true, the simulation tool 202 may execute the trigger instruction, i.e., the second instruction 416, to run the debug mode.

[0059] In some embodiments, in response to receiving a first instruction 414, clock source 402 can generate a clock at a first clock frequency 404 and apply it to FPGA 2026; in response to receiving a second instruction 416, clock source 402 can generate a clock at a second clock frequency 406 and apply it to FPGA 2026. In other embodiments, clock source 402 can simultaneously generate a clock at the first clock frequency 404 and a clock at the second clock frequency 406, and selectively output a clock corresponding to the received simulation mode instruction 401.

[0060] In some embodiments, when the simulation tool 202 is in prototype verification mode, it can run at a first clock frequency 404 (i.e., the simulation of the logic system design is driven by the clock of the first clock frequency 404). Since the first clock frequency 404 is relatively high, the simulation tool 202 can perform the simulation of the logic system design at a higher frequency.

[0061] Then, the simulation tool 202 can receive the second instruction 416 and switch its clock to the second clock frequency 406 (i.e., operate at the second clock frequency 406). As mentioned above, the second instruction 416 can be generated by a trigger during the simulation of the logic system design, or it can be input by the user. At this time, the simulation tool 202 can enter debug mode and operate at the second clock frequency 406 (i.e., the simulation of the logic system design is driven by the clock of the second clock frequency 406). The simulation tool 202 can call the debug function to save the values ​​of key signals of the logic system design at a given moment for subsequent debugging. The debug function may include, but is not limited to: breakpoint debugging, full waveform display, log analysis, and variable tracking, etc. Since the second clock frequency 406 is low, it provides sufficient time for the simulation tool 202 to read the values ​​of key signals and implement various debug functions.

[0062] In some other embodiments, when the simulation tool 202 is in debug mode and receives the first instruction 414, the simulation tool 202 can switch back from the second clock frequency 406 to the first clock frequency 404, thereby resuming operation at the higher first clock frequency 404.

[0063] Therefore, the simulation tool 202 in this embodiment of the application runs at either the first clock frequency 404 or the second clock frequency 406 as needed, avoiding the problem of the dual-mode simulation tool 202 running at a lower frequency as is the case in the usual approach, and greatly improving the overall operating efficiency of the hardware simulation tool.

[0064] This application also provides a method for simulating logic system design on a hardware simulation tool.

[0065] Figure 5 A flowchart of a method 500 for simulating logic system design on a hardware emulation tool according to an embodiment of this application is shown, wherein method 500 can be performed by, for example... Figure 2 The simulation system 200 shown is executed. Method 500 may include the following steps.

[0066] In step 502, the simulation tool 202 receives a simulation mode command (e.g., Figure 4 Simulation mode instruction 401), the simulation mode instruction includes instructions for enabling the hardware simulation tool (e.g., Figure 3 The simulation tool 202) is in prototype verification mode (e.g., Figure 3 The first instruction of mode 302) (e.g., Figure 4 The first instruction 414) or used to put the hardware emulation tool into debug mode (e.g., Figure 3 The second instruction of mode 304 (e.g., Figure 4 The second instruction 416).

[0067] In some embodiments, the simulation mode command is received (e.g., Figure 4 The simulation mode instruction 401 further includes: receiving the simulation mode instruction from the user.

[0068] In other embodiments, receiving the simulation mode instruction further includes: responding to the hardware emulation tool (e.g., Figure 3 Simulation tool 202) is used to simulate the logic system design (e.g., Figure 2 When the design 210 meets the given conditions (e.g., the triggering condition "(a>0 && a<5)"), the simulation mode instruction is generated (e.g., Figure 4 The second instruction 416). Wherein, the logic system design (e.g., Figure 2 The design 210) includes at least one target signal (e.g., the aforementioned input signal a). Receiving the simulation mode instruction further includes: on the hardware simulation tool (e.g., Figure 2 The simulation tool 202) is used in the prototype verification mode (e.g., Figure 3 Mode 302) simulates the logic system design (e.g., Figure 2 Design 210); acquire the value of the at least one target signal (e.g., the input signal a mentioned above); determine whether the value of the at least one target signal (e.g., the input signal a mentioned above) satisfies the trigger condition (e.g., the trigger condition "(a>0 && a<5)" mentioned above); and in response to the value of the target signal (e.g., the input signal a mentioned above) satisfying the trigger condition, generate the second instruction (e.g., Figure 4 The second instruction 416).

[0069] In step 504, in response to receiving the first instruction (e.g., Figure 4 The first instruction 414) causes the hardware simulation tool to operate in the prototype verification mode (e.g., Figure 3 The prototype verification mode (e.g., mode 302) is used. Figure 3 In mode 302), the hardware emulation tool (e.g., Figure 2 Simulation tool 202) simulates the logic system design (e.g., Figure 2 The operating frequency of the design 210 is the first frequency (e.g., Figure 4The first clock frequency is 404.

[0070] The hardware emulation tool (e.g., Figure 3 The simulation tool 202) includes a clock source (e.g., Figure 4 The clock source 402), the clock source (e.g., Figure 4 The clock source 402) is used to generate a first clock at a first frequency (e.g., Figure 4 The first clock frequency 404) and the second clock frequency (e.g., Figure 4 The second clock frequency is 406). The method further includes: making the hardware emulation tool (e.g., Figure 3 The simulation tool 202) is used in the prototype verification mode (e.g., Figure 3 In mode 302) during operation, a first clock (e.g., at the first frequency) is used. Figure 4 The first clock frequency 404) drives the logic system design (e.g., Figure 2 Simulation of the design 210); and in order to enable the hardware simulation tool (e.g., Figure 3 The simulation tool 202) is in the debug mode (e.g., Figure 3 In mode 304) operation, a second clock (e.g., using the second frequency) is used. Figure 4 The second clock frequency 406) drives the logic system design (e.g., Figure 2 Simulation of the design 210).

[0071] In step 506, in response to receiving the second instruction (e.g., Figure 4 The second instruction 416) causes the hardware emulation tool (e.g., Figure 2 The simulation tool 202) is in the debug mode (e.g., Figure 3 The debug mode (e.g., mode 304) is used. Figure 3 In mode 304), the hardware emulation tool (e.g., Figure 2 Simulation tool 202) simulates the logic system design (e.g., Figure 2 The operating frequency of the design 210 is the second frequency (e.g., Figure 4 The second clock frequency 406), the first frequency (e.g., Figure 4 The first clock frequency 404) is higher than the second frequency (e.g., Figure 4 The second clock frequency is 406). In the debug mode (e.g., Figure 3 In mode 304), the hardware emulation tool (e.g., Figure 2 The simulation tool 202 is configured to save the logic system design (e.g., ...) during the simulation. Figure 2The design 210) is the main input for a given clock cycle.

[0072] This application also provides an electronic device. The electronic device may be... Figure 1 The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 400.

[0073] This application also provides a non-transitory computer-readable storage medium. This non-transitory computer-readable storage medium stores a set of instructions for a computer, which, when executed, causes the computer to perform method 400.

[0074] The foregoing has described some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0075] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of this application as described above, which are not provided in the details for the sake of brevity.

[0076] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0077] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for simulating logic system design on a hardware simulation tool, comprising: Receive simulation mode instructions, the simulation mode instructions including a first instruction for putting the hardware simulation tool into prototype verification mode or a second instruction for putting the hardware simulation tool into debug mode; In response to receiving the first instruction, the hardware simulation tool is made to run in the prototype verification mode; as well as In response to receiving the second instruction, the hardware emulation tool is made to run in the debug mode.

2. The method as described in claim 1, wherein, In the prototype verification mode, the hardware simulation tool simulates the operating frequency of the logic system design at a first frequency. In the debug mode, the hardware simulation tool simulates the operating frequency of the logic system design at a second frequency, where the first frequency is higher than the second frequency.

3. The method as described in claim 2, wherein, The hardware simulation tool includes a clock source, which is used to generate a first clock at the first frequency and a second clock at the second frequency. The method further includes: While the hardware simulation tool is running in the prototype verification mode, the simulation of the logic system design is driven by a first clock at the first frequency; and When the hardware simulation tool is run in the debug mode, the simulation of the logic system design is driven by a second clock at the second frequency.

4. The method of claim 1, wherein, In the debug mode, the hardware simulation tool is configured to save the main inputs of the logic system design at a given clock cycle during the simulation.

5. The method of claim 1, wherein, Receiving the simulation mode command further includes: Receive the simulation mode instructions from the user.

6. The method of claim 1, wherein, Receiving the simulation mode command further includes: The simulation mode instruction is generated in response to the hardware simulation tool meeting given conditions when simulating the logic system design.

7. The method of claim 6, wherein, The logic system design includes at least one target signal, and receiving the simulation mode command further includes: The logic system design is simulated on the hardware simulation tool using the prototype verification mode. Obtain the value of the at least one target signal; Determine whether the value of the at least one target signal satisfies the triggering condition; and The second instruction is generated in response to the value of the target signal satisfying the triggering condition.

8. An electronic device for simulating logic system design, comprising: Memory is used to store a set of instructions; as well as At least one processor is configured to execute the set of instructions to perform the method as described in any one of claims 1 to 7.

9. A non-transitory computer-readable storage medium storing a set of instructions for a computing device, the set of instructions being configured to cause the computing device to perform the method as described in any one of claims 1 to 7.

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