Data processing chip, data processing method and electronic equipment

Abstract

The invention provides a data processing chip, a data processing method and electronic equipment, and relates to the technical field of data processing.The data processing chip comprises a 3D-NAND storage module and a calculation module, and the 3D-NAND storage module and the calculation module are sealed in the same packaging body; the 3D-NAND storage module comprises a storage unit array controlled by a plurality of word lines and is used for storing weight parameters of a neural network model; the calculation module is configured to receive target data to be processed; obtaining a weight parameter of the neural network model from a 3D-NAND storage module; and performing matrix multiplication and addition operation on the weight data and the target data. By applying the data processing chip provided by the embodiment of the invention, the data calculation efficiency can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing chip, a data processing method, and an electronic device. Background Technology

[0002] In recent years, deep neural networks have made groundbreaking progress in fields such as computer vision and natural language processing, and their performance improvement is closely dependent on the continuous expansion of model size. These models contain massive amounts of weight parameters, and frequent and large-scale data exchanges are required between the processor and memory when performing inference or training tasks.

[0003] In traditional computing architectures, computing units (such as CPUs and GPUs) are separated from storage units (such as DRAM and SSDs). While this increases computing speed, the data transfer bandwidth grows slowly, limiting overall performance. When performing large-scale neural network calculations, a large number of parameters need to be repeatedly loaded from external memory into the computing unit cache. This process is time-consuming and energy-intensive, severely impacting computational efficiency. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a data processing chip, a data processing method, and an electronic device, thereby improving the efficiency of data computation. The specific solution is as follows:

[0005] A data processing chip, comprising:

[0006] A 3D-NAND storage module and a computing module, wherein the 3D-NAND storage module and the computing module are encapsulated in the same package.

[0007] The 3D-NAND storage module includes a storage cell array controlled by multiple word lines for storing weight parameters of a neural network model;

[0008] The computing module is configured as follows:

[0009] Receive the target data to be processed;

[0010] The multiple word lines in the 3D-NAND storage module are switched from a first voltage to a second voltage; a selected word line to be read is determined among the multiple word lines, and the selected word line is adjusted to a third voltage to read the data of the memory cell corresponding to the selected word line; after the data reading of the selected word line is completed, the voltage of the selected word line is restored to the second voltage, and the process of determining the selected word line to be read among the multiple word lines is repeated until the data reading of the multiple word lines is completed, thereby obtaining the weight parameters of the neural network model; wherein, the first voltage is less than the third voltage, and the third voltage is less than the second voltage;

[0011] Perform matrix multiplication and addition operations on the weighted data and the target data.

[0012] Optionally, in the aforementioned data processing chip, the computing module includes a parallel computing unit, which includes a first cache, a second cache, and a computing circuit. The computing circuit is configured to perform matrix multiplication and addition operations on the weight parameters cached in the first cache and the target data cached in the second cache.

[0013] Optionally, the computing circuit of the aforementioned data processing chip includes multiple multiply-accumulate circuit groups;

[0014] The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in column order of the matrix;

[0015] The second cache is configured to copy the target data into multiple copies and store them, wherein the number of copies of the target data corresponds to the number of weight parameter columns currently stored in the first cache;

[0016] The plurality of multiply-accumulate circuit groups are configured to perform multiply-accumulate operations in parallel on the column weight parameters stored in the first cache and the corresponding number of target data stored in the second cache.

[0017] Optionally, the computing circuit of the aforementioned data processing chip includes a multiplier array;

[0018] The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in row order of the matrix;

[0019] The second cache is configured to: reassemble the received target data into multiple data fragments according to the order of its data elements and store them;

[0020] The multiplier array is configured to perform an outer product calculation on the weight parameters stored in the first cache in the row direction and the current data segment stored in the second cache, and accumulate the calculation result into the result cache.

[0021] Optionally, the computing module of the aforementioned data processing chip includes a control circuit.

[0022] The control circuit is configured as follows:

[0023] The multiple word lines in the 3D-NAND storage module are switched from a first voltage to a second voltage, and the selected word line to be read is determined among the multiple word lines.

[0024] The selected word line is adjusted to the third voltage to read the data of the memory cell corresponding to the selected word line;

[0025] After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among the multiple word lines until the data reading of the multiple word lines is completed, thereby obtaining the weight parameters of the neural network model.

[0026] The aforementioned data processing chip may optionally also include a voltage control module;

[0027] The voltage control module is encapsulated in the same package as the 3D-NAND memory module and the computing module, and is used to provide voltage to the word lines of the 3D-NAND memory module.

[0028] The aforementioned data processing chip may optionally also include a sensor module;

[0029] The sensor module is used to collect physical environment signals, and transmit the collected physical environment signals as target data to be processed to the computing module.

[0030] Optionally, the 3D-NAND storage module may include multiple 3D-NAND chip particles, and / or the computing module may include multiple logic chip particles.

[0031] The multiple 3D-NAND chip particles and the computing module, or the 3D-NAND storage module and the multiple logic chip particles, are encapsulated in the same package.

[0032] A data processing method, comprising:

[0033] Receive the target data to be processed;

[0034] Switch the voltage of multiple word lines in the 3D-NAND storage module from a first voltage to a second voltage;

[0035] Among the multiple word lines, the selected word line to be read is determined, and the voltage of the selected word line is adjusted from the second voltage to the third voltage to read the data of the memory cell corresponding to the selected word line; wherein, the first voltage is less than the third voltage, and the third voltage is less than the second voltage;

[0036] After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among the multiple word lines until the data reading of the multiple word lines is completed, and the weight parameters of the neural network model are obtained.

[0037] Perform matrix multiplication and addition operations on the weighted data and the target data.

[0038] An electronic device comprising the aforementioned data processing chip.

[0039] This application provides a data processing chip, a data processing method, and an electronic device. The data processing chip includes a 3D-NAND storage module and a computing module, the 3D-NAND storage module and the computing module being encapsulated in the same package. The 3D-NAND storage module includes a memory cell array controlled by multiple word lines for storing weight parameters of a neural network model. The computing module is configured to: receive target data to be processed; switch the multiple word lines in the 3D-NAND storage module from a first voltage to a second voltage; determine a selected word line to be read from among the multiple word lines, adjust the selected word line to a third voltage to read data from the memory cell corresponding to the selected word line; after completing the data reading of the selected word line, restore the voltage of the selected word line to the second voltage, and return to the step of determining the selected word line to be read from among the multiple word lines, until the data reading of the multiple word lines is completed, obtaining the weight parameters of the neural network model; wherein the first voltage is less than the third voltage, and the third voltage is less than the second voltage; and perform matrix multiplication and addition operations on the weight data and the target data. The data processing chip provided in the embodiments of this application can improve the efficiency of data calculation. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This application provides a schematic diagram of the structure of a data processing chip.

[0042] Figure 2 A schematic diagram of another data processing chip provided in this application;

[0043] Figure 3 A schematic diagram of the structure of another data processing chip provided in this application;

[0044] Figure 4 A schematic diagram of another data processing chip provided in this application;

[0045] Figure 5 A data reading diagram provided for this application;

[0046] Figure 6 A schematic diagram of the architecture of a parallel computing unit provided in this application;

[0047] Figure 7 A schematic diagram of the architecture of another parallel computing unit provided in this application;

[0048] Figure 8 A flowchart of a data processing method provided in this application;

[0049] Figure 9 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] See Figure 1 This is a schematic diagram of the structure of a data processing chip provided in an embodiment of this application. The data processing chip includes:

[0053] The 3D and non-3D-NAND storage module 101 and the computing module 102 are packaged together in the same package.

[0054] The 3D-NAND storage module 101 includes an array of storage cells controlled by multiple word lines (WLs) for storing weight parameters of a neural network model. In this embodiment, the 3D-NAND storage module 101 is specifically a storage chip based on three-dimensional stacked flash memory technology. The 3D-NAND storage module includes an array of storage cells controlled by multiple word lines (WLs) for storing weight parameters of a neural network model. The weight parameters are coefficient values ​​that connect neurons in the neural network model and need to be determined through training.

[0055] Calculation module 102 is configured as follows:

[0056] Receive the target data to be processed;

[0057] The first voltage is switched to the second voltage across multiple word lines in the 3D-NAND memory module. The selected word line to be read is determined from among the multiple word lines, and its voltage is adjusted to the third voltage to read the data from the corresponding memory cell. After the data reading of the selected word line is completed, the voltage of the selected word line is restored to the second voltage, and the process of determining the selected word line to be read from among the multiple word lines is repeated until the data reading of all multiple word lines is completed, thus obtaining the weight parameters of the neural network model. The first voltage is less than the third voltage, and the third voltage is less than the second voltage.

[0058] Perform matrix multiplication and addition operations on the weighted data and the target data.

[0059] In this embodiment, the computing module 102 can be a logic chip with high parallel processing capabilities.

[0060] Optionally, the target data is the input data that needs to be used for reasoning or processing using a stored neural network model, such as feature vectors or matrices formed after preprocessing of raw data such as images and speech.

[0061] In this embodiment, the calculation module 102 needs to read weight parameters from the 3D-NAND storage module 101. Specifically, the calculation module 102 first switches multiple word lines in the 3D-NAND storage module 101 from a first voltage to a second voltage. Here, the first voltage is usually a lower voltage, such as a voltage close to 0V, representing an initial state; the second voltage is a higher voltage. Then, the calculation module 102 determines the word line to be read as the selected word line among the multiple word lines. The determination method can be based on a preset address order. Afterwards, the calculation module 102 adjusts the voltage of this selected word line from the second voltage to a third voltage. The third voltage, as a read voltage (medium voltage) between the first voltage (low voltage) and the second voltage (high voltage), is connected to the memory cell on the selected word line, so that the memory cell generates different conductivity states according to the stored data bits, thereby enabling the read circuit connected to the bit line to sense and read the data, while other unselected word lines remain in a conductive state due to the higher second voltage, without affecting the read path.

[0062] After completing the data reading of a row or group of storage units corresponding to the currently selected word line, the calculation module 102 restores the voltage of the selected word line to the second voltage, and reselects the next word line to be read from each word line, and adjusts its voltage to the third voltage for data reading. At the same time, the word line that has just been read continues to remain in the unselected but on state because its voltage has been restored to the second voltage.

[0063] In this embodiment, the calculation module 102 sequentially switches different word lines to the third voltage until all data needs to be read in a specific order on multiple word lines are completed. In this way, after raising all word line voltages to the second voltage at once, multiple rows of weight parameter data can be read continuously by alternately lowering (to the third voltage) and restoring (to the second voltage) the word line voltages, without having to repeat the process of switching all word line voltages from low to high and then from high to low before and after each reading of a single row of data. This continuous reading mode effectively reduces the number of global voltage switching operations and waiting time, thereby significantly improving the overall bandwidth and speed of weight parameter data flowing out of the 3D-NAND storage module.

[0064] The calculation module 102 performs matrix multiplication and addition operations on the weight parameters obtained through continuous reading and the previously received target data. Matrix multiplication and addition is a computational operation in the forward inference of a neural network. The calculation module 102 integrates highly parallel computing units, such as a multiply-accumulate array composed of a large number of scalar multipliers and adders, to efficiently complete the multiplication and accumulation operations between the weight matrix and the input data vector or matrix.

[0065] It is easy to understand that by encapsulating a high-capacity 3D-NAND storage module and a high-performance computing module in the same package and employing the aforementioned continuous read method, the data processing chip provided in this application embodiment achieves tight coupling between storage and computing. This effectively reduces the data transport overhead and access latency caused by the separation of storage chips (such as DRAM) and computing chips (such as CPU / GPU) in traditional computing architectures, making it suitable for efficiently executing inference tasks of large-scale neural network models on the terminal device side.

[0066] In one embodiment provided in this application, based on the above scheme, optionally, the computing module includes a parallel computing unit, the parallel computing unit includes a first cache, a second cache and a computing circuit, and the computing circuit is configured to perform matrix multiplication and addition operations on the weight parameters cached in the first cache and the target data cached in the second cache.

[0067] For example, the first cache can be a high-speed static random access memory (SRAM) that can temporarily store the weight parameters of the neural network model read continuously from the 3D-NAND storage module 101. Since the amount of weight parameters is usually large and the reading from the 3D-NAND is continuous streaming, the first cache provides a high-speed buffer area that can organize the outgoing weight parameters in the order and format required for computation. For example, a two-dimensional weight matrix can be mapped and stored as a one-dimensional continuous data sequence in column or row order so that subsequent computation circuits can access it efficiently and systematically.

[0068] The second cache can also be a type of SRAM. It can be used to cache target data to be processed. After being input into the calculation module 102, the target data does not directly participate in the calculation; instead, it may require certain preprocessing and buffering depending on the calculation mode. For example, in one implementation, a target data set may need to be copied multiple times or reorganized. This processed intermediate data is temporarily stored in the second cache, waiting to be paired with the weight parameters in the first cache for calculation.

[0069] It is easy to understand that the first cache and the second cache can be two separate storage entities physically, or they can be logically divided into different address spaces of the same storage entity. This application does not limit this.

[0070] In addition, the computing circuit is the hardware circuit that performs the actual arithmetic operations. It can simultaneously read the weight parameters cached in the first cache and the target data cached in the second cache, and perform matrix multiplication and addition operations on these two sets of data. Matrix multiplication and addition operations can specifically be a combination of a series of multiplication and addition operations.

[0071] In one alternative implementation, the computational circuit can include a large number of parallel multiply-accumulate (MAC) units, forming a multiply-accumulate circuit group or array. These multiply-accumulate units can jointly perform multiplication operations between the corresponding parts of the weight parameters and the corresponding parts of the target data, and accumulate their respective product results. Through this parallel approach, the computational circuit can quickly convert matrix or vector data stored in two caches into the result of matrix multiplication and addition operations, thereby greatly accelerating the computation process of the neural network layer.

[0072] It should be noted that the specific computation mode executed by the computing circuit can be closely coordinated with the data organization in the first and second caches. For example, when the first cache stores the weight matrix column-majorly and the second cache copies the input vector multiple times, the computing circuit may be configured to execute a parallel inner product computation mode. Conversely, if the data is organized in other ways, the computing circuit may correspondingly execute other efficient computation modes such as outer products. This coordinated design of cache data layout and computing circuit mode can effectively improve overall computational efficiency.

[0073] In summary, by setting up a parallel computing unit that includes a dedicated first cache, a second cache, and parallel computing circuits, this embodiment enables the computing module 102 to not only acquire weight parameters at high speed, but also to complete the calculation between the weight parameters and the target data with extremely high hardware utilization and parallelism. Thus, in a storage-computing integrated architecture, efficient processing from storage to computation is achieved.

[0074] In one embodiment provided in this application, based on the above-described scheme, optionally, the calculation circuit includes multiple multiply-accumulate circuit groups;

[0075] The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in column order of the matrix;

[0076] The second cache is configured to copy the target data into multiple copies and store them, wherein the number of copies of the target data corresponds to the number of weight parameter columns currently stored in the first cache;

[0077] Multiple multiply-accumulate circuit groups are configured to perform multiply-accumulate operations in parallel on the column weight parameters stored in the first cache and the corresponding number of target data stored in the second cache.

[0078] In this process, all data elements of the first column of the weight parameters are first stored sequentially in the contiguous address space of the first cache, followed by all elements of the second column, and so on, until the last column. In this way, the two-dimensional matrix structure is physically mapped to a long one-dimensional data sequence with clear column boundaries. Furthermore, the second cache is configured to copy the received target data multiple times and store these copies. Here, the target data is an input vector or a row of an input matrix. The number of copies of the target data corresponds to the number of columns of the weight parameters currently stored in the first cache. For example, if the weight matrix to be calculated has K columns, then the second cache stores K identical copies of the input data. This copying operation is for data alignment, ensuring that each column of weight parameters has a complete copy of the input data to participate in the calculation simultaneously.

[0079] For example, each multiply-accumulate circuit group contains multiple multiply-accumulate units connected in parallel. These multiply-accumulate circuit groups operate on the prepared data in the first and second caches in parallel. Specifically, each column of weight parameters stored in the first cache and the corresponding copy of the target data stored in the second cache can be read synchronously. The first column of weights corresponds to the first input copy, the second column of weights corresponds to the second input copy, and so on.

[0080] Each multiply-accumulate circuit group is responsible for processing the multiply-accumulate operation between a column of weight parameters and the corresponding complete input data. This operation can be understood as calculating the product of all weight values ​​in that column with each value of the input vector, and summing these product results to obtain a partial sum or an element of the final output value. Because multiple multiply-accumulate circuit groups work in parallel, they can process multiple columns of weights and multiple sets of input data simultaneously, thus producing K partial results in one computation cycle. This greatly improves the computational throughput and achieves a high degree of data-level parallelism.

[0081] In one embodiment provided in this application, based on the above-described scheme, optionally, the computing circuit includes a multiplier array;

[0082] The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in row order of the matrix;

[0083] The second cache is configured to reassemble the received target data into multiple data fragments according to the order of its data elements and store them.

[0084] The multiplier array is configured to perform an outer product calculation on the weight parameters stored in the first cache in the row direction and the current data segment stored in the second cache, and accumulate the calculation result into the result cache.

[0085] In this embodiment, the first cache stores the weight parameters obtained continuously from the 3D-NAND storage module in row order of its original two-dimensional weight matrix. This means that all data elements in the first row of the weight matrix are stored consecutively in the first cache, followed by all elements in the second row, and so on. Furthermore, the configuration of the second cache complements the storage method of the first cache. Specifically, the second cache is configured to reassemble the received target data. Here, the target data typically contains multiple input vectors to be processed. The reassembly method involves extracting the first element of each input vector to form a first data segment, extracting the second element to form a second data segment, and so on, according to the order of the input vector data elements. In other words, the data originally arranged in vector order is transformed into multiple new data segments arranged in element position order. These reassembled data segments are stored sequentially in the second cache, and each segment will be called in different computation cycles.

[0086] For example, the multiplier array consists of multiple (e.g., M rows × N columns) multiplier circuits arranged in a two-dimensional grid. This array is configured to perform outer product calculations. Specifically, in one computation stage, the multiplier array synchronously reads an entire row of weight parameters (assuming it contains M data points) stored row-by-row in a first cache, and a data segment currently stored in a second cache (assuming it contains N recombined input elements). Subsequently, each multiplier in the array calculates the product of a weight parameter and an input element, i.e., performs the outer product operation, thereby generating M × N partial product results at once. These partial product results are accumulated in a preset result cache.

[0087] It's easy to understand that when the current computation produces a result, at the start of the next computation, the multiplier array reads the next row of data from the weight matrix and the next data segment from the second buffer, performs a new round of outer product calculation, and accumulates the resulting batch of partial product results into the corresponding address in the result buffer, summing it with the result from the previous round. This process continues until all rows of the weight matrix and all batches of data segments have been processed. Ultimately, what accumulates in the result buffer is the complete matrix multiplication and addition result of the weight matrix and multiple input vectors.

[0088] In one embodiment provided in this application, based on the above-described scheme, optionally, the calculation module includes a control circuit;

[0089] The control circuit is configured as follows:

[0090] The first voltage is switched to the second voltage for multiple word lines in the 3D-NAND storage module, and the selected word line to be read is determined among the multiple word lines.

[0091] Adjust the selected word line to the third voltage to read the data of the memory cell corresponding to the selected word line;

[0092] After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among multiple word lines until the data reading of multiple word lines is completed, and the weight parameters of the neural network model are obtained.

[0093] In one embodiment provided in this application, based on the above-described solution, optionally, a voltage control module is also included;

[0094] The voltage control module is packaged together with the 3D-NAND memory module and the computing module in the same package and is used to provide voltage to the word lines of the 3D-NAND memory module.

[0095] In this embodiment, the voltage control module can be a separate power management chip. See also Figure 2 The voltage control module is integrated into the same package as the 3D-NAND memory module and computing module using a preset packaging method, forming a package containing three or more chips. This co-package design greatly shortens the power path between the voltage control module and the 3D-NAND memory module.

[0096] A voltage control module can be used to provide the required operating voltages to the word lines of a 3D-NAND memory module. Examples include a first voltage, a second voltage, and a third voltage.

[0097] In one embodiment provided in this application, based on the above-described solution, optionally, a sensor module may also be included;

[0098] The sensor module is used to collect physical environment signals, and transmits the collected physical environment signals as target data to be processed to the computing module.

[0099] The sensor module can be a separate sensor chip that is integrated into the same package as the 3D-NAND storage module and the computing module through a preset packaging method.

[0100] For example, physical environment signals may include, but are not limited to, optical image signals, sound vibration signals, temperature change signals, pressure or deformation signals, inertial motion signals, etc.

[0101] In a specific application scenario, suppose the sensor module is a low-power image sensor. When this data processing chip is deployed in a smart vision terminal, the image sensor continuously collects ambient light and generates image frames. These image frame data are sent to the computing module in real time as target data without leaving the chip package. At the same time, the computing module quickly reads pre-stored neural network weight parameters from the encapsulated 3D-NAND storage module, such as the parameters of an image recognition model, and performs high-speed matrix multiplication and addition operations on the incoming image frame data, ultimately directly outputting the recognition result, such as object category, facial features, etc.

[0102] In one embodiment provided in this application, based on the above solution, optionally, the 3D-NAND storage module includes multiple 3D-NAND chip particles, and / or the computing module includes multiple logic chip particles;

[0103] Multiple 3D-NAND chips and computing modules, or 3D-NAND storage modules and multiple logic chips, are packaged together in the same package.

[0104] The data processing chip provided in this application adopts a memory-computing architecture, which can tightly integrate the storage module and the computing module. Specifically, as shown in the example... Figure 3 As shown, the data processing chip includes at least one 3D-NAND memory chip and at least one logic chip. Both are packaged together in the same package via a high-bandwidth interconnect, enabling a high-speed data path between storage and computation. The logic chip integrates multiple functional units, primarily including:

[0105] Control circuitry is used to control the read and write operations of the encapsulated 3D-NAND memory chips.

[0106] The communication unit is used for high-speed data communication with a host or other chip outside the package.

[0107] Parallel computing units are used to perform highly parallel matrix and vector operations.

[0108] To accommodate different capacity and functional requirements, in one optional embodiment, a 3D-NAND storage chip can be packaged with multiple logic chip chips to improve computing power; or, in addition to storage and logic chips, it can also be packaged with functional chips (such as high-voltage control chips, sensor chips, etc.).

[0109] See Figure 4 In another alternative embodiment, multiple 3D-NAND memory chips can be packaged with a single logic chip to provide a larger model parameter storage capacity; similarly, they can also be packaged together with the aforementioned functional chips.

[0110] SeeFigure 5 This is a schematic diagram of data reading of a 3D-NAND module provided in an embodiment of this application. The parameter reading process is as follows:

[0111] a) Initialization: Switch the voltage of all word lines (WL) in the 3D-NAND memory array from the first voltage (low voltage) to the second voltage (high voltage).

[0112] b) First line read: When all WL are in the second voltage state, the selected word line to be read is determined, and the voltage of the selected word line is adjusted to the third voltage (medium voltage). At this time, the memory cell connected to the selected word line is selected, and its data is read through the bit line (BL).

[0113] c) Continuous switching read: After completing the data reading of the currently selected word line, you can choose not to pull all WL voltages down, but instead restore the voltage of the currently selected word line to the second voltage, and at the same time adjust the voltage of the next word line to be read to the third voltage to read a new line of data.

[0114] d) Loop and End: Repeat step c, continuously switching different word lines to the third voltage in a preset order for reading, until all or part of the target word lines have been read. Finally, restore the voltage of all word lines to the first voltage.

[0115] This application provides a control circuit for implementing the above-described continuous read method. This circuit can be integrated into the logic chip and is used to automatically control the word line voltages to switch in a selected sequence, thereby efficiently and automatically completing the continuous data stream output.

[0116] In some embodiments, to match the high-speed continuous data stream and realize in-memory computation, this application designs the encapsulated logic chip as a computing module with high parallel computing capabilities. This module has the following functions: 1. High-speed reception of continuous data streams from 3D-NAND chips; 2. High-speed execution of matrix and vector calculations.

[0117] In some embodiments, the parallel computing unit includes a parallel architecture based on an inner product computation pattern, specifically as follows: Figure 6As shown, the two-dimensional weight matrix continuously read from the 3D-NAND chips by the row computing unit is mapped sequentially along the column direction and stored in the first cache within the computing module, i.e., the data is concatenated column by column to form a one-dimensional data sequence. One or more input vectors (target data) input through the high-speed interface are copied K times and stored in the second cache. A computing array composed of multiple sets of vector multiply-accumulate circuits is configured to perform multiply-accumulate operations in parallel on the weight data of each column in the first cache and the corresponding number of input vector data in the second cache. Each set of circuits can contain multiple (e.g., 8, 16, 32, ..., 256) multiply-accumulaters supporting precision such as INT8, FP8, INT16, FP16, etc. The calculation results of each set of multiply-accumulate circuits are summed and accumulated to finally generate the complete result of multiplying and adding the weight matrix and the input vector.

[0118] In some embodiments, the data in the second cache may not need to be physically copied K times. Instead, it can be accessed by K sets of computing circuits simultaneously through time-sharing or broadcasting mechanisms to save cache overhead.

[0119] In some embodiments, the parallel computing unit includes a parallel architecture based on an outer product computation pattern, specifically as follows: Figure 7 As shown, the parallel computing unit can map the weight matrix sequentially along the row direction and store it in the first cache, i.e., concatenating the data row by row. Elements of multiple input vectors are reorganized. Specifically, the first element of all input vectors forms the first new vector segment, the second element forms the second new vector segment, and so on. These vector segments are cached sequentially in the second cache. The computing module contains a multiplier array. In one computing step, this array performs an outer product calculation on a row of weight data in the first cache and a current vector segment in the second cache, generating a partial result matrix and accumulating it in the result cache. In the next computing step, the next row of weight data and the next input vector segment are read, a new outer product calculation is performed, and the result is accumulated in the corresponding position of the result cache. This process is iterated until all rows and segments are processed, and the final calculation result is obtained in the result cache.

[0120] In some embodiments, the data arrangement directions of the first cache and the second cache are orthogonal to each other. The size of the multiplier array (n*m multipliers) and the cache size (n bytes or 2n bytes for input, m bytes or 2m bytes for weights) can be configured according to the data precision (INT8 / FP8 or INT16 / FP16).

[0121] By applying the method provided in this application, the voltage switching latency of 3D-NAND memory chips during continuous access is significantly reduced through a continuous read method, thereby significantly improving the speed of model parameter retrieval. By providing a highly parallel computing architecture tightly coupled with memory, complete matrix calculations can be performed in a single pipeline without distributing computational tasks, greatly improving computational efficiency. Furthermore, by encapsulating high-capacity 3D-NAND memory with high-performance computing units and optimizing the data path, the parameters of large-scale neural network models do not need to be frequently and slowly transferred between memory chips and computing chips, achieving efficient and low-power in-memory computation.

[0122] See Figure 8 This is a flowchart of a data processing method provided in this application. This method can be applied to the computing module in the aforementioned data processing chip. The method specifically includes:

[0123] S801: Receive the target data to be processed.

[0124] S802: Switches the voltage of multiple word lines in the 3D-NAND memory module from a first voltage to a second voltage.

[0125] S803: Determine the selected word line to be read among multiple word lines, and adjust the voltage of the selected word line from the second voltage to the third voltage to read the data of the memory cell corresponding to the selected word line; wherein, the first voltage is less than the third voltage, and the third voltage is less than the second voltage.

[0126] S804: After completing the data reading of the selected word line, restore the voltage of the selected word line to the second voltage, and return to execute the step of determining the selected word line to be read among multiple word lines until the data reading of multiple word lines is completed, and obtain the weight parameters of the neural network model.

[0127] S805: Perform matrix multiplication and addition operations on the weighted data and the target data.

[0128] See Figure 9 This application also provides an electronic device including the data processing chip described above.

[0129] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0130] It is understood that the above notification and user authorization process is merely illustrative and does not constitute a limitation on the implementation of the present invention. Other methods that comply with relevant laws and regulations may also be applied to the implementation of the present invention.

[0131] It is understood that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and related provisions.

[0132] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0133] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0134] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0135] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0136] The solution provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data processing chip, characterized in that, include: A 3D-NAND storage module and a computing module, wherein the 3D-NAND storage module and the computing module are encapsulated in the same package. The 3D-NAND storage module includes a storage cell array controlled by multiple word lines for storing weight parameters of a neural network model; The computing module is configured as follows: Receive the target data to be processed; The multiple word lines in the 3D-NAND storage module are switched from a first voltage to a second voltage; among the multiple word lines, the selected word line to be read is determined, and the selected word line is adjusted to a third voltage to read the data of the storage cell corresponding to the selected word line; After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among the multiple word lines until the data reading of the multiple word lines is completed, and the weight parameters of the neural network model are obtained; wherein, the first voltage is less than the third voltage, and the third voltage is less than the second voltage; Perform matrix multiplication and addition operations on the weighted data and the target data.

2. The data processing chip according to claim 1, characterized in that, The computing module includes a parallel computing unit; The parallel computing unit includes a first cache, a second cache, and a computing circuit. The computing circuit is configured to perform matrix multiplication and addition operations on the weight parameters cached in the first cache and the target data cached in the second cache.

3. The data processing chip according to claim 2, characterized in that, The computing circuit includes multiple groups of multiply-accumulate circuits; The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in column order of the matrix; The second cache is configured to copy the target data into multiple copies and store them, wherein the number of copies of the target data corresponds to the number of weight parameter columns currently stored in the first cache; The plurality of multiply-accumulate circuit groups are configured to perform multiply-accumulate operations in parallel on the column weight parameters stored in the first cache and the corresponding number of target data stored in the second cache.

4. The data processing chip according to claim 2, characterized in that, The computing circuit includes a multiplier array; The first cache is configured to store the weight parameters obtained from the 3D-NAND storage module in row order of the matrix; The second cache is configured to: reassemble the received target data into multiple data fragments according to the order of its data elements and store them; The multiplier array is configured to perform an outer product calculation on the weight parameters stored in the first cache in the row direction and the current data segment stored in the second cache, and accumulate the calculation result into the result cache.

5. The data processing chip according to claim 1, characterized in that, The computing module includes a control circuit; The control circuit is configured as follows: The multiple word lines in the 3D-NAND storage module are switched from a first voltage to a second voltage, and the selected word line to be read is determined among the multiple word lines. The selected word line is adjusted to the third voltage to read the data of the memory cell corresponding to the selected word line; After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among the multiple word lines until the data reading of the multiple word lines is completed, thereby obtaining the weight parameters of the neural network model.

6. The data processing chip according to claim 1, characterized in that, Also includes: Voltage control module; The voltage control module is encapsulated in the same package as the 3D-NAND memory module and the computing module, and is used to provide voltage to the word lines of the 3D-NAND memory module.

7. The data processing chip according to claim 1, characterized in that, Also includes: Sensor module; The sensor module is used to collect physical environment signals, and transmit the collected physical environment signals as target data to be processed to the computing module.

8. The data processing chip according to claim 1, characterized in that, The 3D-NAND storage module includes multiple 3D-NAND chip particles, and / or the computing module includes multiple logic chip particles; The multiple 3D-NAND chip particles and the computing module, or the 3D-NAND storage module and the multiple logic chip particles, are encapsulated in the same package.

9. A data processing method, characterized in that, include: Receive the target data to be processed; Switch the voltage of multiple word lines in the 3D-NAND storage module from a first voltage to a second voltage; Among the multiple word lines, the selected word line to be read is determined, and the voltage of the selected word line is adjusted from the second voltage to the third voltage to read the data of the memory cell corresponding to the selected word line; wherein, the first voltage is less than the third voltage, and the third voltage is less than the second voltage; After completing the data reading of the selected word line, the voltage of the selected word line is restored to the second voltage, and the process returns to the step of determining the selected word line to be read among the multiple word lines until the data reading of the multiple word lines is completed, and the weight parameters of the neural network model are obtained. Perform matrix multiplication and addition operations on the weighted data and the target data.

10. An electronic device, characterized in that, Includes the data processing chip according to any one of claims 1 to 8.

Images