Low capacity balanced bridge base frequency disturbance rejection and current limiting control method under unbalanced loads
By acquiring and filtering the midpoint voltage, and combining it with voltage loop and current loop PI controllers to generate PWM signals, the problem of midpoint voltage fluctuation and limiting while taking into account bus voltage in low-capacity balanced bridges under unbalanced loads is solved, thus achieving more stable midpoint voltage control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RENAC POWER TECH CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-05-29
AI Technical Summary
Under unbalanced load conditions, the control capability of a low-capacity balancing bridge is limited, resulting in large fundamental frequency fluctuations in the neutral point voltage. This affects the neutral point voltage balance control effect and system operation stability. Furthermore, the fixed limiting method is difficult to accommodate different bus voltage conditions.
The neutral point voltage and the total DC bus voltage are calculated by collecting the balance bridge current, positive bus voltage, and negative bus voltage. The fundamental frequency notch filter is then applied. A voltage loop PI controller is used to generate a current reference value. The current reference value is then limited within a range based on the limit value calculated according to the total DC bus voltage. Finally, a PWM signal is generated by the current loop PI controller to drive the balance bridge switching transistor.
It improves the control capability of low-capacity balanced bridges under unbalanced loads, enhances the neutral point voltage balance control effect, reduces the impact of base frequency fluctuations on the control link, and maintains safe and reliable regulation capability under different bus voltage conditions.
Smart Images
Figure CN121863891B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronic control technology, and in particular to a method for suppressing fundamental frequency disturbances and limiting current under unbalanced loads in a low-capacity balanced bridge. Background Technology
[0002] In off-grid operation or under complex load conditions, the DC-side midpoint voltage of multilevel converters is easily affected by factors such as load asymmetry, power factor changes, and fluctuations in operating conditions, leading to imbalance. To maintain midpoint voltage balance, existing technologies typically employ a balancing bridge. By adjusting the duty cycle of the balancing bridge's switching transistors, current is injected into or extracted from the midpoint of the bus capacitor, thereby maintaining midpoint voltage balance. Considering factors such as cost and losses, low-capacity balancing bridges, also known as low-power balancing bridges, are often used in practical applications. This means that the switching transistors, inductors, and current sensors of the balancing bridge use lower power ratings. Due to the limited control capability of low-capacity balancing bridges, they are mainly used to suppress unstable factors such as DC bias and low-frequency fluctuations in the midpoint voltage, without needing to completely eliminate the fundamental frequency component and third harmonic component.
[0003] However, under unbalanced load conditions, the neutral point voltage often exhibits significant fundamental frequency fluctuations. Due to the limited control capability of low-capacity balancing bridges, these large fundamental frequency fluctuations consume the bridge's regulation capacity, reducing its ability to suppress DC bias and low-frequency fluctuations in the neutral point voltage. This negatively impacts the neutral point voltage balance control effect and system stability. Furthermore, existing technologies often employ fixed current reference value limiting methods. However, the operating state of the balancing bridge varies under different bus voltage conditions, making it difficult to balance the neutral point voltage balance control requirements with the bridge's operational safety. Therefore, existing low-capacity balancing bridge control methods still suffer from the problem of the neutral point voltage balance control effect being significantly affected by fundamental frequency fluctuations under unbalanced load conditions, and the current reference value limiting method failing to accommodate different bus voltage conditions. Summary of the Invention
[0004] This application provides a method for suppressing fundamental frequency disturbances and limiting current in a low-capacity balanced bridge under unbalanced loads, which can improve the control capability of the low-capacity balanced bridge under unbalanced loads and meet the control requirements of different bus voltages. This application provides the following technical solution:
[0005] In a first aspect, this application provides a method for suppressing fundamental frequency disturbances and controlling current limiting in a low-capacity balanced bridge under unbalanced load, the method comprising:
[0006] Collect the balance bridge current, positive bus voltage, and negative bus voltage, and calculate the midpoint voltage and the total DC bus voltage based on the positive bus voltage and the negative bus voltage;
[0007] The midpoint voltage is subjected to fundamental frequency notch filtering, and the filtered midpoint voltage is output.
[0008] The filtered midpoint voltage is input to the voltage loop PI controller and the current reference value is output.
[0009] The current reference value is limited based on the total DC bus voltage, and the current reference value is limited by the limit value to obtain the limited current reference value.
[0010] The difference between the current reference value after the limit and the balance bridge current is input into the current loop PI controller. The balance bridge duty cycle is calculated based on the output of the current loop PI controller, the negative bus voltage, and the total DC bus voltage. Then, a PWM signal is generated based on the duty cycle to drive the balance bridge switching transistor.
[0011] In one specific implementation, the topology of the low-capacity balanced bridge is as follows:
[0012] An upper bridge arm switch is connected in series between the positive and negative busbars. and lower bridge arm switch tube The upper bridge arm switch tube With the lower bridge arm switch tube The connecting nodes form the midpoint of the balance bridge arm;
[0013] The DC-side bus includes an upper bus capacitor and a lower bus capacitor connected in series, wherein the voltage of the upper bus capacitor is the positive bus voltage. The voltage of the lower bus capacitor is the negative bus voltage. The connection point between the two forms the midpoint of the bus capacitor;
[0014] The midpoint of the balanced bridge arm and the midpoint of the bus capacitor are connected by an inductor. Connection, the inductor The current flowing through it is the bridge current. ;
[0015] The voltage loop PI controller takes the midpoint voltage as input and outputs a reference value for the balanced bridge current, while the current loop PI controller uses the reference value for the balanced bridge current and the balanced bridge current... The difference is taken as input, and the upper bridge arm switch is controlled according to the adjustment result. With the lower bridge arm switch tube The duty cycle of the balance bridge current is adjusted to ensure that the current in the balance bridge is... Track the current reference value.
[0016] In one specific implementation, the step of acquiring the balanced bridge current, positive bus voltage, and negative bus voltage, and calculating the midpoint voltage and the total DC bus voltage based on the positive bus voltage and the negative bus voltage includes:
[0017] Collect balanced bridge current Positive bus voltage and negative bus voltage And based on the sampled positive bus voltage and negative bus voltage Calculate the midpoint voltage and DC bus total voltage Midpoint voltage and DC bus total voltage The calculation formula is as follows:
[0018] .
[0019] In one specific implementation, the step of performing fundamental frequency notch filtering on the midpoint voltage and outputting the filtered midpoint voltage includes:
[0020] Midpoint voltage The input is processed by a notch filter, and the midpoint voltage after filtering is... It can be represented as follows:
[0021] ;
[0022] in, The transfer function of the notch filter is expressed as follows:
[0023] ;
[0024] in, For the Laplace operator; Let be the center angular frequency of the notch filter, satisfying ; The fundamental frequency; is the damping coefficient of the notch filter.
[0025] In one specific implementation, the step of inputting the filtered midpoint voltage into the voltage loop PI controller and outputting a current reference value includes:
[0026] The current reference value The calculation formula is as follows:
[0027] ;
[0028] in, This is the filtered midpoint voltage. and These are the proportional and integral coefficients of the voltage loop PI controller, respectively. For the Laplace operator.
[0029] In one specific implementation, the step of calculating a limiting value for the current reference value based on the total DC bus voltage, and using the limiting value to perform interval limiting on the current reference value to obtain a limited current reference value, includes:
[0030] Based on the total voltage of the DC bus Calculate the limit value of the current reference value The calculation formula is as follows:
[0031] ;
[0032] in, and It is an adjustable coefficient, and satisfies , ;
[0033] After obtaining the amplitude limit value Then, the current reference value A limiting process is performed to obtain the current reference value after limiting. The relationship is as follows:
[0034] .
[0035] In one specific implementation, the step of inputting the difference between the limited current reference value and the balanced bridge current into the current loop PI controller, calculating the balanced bridge duty cycle based on the output of the current loop PI controller, the negative bus voltage, and the total DC bus voltage, and then generating a PWM signal to drive the balanced bridge switching transistor based on the duty cycle includes:
[0036] The obtained current reference value after limiting With the balance bridge current By comparison, the current deviation is obtained. The current deviation is then input into the current loop PI controller for adjustment.
[0037] The current loop PI controller generates a current adjustment amount based on the current deviation and correlates it with the negative bus voltage. and the total voltage of the DC bus Jointly participate in duty cycle calculation;
[0038] Duty cycle The calculation formula is as follows:
[0039] ;
[0040] in, and These are the proportional and integral coefficients of the current loop PI controller, respectively. For the Laplace operator;
[0041] Get the duty cycle Then, regarding the duty cycle PWM modulation is performed to generate a drive signal, and the generated PWM signal is used to drive the upper arm switching transistor of the balanced bridge. Simultaneously, it generates a complementary PWM signal to drive the lower bridge arm switching transistor. .
[0042] Secondly, this application provides a low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control system under unbalanced load, which adopts the following technical solution:
[0043] A low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control system under unbalanced load includes:
[0044] The voltage calculation module is used to collect the balance bridge current, positive bus voltage and negative bus voltage, and calculate the midpoint voltage and the total DC bus voltage based on the positive bus voltage and the negative bus voltage;
[0045] The filtering module is used to perform fundamental frequency notch filtering on the midpoint voltage and output the filtered midpoint voltage.
[0046] The reference value calculation module is used to input the filtered midpoint voltage into the voltage loop PI controller and output a current reference value.
[0047] An interval limiting module is used to calculate the limiting value of the current reference value based on the total voltage of the DC bus, and to use the limiting value to perform interval limiting on the current reference value to obtain the limited current reference value.
[0048] The switching control module is used to input the difference between the current reference value after the limit and the balance bridge current into the current loop PI controller, and calculate the balance bridge duty cycle based on the output of the current loop PI controller, the negative bus voltage and the total DC bus voltage, and then generate a PWM signal to drive the balance bridge switching transistor based on the duty cycle.
[0049] Thirdly, this application provides an electronic device, the device including a processor and a memory; the memory stores a program, the program being loaded and executed by the processor to implement a method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in the first aspect.
[0050] Fourthly, this application provides a computer-readable storage medium storing a program that, when executed by a processor, is used to implement a method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in the first aspect.
[0051] The control of the balanced bridge current is achieved by constructing a control link that combines midpoint voltage processing and current closed-loop regulation. This method first acquires the balanced bridge current, positive bus voltage, and negative bus voltage, and calculates the midpoint voltage and the total DC bus voltage based on these voltages. Then, the midpoint voltage is subjected to fundamental frequency notch filtering, and the filtered midpoint voltage is input to a voltage loop PI controller to generate a current reference value, establishing a correspondence between the current reference value and the midpoint voltage change state. Subsequently, a limit value for the current reference value is calculated based on the total DC bus voltage, and this limit value is used to perform interval limiting on the current reference value to obtain a limited current reference value. Finally, the difference between the limited current reference value and the balanced bridge current is input to the current loop PI controller, and the balanced bridge duty cycle is calculated in conjunction with the negative bus voltage and the total DC bus voltage. The generated PWM signal drives the balanced bridge switching transistors. This forms a complete control link from midpoint voltage processing, current reference value generation, current limiting to current closed-loop control and PWM drive, enabling the output current of the balanced bridge to be adjusted according to changes in the midpoint voltage. At the same time, when the DC bus voltage changes, the current reference value is limited by limiting constraints, so that the balanced bridge current can be adjusted within a controllable range and used to change the voltage distribution relationship between the two bus capacitors. This can improve the problem that the midpoint voltage balance control effect under unbalanced load conditions is greatly affected by fundamental frequency fluctuations and that the current reference value limiting is difficult to take into account different bus voltage conditions.
[0052] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0053] Figure 1 This is a schematic diagram of the topology of the low-capacity balanced bridge in the embodiments of this application.
[0054] Figure 2 This is a flowchart illustrating the method for suppressing and limiting current of low-capacity balanced bridge fundamental frequency disturbance under unbalanced load in the embodiments of this application.
[0055] Figure 3 This is a control block diagram of the low-capacity balanced bridge in the embodiments of this application.
[0056] Figure 4 This is a system topology diagram of a low-capacity balanced bridge applied to a diode-clamped three-level converter in an embodiment of this application.
[0057] Figure 5 This is an experimental waveform diagram of the embodiment of this application without the addition of a 50Hz notch filter.
[0058] Figure 6 This is an experimental waveform diagram after adding a 50Hz notch filter in the embodiment of this application.
[0059] Figure 7 This is an experimental waveform diagram when a fixed current reference value is used for amplitude limiting in the embodiments of this application.
[0060] Figure 8 This is an experimental waveform diagram of the current reference value being limited according to the bus voltage in the embodiments of this application.
[0061] Figure 9 This is a block diagram of the low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control system under unbalanced load in the embodiments of this application.
[0062] Figure 10 This is a block diagram of an electronic device for suppressing and limiting current of low-capacity balanced bridge fundamental frequency disturbance under unbalanced load in an embodiment of this application. Detailed Implementation
[0063] The specific embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this application, but are not intended to limit the scope of this application.
[0064] Optionally, this application uses the low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control method under unbalanced load provided in various embodiments as an example for description in electronic devices. The electronic device is a terminal or server. The terminal can be a computer, tablet computer, etc. This embodiment does not limit the type of electronic device.
[0065] It should be noted that the low-capacity balanced bridge in this application refers to a balanced bridge structure with a low power level used for midpoint voltage regulation. In engineering implementation, it is usually achieved by reducing the power level of the switching devices, inductors and current sensing units. Therefore, it is also referred to as a low-power balanced bridge in some descriptions.
[0066] Reference Figure 1 , Figure 1 This is a schematic diagram of the topology of the low-capacity balanced bridge in this embodiment. As shown in the figure, two switching transistors are connected in series between the positive bus and the negative bus, which are the upper bridge arm switching transistors. and lower bridge arm switch tube Upper bridge arm switch tube With lower bridge arm switch tube The connection nodes between them form the midpoint of the bridge arm of the balanced bridge. The DC-side bus is formed by two bus capacitors connected in series, and the voltage of the upper bus capacitor is the positive bus voltage. The voltage of the lower bus capacitor is the negative bus voltage. The connection point of the two bus capacitors forms the midpoint of the bus capacitor. The midpoint of the balanced bridge arm and the midpoint of the bus capacitor are connected by an inductor. The connection is such that the current flowing through the inductor is the bridge current. Since this bridge arm structure is only used for current regulation at the midpoint of the bus capacitor and does not undertake main power transmission, the switching transistor... Switching transistor ,inductance Both the current sensing unit and the current sensing unit use relatively low power ratings, and the above structure constitutes a low-capacity balanced bridge.
[0067] During operation, the upper bridge arm switching transistor is controlled. and lower bridge arm switch tube The conduction state can adjust the voltage at the midpoint of the balance bridge arm, thereby affecting the inductor. A voltage difference is formed at both ends, driving the inductor current. The inductor current flows between the balancing bridge and the midpoint of the bus capacitor. When the inductor current flows from the balancing bridge to the midpoint of the bus capacitor, current is injected into the midpoint of the bus capacitor; when the inductor current flows from the midpoint of the bus capacitor to the balancing bridge, current is drawn from the midpoint of the bus capacitor. By adjusting the duty cycle of the switching transistor to control the direction and magnitude of the inductor current, the charging and discharging states of the two bus capacitors can be changed, thereby regulating the positive bus voltage. With negative bus voltage The distribution relationship between them is used to achieve balanced control of the DC side midpoint voltage.
[0068] In implementation, this application constructs a dual closed-loop control structure around a low-capacity balanced bridge, employing a voltage-loop PI controller and a current-loop PI controller. The voltage-loop PI controller corresponds to the outer adjustment stage of the low-capacity balanced bridge, taking the midpoint voltage as input to generate the required current reference value for the balanced bridge output based on the degree of midpoint voltage deviation. The current-loop PI controller corresponds to the inner execution stage of the low-capacity balanced bridge, taking the difference between the current reference value and the actual current of the balanced bridge as input to adjust the upper bridge arm switching transistors. and lower bridge arm switch tube The duty cycle allows the actual current output of the low-capacity balanced bridge to track the current reference value.
[0069] Reference Figure 2 This is a flowchart illustrating the method for suppressing and limiting current of low-capacity balanced bridge fundamental frequency disturbance under unbalanced load provided in this application embodiment. The method includes at least the following steps:
[0070] Step S101: Collect the balance bridge current, positive bus voltage and negative bus voltage, and calculate the midpoint voltage and DC bus total voltage based on the positive bus voltage and negative bus voltage.
[0071] In step S101, the balanced bridge current is first collected. Positive bus voltage and negative bus voltage And based on the sampled positive bus voltage and negative bus voltage Calculate the midpoint voltage and DC bus total voltage Midpoint voltage and DC bus total voltage The calculation formula is as follows:
[0072] ;
[0073] Among them, the total voltage of the DC bus The voltage level is obtained by adding the positive bus voltage and the negative bus voltage, and is used to characterize the overall voltage level between the positive and negative buses; the midpoint voltage. The voltage difference between the positive and negative bus voltages is used to characterize the voltage distribution between the two bus capacitors. When the positive and negative bus voltages are equal, the midpoint voltage is... The voltage at the midpoint is zero when the positive bus voltage and the negative bus voltage are not equal. Deviating from zero.
[0074] Step S102: Perform fundamental frequency notch filtering on the midpoint voltage and output the filtered midpoint voltage.
[0075] In step S102, the midpoint voltage calculated in step S101 is... Perform fundamental frequency notch filtering. Due to the midpoint voltage... This reflects the voltage distribution between the two bus capacitors. Under unbalanced load conditions, the asymmetry of the load current will introduce significant fundamental frequency fluctuations at the DC side midpoint, causing the midpoint voltage to... A significant fundamental frequency component is superimposed on the midpoint voltage. For low-capacity balanced bridges, the power ratings of their switching transistors, inductors, and current sensing units are relatively low, and their regulation capability is mainly used to suppress the bias and low-frequency fluctuations of the midpoint voltage; if the midpoint voltage containing a significant fundamental frequency component is superimposed... If the fundamental frequency component is directly input to the regulator, the regulator will respond to it, resulting in a large fundamental frequency component in the regulating current of the balanced bridge. This consumes the control capacity originally intended for midpoint voltage balancing by the low-capacity balanced bridge. Therefore, before regulation, the midpoint voltage is first regulated using a fundamental frequency notch filter. The fundamental frequency component is suppressed, and the filtered midpoint voltage is output. .
[0076] Specifically, the midpoint voltage The input is processed by a notch filter, the center frequency of which is set to the fundamental frequency of the power grid. This is done to suppress the fundamental frequency component in the midpoint voltage. The filtered midpoint voltage... It can be represented as follows:
[0077] ;
[0078] in, The transfer function of the notch filter is expressed as follows:
[0079] ;
[0080] in, For the Laplace operator; Let be the center angular frequency of the notch filter, satisfying ; The fundamental frequency; is the damping coefficient of the notch filter, used to adjust the notch bandwidth. In the formula, the numerator... Used in The corresponding frequency position forms a zero point to suppress the signal component at that frequency; denominator This is used to ensure the dynamic characteristics and stability of the filter. Through the above fundamental frequency notch filtering process, the filtered midpoint voltage is obtained. .
[0081] Step S103: Input the filtered midpoint voltage into the voltage loop PI controller and output the current reference value.
[0082] In step S103, the filtered midpoint voltage obtained in step S102 is... As the input to the voltage loop PI controller, the voltage loop PI controller outputs a current reference value. Due to the filtered midpoint voltage The fundamental frequency component in the midpoint voltage has been filtered out, and what remains are mainly the bias and low-frequency fluctuation components that characterize the midpoint imbalance state. Therefore, the midpoint voltage offset can be converted into the current reference value required by the balance bridge through the voltage loop PI controller, so that the balance bridge outputs the corresponding regulating current according to the degree of midpoint voltage imbalance.
[0083] Specifically, current reference value The calculation formula is as follows:
[0084] ;
[0085] in, and These are the proportional and integral coefficients of the voltage loop PI controller, respectively. For the Laplace operator.
[0086] Step S104: Calculate the current reference value limit based on the total DC bus voltage, and use the limit value to perform interval limiting on the current reference value to obtain the current reference value after limiting.
[0087] In step S104, the current reference value obtained in step S103 is... Limiting is applied. Because the switching devices, inductors, and current sensing units of the low-capacity balancing bridge all use lower power ratings, the allowable current range is limited by the device capacity; therefore, the current reference value needs to be constrained. Simultaneously, changes in the DC bus voltage affect the amplitude of the balancing bridge inductor current change and the magnitude of the current ripple. When the total DC bus voltage... At lower voltage levels, the bus capacitors store less energy, requiring a larger regulating current under the same conditions to change the voltage distribution between the two bus capacitors; when the total DC bus voltage... At higher voltage levels, the voltage across the inductor increases, the rate of current change accelerates, and the current ripple also increases, making overcurrent more likely. Therefore, the total DC bus voltage is introduced during the current reference value limiting process. The current reference value limit is determined based on the total voltage of the DC bus.
[0088] Specifically, firstly, based on the total voltage of the DC bus... Calculate the limit value of the current reference value The calculation formula is as follows:
[0089] ;
[0090] in, and It is an adjustable coefficient, and satisfies , .because Therefore, when the total voltage of the DC bus When increased, the amplitude limit value Consequently, it decreases; when the total voltage of the DC bus decreases... When reduced, the amplitude limit value The current is increased accordingly, thus allowing the allowable range of the current reference value to adaptively adjust with changes in the bus voltage. The above linear relationship is only one implementation method; as long as the limit value decreases as the total DC bus voltage increases, it is acceptable. For example, it can also be implemented using a decreasing function such as an exponential function or a piecewise function.
[0091] Optionally, in the embodiments of this application, the adjustable coefficient and The value is determined based on the maximum allowable current range of the low-capacity balanced bridge and the operating range of the DC bus voltage. Let the operating range of the DC bus voltage be... ,in This is the lowest bus voltage. The highest bus voltage, when the bus voltage is At that time, the corresponding maximum allowable regulating current is When the bus voltage is At that time, the corresponding maximum allowable regulating current is Because the rate of current change and current ripple increase when the bus voltage rises, it satisfies... .
[0092] Adjustable coefficient and This can be determined through the following relationship:
[0093] ;
[0094] Therefore, we can conclude that:
[0095] ;
[0096] Using the above method, the adjustable coefficient can be determined based on the DC bus voltage operating range and the allowable current range of the balance bridge. and The above is just one possible value for the adjustable coefficient. and The value of the adjustable coefficient can be determined using other methods. and The value of the adjustable coefficient is not specified in this application. and The way values can be selected is restricted.
[0097] After obtaining the amplitude limit value Then, the current reference value A limiting process is performed to obtain the current reference value after limiting. The relationship is as follows:
[0098] ;
[0099] Because the balancing bridge uses inductor current to bidirectionally regulate the current between the midpoint of the bridge arm and the midpoint of the bus capacitor, the inductor current flowing from the balancing bridge to the midpoint of the bus capacitor is in the positive direction, and the inductor current flowing from the midpoint of the bus capacitor to the balancing bridge is in the negative direction. Therefore, the current reference value... It can be either positive or negative. To ensure that the current in both directions is constrained, the current reference value's limiting range is set to... Thus, the current reference value after limiting is obtained. .
[0100] Step S105: Input the difference between the current reference value after limiting and the balance bridge current into the current loop PI controller, and calculate the balance bridge duty cycle based on the output of the current loop PI controller, the negative bus voltage and the total DC bus voltage, and then generate a PWM signal to drive the balance bridge switching transistor based on the duty cycle.
[0101] In step S105, the current reference value after limiting obtained in step S104 is... With the balance bridge current By comparison, the current deviation is obtained. The current deviation is then input to the current loop PI controller for adjustment. Because the balance bridge is connected via an inductor... A current path is established between the midpoint of the bridge arm and the midpoint of the bus capacitor. The magnitude of the inductor current directly determines the ability to inject or extract current into or from the midpoint of the bus capacitor, thus affecting the voltage distribution between the two bus capacitors. Therefore, by using the current reference value... With actual current By comparing the current and adjusting the current deviation using a current loop PI controller, the inductor current can be controlled. Tracking current reference value This enables closed-loop control of the balance bridge current.
[0102] Specifically, the current loop PI controller generates a current regulation amount based on the current deviation and correlates it with the negative bus voltage. and the total voltage of the DC bus Both are involved in the duty cycle calculation. Since the voltage at the midpoint of the balanced bridge arm is determined by the duty cycle of the switching transistor, and the voltage across the inductor is equal to the difference between the voltage at the midpoint of the bridge arm and the voltage at the midpoint of the bus capacitor, adjusting the duty cycle can change the voltage across the inductor, thereby changing the trend of the inductor current.
[0103] Therefore, by converting the output of the current loop PI controller into a duty cycle, the inductor current can be regulated. Duty cycle The calculation formula is as follows:
[0104] ;
[0105] in, and These are the proportional and integral coefficients of the current loop PI controller, respectively. For the Laplace operator. After obtaining the duty cycle... Then, regarding the duty cycle PWM modulation is performed to generate a drive signal, and the generated PWM signal is used to drive the upper arm switching transistor of the balanced bridge. Simultaneously, it generates a complementary PWM signal to drive the lower bridge arm switching transistor. By changing the duty cycle of the switching transistor, the voltage at the midpoint of the bridge arm can be adjusted, thereby changing the inductance. The voltage at both ends controls the flow of inductor current between the midpoint of the balance bridge arm and the midpoint of the bus capacitor, thereby regulating the DC side midpoint voltage.
[0106] In summary, combining Figure 3 The technical solution of this application does not directly send the original neutral point voltage into the balanced bridge control link, but first sends it from the positive bus voltage. and negative bus voltage The midpoint voltage was calculated. Total voltage of DC bus Then the midpoint voltage The filtered midpoint voltage is obtained after conversion by a factor of 0.5 and processing with a notch filter. The voltage signal is then converted into a current reference value by the voltage loop PI controller. Because the large fundamental frequency component superimposed on the midpoint voltage under unbalanced load conditions consumes the limited regulation capacity of the low-capacity balancing bridge, if the original midpoint voltage is directly used for control, the voltage loop will continuously respond to this fundamental frequency fluctuation, resulting in a large fundamental frequency regulation component in the output current of the balancing bridge. This disperses the control capability truly used to suppress midpoint imbalance bias and low-frequency fluctuations. This application sets a notch filter before the voltage loop, effectively separating the fundamental frequency disturbance component in the midpoint voltage that contributes little to midpoint balance control from the control input. Then, the PI controller generates a current reference value around the filtered midpoint voltage. Therefore, the regulating current of the balancing bridge more concentratedly corresponds to the midpoint imbalance itself, reducing the interference of fundamental frequency fluctuations on the midpoint voltage balance control effect from the control link.
[0107] Furthermore, this application does not employ a fixed limit on the current reference value, but rather uses the total DC bus voltage. Calculate the amplitude limit Then check the current reference value Obtain by limiting the amplitude Then, combined with the actual balanced bridge current The duty cycle is generated by a current loop PI controller. And drive the upper tube and lower pipe This means that the allowable range of the current reference value is no longer fixed, but varies with the bus voltage state: when the bus voltage is low, the limiting value can be relaxed accordingly, allowing the balancing bridge to output a more sufficient regulating current without causing overcurrent; when the bus voltage is high, the limiting value is tightened accordingly to suppress the overcurrent risk caused by excessively rapid current changes and increased ripple. Therefore, this application, on the one hand, reduces the occupation of the control link by notch filtering, and on the other hand, uses a limiting mechanism related to bus voltage to ensure that the balancing bridge maintains a relatively sufficient regulating capability within the safety boundary under different bus voltage conditions. Thus, it can specifically improve the technical problems of existing low-capacity balancing bridge control methods where the midpoint voltage balance control effect under unbalanced load conditions is easily affected by fundamental frequency fluctuations, and where fixed limiting is difficult to accommodate different bus voltage conditions.
[0108] Two application examples of this application are given below to further illustrate the application effect of the control method described above. Figure 4 This is a system topology diagram of a low-capacity balancing bridge applied to a diode-clamped three-level converter in an embodiment of this application. In this topology, the balancing bridge is used to adjust the midpoint voltage of the DC-side bus capacitor, and its parameters are set as follows: rated voltage RMS value 230V, frequency 50Hz, T... s =62.5μs, L nl =764μH, K pu =4.5, K iu =102, K pi =0.0046, K ii =168, bus capacitance 9.84mF.
[0109] The first example is used to verify the effect of the fundamental frequency notch filter. The experimental conditions are: DC bus voltage... Notch filter damping coefficient The load consists of two 6.8kW asynchronous motors in phase A, and phases B and C are unloaded. Figure 5 The experimental waveforms are shown without the 50Hz notch filter. Figure 6 The experimental waveforms after adding a 50Hz notch filter are shown. Figure 4 It can be seen that without the 50Hz notch filter, due to the significant fundamental frequency fluctuation of the midpoint voltage, the regulating current of the low-capacity balanced bridge needs to respond simultaneously to both the fundamental frequency component and the low-frequency oscillation component of the midpoint voltage. This results in insufficient suppression of the low-frequency oscillation of the midpoint voltage by the balanced bridge, leading to significant distortion in the output voltage and current. After adding the 50Hz notch filter to the midpoint voltage signal, as shown... Figure 6 As shown, the fundamental frequency component in the midpoint voltage is suppressed, and the regulation capability of the low-capacity balancing bridge is used more to suppress the low-frequency oscillation of the midpoint voltage, so that the midpoint voltage fluctuation is significantly reduced and the system can operate normally in steady state.
[0110] The second example verifies the effectiveness of adjusting the current reference value for limiting based on the bus voltage. The experimental conditions are: DC bus voltage... The load consists of three 6.8kW asynchronous motors in phase A, and phases B and C are unloaded. Figure 7 The following is an experimental waveform diagram when using a fixed current reference value for limiting, where the limiting value is... .from Figure 7 It can be seen that, due to the fixed limiting value and the small allowable current range, the output current of the low-capacity balanced bridge is insufficient to provide enough midpoint voltage regulation capability, resulting in insufficient midpoint voltage balancing capability, which causes output current oscillation and eventually shutdown. Figure 8 This is an experimental waveform diagram showing the current limiting based on the bus voltage reference value, where the parameters are... , When the bus voltage is low, the current reference value limit is increased accordingly, enabling the balance bridge to output a larger regulating current, thereby improving the midpoint voltage regulation capability of the low-capacity balance bridge, effectively suppressing low-frequency oscillations of the midpoint voltage, and restoring the output voltage and current waveforms to normal.
[0111] Figure 9 This is a block diagram of a low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control system under unbalanced load according to an embodiment of this application. The system includes at least the following modules:
[0112] The voltage calculation module is used to collect the balance bridge current, positive bus voltage and negative bus voltage, and calculate the midpoint voltage and the total DC bus voltage based on the positive bus voltage and negative bus voltage;
[0113] The filtering module is used to perform fundamental frequency notch filtering on the midpoint voltage and output the filtered midpoint voltage.
[0114] The reference value calculation module is used to input the filtered midpoint voltage into the voltage loop PI controller and output a current reference value.
[0115] The interval limiting module is used to calculate the limiting value of the current reference value based on the total voltage of the DC bus, and to use the limiting value to perform interval limiting on the current reference value to obtain the current reference value after limiting.
[0116] The switching control module is used to input the difference between the current reference value after limiting and the balance bridge current into the current loop PI controller, and calculate the balance bridge duty cycle based on the output of the current loop PI controller, the negative bus voltage and the total DC bus voltage, and then generate a PWM signal to drive the balance bridge switching transistor based on the duty cycle.
[0117] For relevant details, please refer to the above method implementation examples.
[0118] Figure 10This is a block diagram of an electronic device provided in one embodiment of this application. The device includes at least a processor 501 and a memory 502.
[0119] Processor 501 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 501 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 501 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 501 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 501 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.
[0120] The memory 502 may include one or more computer-readable storage media, which may be non-transitory. The memory 502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 502 is used to store at least one instruction, which is executed by the processor 501 to implement the low-capacity balanced bridge baseband disturbance suppression and current limiting control method under unbalanced load provided in the method embodiments of this application.
[0121] In some embodiments, the electronic device may also optionally include: a peripheral device interface and at least one peripheral device. The processor 501, memory 502, and peripheral device interface can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface via a bus, signal line, or circuit board. Indicatively, peripheral devices include, but are not limited to: radio frequency circuits, touch displays, audio circuits, and power supplies.
[0122] Of course, electronic devices may also include fewer or more components, and this embodiment does not limit this.
[0123] Optionally, this application also provides a computer-readable storage medium storing a program that is loaded and executed by a processor to implement the low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control method under unbalanced load in the above-described method embodiments.
[0124] Optionally, this application also provides a computer product including a computer-readable storage medium storing a program, which is loaded and executed by a processor to implement the low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control method under unbalanced load in the above-described method embodiments.
[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0126] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for suppressing fundamental frequency disturbance and controlling current limiting of a low-capacity balanced bridge under unbalanced load, characterized in that, The topology of the low-capacity balanced bridge is as follows: An upper bridge arm switch is connected in series between the positive and negative busbars. and lower bridge arm switch tube The upper bridge arm switch tube With the lower bridge arm switch tube The connection nodes form the midpoint of the balanced bridge arm; the DC side bus includes an upper bus capacitor and a lower bus capacitor connected in series, and the voltage of the upper bus capacitor is the positive bus voltage. The voltage of the lower bus capacitor is the negative bus voltage. The connection point between the two forms the midpoint of the bus capacitor; the midpoint of the balanced bridge arm and the midpoint of the bus capacitor are connected by an inductor. Connection, the inductor The current flowing through it is the bridge current. ; The method includes: Collect the balance bridge current, positive bus voltage, and negative bus voltage, and calculate the midpoint voltage and the total DC bus voltage based on the positive bus voltage and the negative bus voltage; The midpoint voltage is subjected to fundamental frequency notch filtering, and the filtered midpoint voltage is output. The filtered midpoint voltage is input to the voltage loop PI controller and the current reference value is output. The current reference value is limited based on the total DC bus voltage, and the current reference value is limited by the limit value to obtain the limited current reference value. The difference between the limited current reference value and the balanced bridge current is input to the current loop PI controller. The balanced bridge duty cycle is calculated based on the output of the current loop PI controller, the negative bus voltage, and the total DC bus voltage. A PWM signal is then generated based on the duty cycle to drive the balanced bridge switching transistors. This includes: The obtained current reference value after limiting With the balance bridge current By comparison, the current deviation is obtained. The current deviation is then input to a current loop PI controller for adjustment; the current loop PI controller generates a current adjustment amount based on the current deviation and correlates it with the negative bus voltage. and the total voltage of the DC bus Jointly participate in duty cycle calculation; Duty cycle The calculation formula is as follows: ； in, and These are the proportional and integral coefficients of the current loop PI controller, respectively. For the Laplace operator; obtain the duty cycle Then, regarding the duty cycle PWM modulation is performed to generate a drive signal, and the generated PWM signal is used to drive the upper arm switching transistor of the balanced bridge. Simultaneously, it generates a complementary PWM signal to drive the lower bridge arm switching transistor. .
2. The method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in claim 1, characterized in that, The voltage loop PI controller takes the midpoint voltage as input and outputs a balanced bridge current reference value. The current loop PI controller takes the balanced bridge current reference value and the balanced bridge current... The difference is taken as input, and the upper bridge arm switch is controlled according to the adjustment result. With the lower bridge arm switch tube The duty cycle of the balance bridge current is adjusted to ensure that the current in the balance bridge is... Track the current reference value.
3. The method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in claim 1, characterized in that, The process of acquiring the balanced bridge current, positive bus voltage, and negative bus voltage, and calculating the midpoint voltage and total DC bus voltage based on the positive and negative bus voltages includes: Collect balanced bridge current Positive bus voltage and negative bus voltage And based on the positive bus voltage obtained from the sampling and negative bus voltage Calculate the midpoint voltage and DC bus total voltage Midpoint voltage and DC bus total voltage The calculation formula is as follows: 。 4. The method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in claim 1, characterized in that, The step of performing fundamental frequency notch filtering on the midpoint voltage and outputting the filtered midpoint voltage includes: Midpoint voltage The input is processed by a notch filter, and the midpoint voltage after filtering is... It can be represented as follows: ； in, The transfer function of the notch filter is expressed as follows: ； in, For the Laplace operator; Let be the center angular frequency of the notch filter, satisfying ; The fundamental frequency; is the damping coefficient of the notch filter.
5. The method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in claim 1, characterized in that, The step of inputting the filtered midpoint voltage into the voltage loop PI controller and outputting a current reference value includes: The current reference value The calculation formula is as follows: ； in, This is the filtered midpoint voltage. and These are the proportional and integral coefficients of the voltage loop PI controller, respectively. For the Laplace operator.
6. The method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in claim 1, characterized in that, The step of calculating the current reference value based on the total DC bus voltage and then using the limiting value to perform interval limiting on the current reference value to obtain the limited current reference value includes: Based on the total voltage of the DC bus Calculate the limit value of the current reference value The calculation formula is as follows: ； in, and It is an adjustable coefficient, and satisfies , ; After obtaining the amplitude limit value Then, the current reference value A limiting process is performed to obtain the current reference value after limiting. The relationship is as follows: 。 7. A low-capacity balanced bridge fundamental frequency disturbance suppression and current limiting control system under unbalanced load, characterized in that, The topology of the low-capacity balanced bridge is as follows: An upper bridge arm switch is connected in series between the positive and negative busbars. and lower bridge arm switch tube The upper bridge arm switch tube With the lower bridge arm switch tube The connection nodes form the midpoint of the balanced bridge arm; the DC side bus includes an upper bus capacitor and a lower bus capacitor connected in series, and the voltage of the upper bus capacitor is the positive bus voltage. The voltage of the lower bus capacitor is the negative bus voltage. The connection point between the two forms the midpoint of the bus capacitor; the midpoint of the balanced bridge arm and the midpoint of the bus capacitor are connected by an inductor. Connection, the inductor The current flowing through it is the bridge current. ; The system includes: The voltage calculation module is used to collect the balance bridge current, positive bus voltage and negative bus voltage, and calculate the midpoint voltage and the total DC bus voltage based on the positive bus voltage and the negative bus voltage; The filtering module is used to perform fundamental frequency notch filtering on the midpoint voltage and output the filtered midpoint voltage. The reference value calculation module is used to input the filtered midpoint voltage into the voltage loop PI controller and output a current reference value. An interval limiting module is used to calculate the limiting value of the current reference value based on the total voltage of the DC bus, and to use the limiting value to perform interval limiting on the current reference value to obtain the limited current reference value. A switching control module is used to input the difference between the limited current reference value and the balanced bridge current into a current loop PI controller, calculate the balanced bridge duty cycle based on the output of the current loop PI controller, the negative bus voltage, and the total DC bus voltage, and then generate a PWM signal to drive the balanced bridge switching transistor based on the duty cycle, including: The obtained current reference value after limiting With the balance bridge current By comparison, the current deviation is obtained. The current deviation is then input to a current loop PI controller for adjustment; the current loop PI controller generates a current adjustment amount based on the current deviation and correlates it with the negative bus voltage. and the total voltage of the DC bus Jointly participate in duty cycle calculation; Duty cycle The calculation formula is as follows: ； in, and These are the proportional and integral coefficients of the current loop PI controller, respectively. For the Laplace operator; obtain the duty cycle Then, regarding the duty cycle PWM modulation is performed to generate a drive signal, and the generated PWM signal is used to drive the upper arm switching transistor of the balanced bridge. Simultaneously, it generates a complementary PWM signal to drive the lower bridge arm switching transistor. .
8. An electronic device, characterized in that, The device includes a processor and a memory; the memory stores a program, which is loaded and executed by the processor to implement a method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, The storage medium stores a program that, when executed by a processor, is used to implement a method for suppressing and limiting the fundamental frequency disturbance of a low-capacity balanced bridge under unbalanced load as described in any one of claims 1 to 6.