Low-bandwidth trans-impedance amplifier and binary sampling optical receiver
By using a low-bandwidth transimpedance amplifier and a binary sampling optical receiver structure, and employing feedforward decision and adjustable threshold sampling, the problem of bandwidth and noise trade-off in traditional optical receivers is solved, realizing a high-sensitivity and low-power optical communication system.
Patent Information
- Application Number
- CN202512050045.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-14
AI Technical Summary
Traditional optical receivers, when increasing the bandwidth of the transimpedance amplifier to avoid intersymbol interference, experience increased noise, leading to decreased receiver sensitivity, and feedback path delay limits performance at high speeds.
The optical receiver structure employs a low-bandwidth transimpedance amplifier and binary sampling. It utilizes a feedforward decision method and an adjustable threshold sampling mechanism to form a symmetrical differential voltage signal through multiple common-source amplifier stages and a variable gain amplifier, and uses a dual sampling array for binary decoding.
It improves receiver sensitivity while reducing system bandwidth requirements, achieving a balance between power consumption, area, and data rate. It has excellent practical value and is suitable for implementation using CMOS standard processes.
Smart Images
Figure CN121864038A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optical communication technology, and in particular to a low-bandwidth transimpedance amplifier and a binary sampling optical receiver. Background Technology
[0002] With the ever-increasing demand for bandwidth density and energy efficiency in data centers, short-distance high-speed optical interconnect technology has gradually replaced traditional copper electrical connections, becoming the mainstream interconnect solution. Among these, intensity-modulated direct-detection (IMDD) optical links are widely used in 400G / 800G-level optical module designs due to their advantages such as simple structure, low cost, and low power consumption. An IMDD optical receiver mainly consists of a photodetector, transimpedance amplifier, post-amplifier, and decision logic. As a key analog front-end in the link, the TIA directly affects key performance indicators such as system sensitivity, power consumption, and noise bandwidth performance.
[0003] To avoid severe inter-symbol interference, traditional NRZ (Non-Return-to-Zero) optical receivers require transimpedance amplifiers with bandwidth exceeding the data rate; otherwise, signal spectral broadening will lead to severe vertical eye diagram compression and insufficient decision margin. However, increasing the transimpedance amplifier bandwidth comes at the cost of increased system noise, especially when the feedback resistance decreases, resulting in a significant increase in thermal noise density and a decrease in receiver sensitivity. Summary of the Invention
[0004] This invention provides a low-bandwidth transimpedance amplifier and a binary sampling optical receiver to solve the technical problems of high power consumption, complex structure, and difficulty in balancing bandwidth and noise in traditional optical receiving systems.
[0005] This invention provides a low-bandwidth transimpedance amplifier and a binary sampling optical receiver, comprising: Photodetector; A transimpedance amplifier is used to convert the current signal output by the photodetector into a differential voltage signal; A variable gain amplifier is used to amplify the differential voltage signal to different degrees and perform DC compensation to obtain an output signal; A dual sampling array is used to perform binary sampling on the compensated output signal, and binary decoding and output are completed through an XOR gate.
[0006] In one embodiment of the present invention, the transimpedance amplifier includes a positive output path and a negative output path. The current signal generates a positive output voltage through the positive output path; the current signal generates a negative output voltage through the negative output path. The resistance value of the feedback resistor in the positive output path is adjustable. The secondary output path consists of three series-connected common-source amplifier stages and a single-ended slip stage, so that the negative output voltage is symmetrical with the positive output voltage, resulting in a symmetrical differential voltage signal.
[0007] In one embodiment of the present invention, the feedback resistor is composed of multiple resistor branches connected in parallel. Each resistor branch is formed by a transmission gate and a resistor connected in series, and the resistance value of the resistor connected in series in each resistor branch is different.
[0008] In one embodiment of the present invention, the three common-source amplifier stages are connected in series and then in parallel with the feedback resistor. Each common-source amplifier stage includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected to each other as the input terminal of the corresponding common-source amplifier stage, and their drains are connected to each other as the output terminal of the corresponding common-source amplifier stage. A transimpedance is connected in series between the input and output terminals of the last two common-source amplifier stages.
[0009] In one embodiment of the present invention, the single-ended slip stage includes a first stage structure and a second stage structure connected in series. The first stage structure is connected to the output terminal of the multiple common-source amplifier stages, and the output terminal of the second stage structure outputs the negative output voltage. The first stage structure and the second stage structure both include the structure of the first stage common-source amplifier stage, and the input terminal and output terminal of the second stage structure are directly connected.
[0010] In one embodiment of the present invention, the variable gain amplifier includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a common-mode feedback amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first current source, and a second current source. The gates of the first PMOS transistor and the first NMOS transistor are interconnected and connected to the positive output voltage of the transimpedance amplifier; the gates of the second PMOS transistor and the second NMOS transistor are interconnected and connected to the negative output voltage of the transimpedance amplifier; the source of the first PMOS transistor is connected to the drain of the fifth PMOS transistor and one end of the first resistor; the source of the first NMOS transistor is grounded through the first current source; the source of the second PMOS transistor is connected to the other end of the first resistor and the drain of the sixth PMOS transistor; the second resistor is connected in series between the sources of the first NMOS transistor and the second NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and connected to the gate of the third PMOS transistor, the gate of the third NMOS transistor, and one end of the third resistor; the source of the third PMOS transistor is connected to the power supply voltage, and its drain is connected to the drain of the third NMOS transistor and the other end of the third resistor as the variable gain amplifier. The negative output terminal of the variable gain amplifier is provided; the source of the third NMOS transistor is grounded; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the fourth PMOS transistor, one end of the fourth resistor, and the gate of the fourth NMOS transistor; the source of the fourth PMOS transistor is connected to the power supply voltage, and the drain is connected to the other end of the fourth resistor and the drain of the fourth NMOS transistor as the positive output terminal of the variable gain amplifier, and the source of the fourth NMOS transistor is grounded; one end of the fifth resistor is connected to the drain of the fourth PMOS transistor, and one end of the sixth resistor is connected to the drain of the third PMOS transistor; the other end of the fifth resistor is connected to the other end of the sixth resistor and connected to the inverting input terminal of the common-mode feedback amplifier; the non-inverting input terminal of the common-mode feedback amplifier is connected to the reference voltage, and the output terminal is connected to the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor; the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the power supply voltage.
[0011] In one embodiment of the present invention, the dual-sampling array includes multiple sampling channels, each sampling channel consisting of a first sampler, a second sampler, and an XOR gate. The differential output of the first sampler serves as the differential input of the second sampler, and the sampling clocks of the first sampler and the second sampler are out of phase. The first sampler receives the output of the variable gain amplifier and a threshold voltage as inputs, wherein the output of the variable gain amplifier and the threshold voltage are both differential signals. The differential signal output by the second sampler serves as the input of the XOR gate.
[0012] In one embodiment of the present invention, the first sampler and the second sampler have the same circuit structure. The first sampler includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor. The gate of the fifth NMOS transistor is connected to a positive threshold voltage, and the gate of the eighth NMOS transistor is connected to a negative threshold voltage. The sources of the fifth, sixth, seventh, and eighth NMOS transistors are interconnected and connected to the drain of the ninth NMOS transistor. The gate of the sixth NMOS transistor is connected to the positive output voltage of the transimpedance amplifier. The gate of the seventh NMOS transistor is connected to the negative output voltage of the transimpedance amplifier. The drain of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor and the source of the tenth NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor and the source of the tenth NMOS transistor. The source of the eleventh NMOS transistor; the gate of the tenth NMOS transistor is connected to the gate of the eighth PMOS transistor, and is connected to the drain of the eleventh NMOS transistor, the drain of the ninth PMOS transistor, and the drain of the tenth PMOS transistor, serving as the positive output terminal of the sampler; the drain of the tenth NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the eleventh NMOS transistor, and the drain of the seventh PMOS transistor, serving as the negative output terminal of the sampler; the sources of the seventh, eighth, ninth, and tenth PMOS transistors are respectively connected to the power supply voltage.
[0013] The beneficial effects of this invention: This invention proposes a novel structure for information reconstruction using a low-bandwidth transimpedance amplifier (TIA) and a binary sampling optical receiver, namely a binary sampling receiver. This architecture eliminates the need for a feedback path, employs a feedforward decision method supplemented by an adjustable threshold sampling mechanism, ensuring sensitivity while avoiding the delay limitations of the feedback path. It achieves an excellent balance of power consumption, area, and speed under standard CMOS processes, possessing high practical value. Attached Figure Description
[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0015] In the attached diagram: Figure 1 This is a schematic diagram of the overall architecture of the optical receiver in one embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of a transimpedance amplifier in one embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of a variable gain amplifier in one embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of the sampler in one embodiment of the present invention; Figure 5 This is a schematic diagram of the impulse response curves of AFE under different production verification tests in one embodiment of the present invention; Figure 6 This is the output eye diagram of the AFE in one embodiment of the present invention.
[0016] The attached figures are labeled as follows: M11 - First PMOS transistor; M12 - First NMOS transistor; M13 - Second PMOS transistor; M14 - Second NMOS transistor; M15 - Third PMOS transistor; M16 - Third NMOS transistor; M17 - Fourth PMOS transistor; M18 - Fourth NMOS transistor; M19 - Fifth PMOS transistor; M20 - Sixth PMOS transistor; R DP - First resistor; R DN - Second resistor; R3 - Third resistor; R4 - Fourth resistor; Rcm2 - Fifth resistor; Rcm1 - Sixth resistor; M21 - Fifth NMOS transistor; M22 - Sixth NMOS transistor; M23 - Seventh NMOS transistor; M24 - Eighth NMOS transistor; M25 - Ninth NMOS transistor; M26 - Tenth NMOS transistor; M27 - Eleventh NMOS transistor; M28 - Seventh PMOS transistor; M29 - Eighth PMOS transistor; M30 - Ninth PMOS transistor; M31 - Tenth PMOS transistor; SA1 - First sampler; SA2 - Second sampler. Detailed Implementation
[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0018] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0019] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.
[0020] Research has found that: Traditional NRZ (Non-Return-to-Zero) optical receiver architectures require transimpedance amplifiers with bandwidth exceeding the data rate to avoid severe inter-symbol interference (ISI). Otherwise, signal spectral broadening leads to severe vertical eye diagram compression and insufficient decision margin. However, increasing the transimpedance amplifier bandwidth comes at the cost of increased system noise, especially when the feedback resistor decreases, resulting in a significant increase in thermal noise density and a decrease in receiver sensitivity. Furthermore, to further offset the ISI caused by insufficient bandwidth, some literature introduces continuous-time linear equalizers or decision feedback equalizers for equalization. For example, some propose reducing the transimpedance amplifier bandwidth and achieving improved sensitivity through a single-stage decision feedback equalizer. While this method has made some progress in noise control, the feedback equalizer must complete the decision and form feedback within an extremely short time, leading to significant challenges at high data rates, including feedback loop delay bottlenecks, increased dependence on clock phase, and increased risk of bit error propagation.
[0021] To reduce implementation difficulty, another approach is to use a multi-stage amplification structure instead of the transimpedance amplifier + equalizer architecture. This involves first slowly amplifying the bandwidth and then processing it in segments. For example, a two-stage parallel transimpedance amplifier structure can achieve a balance between gain and noise performance, but the overall power consumption and area are still relatively large. Other research proposes to pre-control inter-symbol interference by introducing pseudo-binary or partial response signal encoding, enabling the receiver to achieve high-sensitivity decision-making with lower bandwidth. Dual-binary signals have a three-level structure, and theoretically, decision-making can be achieved through dual-threshold sampling at specific locations. However, such methods mostly remain at the theoretical modeling level, lacking circuit-level implementation solutions. Especially in standard CMOS processes, limitations such as linearity, common-mode control, and clock phase matching make practical implementation difficult.
[0022] Based on the problems existing in the above-mentioned related technologies, the present invention proposes a low-bandwidth transimpedance amplifier and a binary sampling optical receiver. The technical solution of the present invention will be described in detail below with reference to specific embodiments.
[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of the overall architecture of an optical receiver in one embodiment of the present invention. The optical receiver includes: a photodetector; a transimpedance amplifier for converting the current signal output by the photodetector into a differential voltage signal; a variable gain amplifier for amplifying the differential voltage signal to different degrees and performing DC compensation to obtain an output signal; and a dual sampling array for binary sampling of the compensated output signal and performing binary decoding and output through an XOR gate. Specifically, the photodetector can be a light-emitting diode (LED) that converts the optical signal into a current signal. The current signal is fed into the transimpedance amplifier to convert it into a voltage signal. The variable gain amplifier includes a gain section and a DC compensation section. After the voltage signal is amplified to different degrees by the gain section, it is compensated by the DC compensation section to obtain a differential signal input to the binary sampling structure for sampling. The entire architecture uses a feedforward sampling path instead of the traditional DFE loop structure, which reduces the system bandwidth requirements while improving the receiving sensitivity.
[0024] In one embodiment, the transimpedance amplifier includes a positive output path and a negative output path. The current signal generates a positive output voltage through the positive output path and generates a negative output voltage through the negative output path. The resistance value of the feedback resistor in the positive output path is adjustable. The secondary output path consists of three series-connected common-source amplifier stages and a single-ended slip stage, so that the negative output voltage is symmetrical to the positive output voltage, resulting in a symmetrical differential voltage signal.
[0025] In one embodiment, the feedback resistor is composed of multiple parallel resistor branches. Each resistor branch consists of a transmission gate and a resistor connected in series, and the resistance value of the resistor connected in series in each resistor branch is different. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a transimpedance amplifier in one embodiment of the present invention. Figure 2Taking a feedback resistor composed of three resistor branches as an example, the resistances in the three branches are 1X, 1.5X, and 2X, respectively. The transimpedance amplifier is a three-stage series structure. The input terminal is connected to the photodiode PD. The first stage consists of a PMOS transistor M1 and an NMOS transistor M2, with their gates connected to the input. The source of M1 is connected to the power supply voltage, and the source of M2 is grounded. Their drains are connected as the first stage output, which is connected to the second stage M3 and M4. The second stage structure is the same as the first stage. The gates of M3 and M4 are connected to the input, the source of M3 is connected to the power supply voltage, and the source of M4 is grounded. Their drains are connected as the second stage output. The difference is that there is a transimpedance R2 between the input and output of the second stage. The third stage M4 and M5 are the same as the second stage. Their gates are connected to the input, the source of M4 is connected to the power supply voltage, and the source of M5 is grounded. Their drains are connected as the first stage output, and a resistor R3 is connected between the output and the input. At the same time, the feedback resistor RF consists of three parallel transmission gates TG1, TG2, and TG3 connected in series with resistors Rf1, Rf2, and Rf3.
[0026] In one embodiment, the single-ended slip stage includes a first-stage structure and a second-stage structure connected in series. The first-stage structure is connected to the output of the multi-stage common-source amplifier, and the output of the second-stage structure outputs the negative output voltage. Both the first-stage and second-stage structures include the structure of the first-stage common-source amplifier, and the input and output of the second-stage structure are directly connected. Specifically, the single-ended slip stage consists of M7, M8, M9, and M10, forming a two-stage series structure. The input is connected to the output of the front-end transimpedance amplifier. The first stage consists of PMOS transistor M7 and NMOS transistor M8, with their gates connected to the input. The source of M7 is connected to the power supply voltage, and the source of M8 is grounded. Their drains are connected as the first-stage output, connected to the second stage, M9 and M10. Their gates are connected to the first-stage output, and the source of M9 is connected to the power supply voltage. The source of M10 is grounded. Their drains are connected as the first-stage output, and the second-stage output is connected to the input. The differential positive output is the direct output of the transimpedance amplifier, and the negative output is the single-ended slip stage output.
[0027] In one embodiment, the variable gain amplifier includes a first PMOS transistor M11, a first NMOS transistor M12, a second PMOS transistor M13, a second NMOS transistor M14, a third PMOS transistor M15, a third NMOS transistor M16, a fourth PMOS transistor M17, a fourth NMOS transistor M18, a fifth PMOS transistor M19, a sixth PMOS transistor M20, a common-mode feedback amplifier, and a first resistor R. DP Second resistor R DN , third resistor R3, fourth resistor R4, fifth resistor Rcm2, sixth resistor Rcm1, first current source, second current source; The gates of the first PMOS transistor M11 and the first NMOS transistor M12 are interconnected and connected to the positive output voltage of the transimpedance amplifier; the gates of the second PMOS transistor M13 and the second NMOS transistor M14 are interconnected and connected to the negative output voltage of the transimpedance amplifier; the source of the first PMOS transistor M11 is connected to the drain of the fifth PMOS transistor M19 and one end of the first resistor RDP; the source of the first NMOS transistor M12 is grounded through the first current source; the source of the second PMOS transistor M13 is connected to the first resistor RDP. DP The other end and the drain of the sixth PMOS transistor M20; the second resistor R DN A series connection is made between the source of the first NMOS transistor M12 and the source of the second NMOS transistor; the drain of the first PMOS transistor M11 is connected to the drain of the first NMOS transistor M12, and is connected to the gate of the third PMOS transistor M15, the gate of the third NMOS transistor M16, and one end of the third resistor R3; the source of the third PMOS transistor M15 is connected to the power supply voltage, and its drain is connected to the drain of the third NMOS transistor M16 and the other end of the third resistor R3 as the negative output terminal of the variable gain amplifier; the source of the third NMOS transistor M16 is grounded; the drain of the second PMOS transistor M13 is connected to the drain of the second NMOS transistor M14, the gate of the fourth PMOS transistor M17, one end of the fourth resistor R4, and the gate of the fourth NMOS transistor M18; the fourth PMOS transistor M14... The source of transistor M17 is connected to the power supply voltage, and its drain is connected to the other end of the fourth resistor R4 and the drain of the fourth NMOS transistor M18, respectively, serving as the positive output terminal of the variable gain amplifier. The source of the fourth NMOS transistor M18 is grounded. One end of the fifth resistor Rcm2 is connected to the drain of the fourth PMOS transistor M17, and one end of the sixth resistor Rcm1 is connected to the drain of the third PMOS transistor M15. The other end of the fifth resistor Rcm2 is connected to the other end of the sixth resistor Rcm1 and is connected to the inverting input terminal of the common-mode feedback amplifier. The non-inverting input terminal of the common-mode feedback amplifier is connected to the reference voltage, and its output terminal is connected to the gate of the fifth PMOS transistor M19 and the gate of the sixth PMOS transistor M20, respectively. The sources of the fifth PMOS transistor M19 and the sixth PMOS transistor M20 are respectively connected to the power supply voltage.
[0028] Specifically, please refer to Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of a variable gain amplifier in one embodiment of the present invention. The variable gain amplifier consists of a two-stage structure. In the first stage, the gates of M11 and M12 are connected to the positive output of the transimpedance amplifier, and the gates of M13 and M14 are connected to the negative output of the transimpedance amplifier. The sources of M11 and M13 are connected through a first resistor R. DPConnect the M12 and M14 components, and then connect them to the drain terminals of current mirrors M19 and M20 respectively. Connect the sources of M19 and M20 to the power supply voltage. Connect the gates of M19 and M20 together, and then connect them to the output of the common-mode feedback amplifier. Connect the sources of M12 and M14 through a second resistor R. DN The first stage consists of M15, M16, M17, and M18. The gates of M17 and M18 are connected, then connected to the positive output of the first stage. Their drains are connected to the positive output. A fourth resistor R4 is connected in series between the drains and gates of M17 and M18. The gates of M15 and M18 are connected, then connected to the positive output of the first stage. Their drains are connected to the positive output. A third resistor R3 is connected in series between the drains and gates of M15 and M16. Finally, the positive and negative outputs of the variable gain amplifier are connected to the negative input of the common-mode feedback amplifier through identical resistors Rcm2 (fifth resistor) and Rcm1 (sixth resistor). The positive input of the common-mode feedback amplifier is connected to a reference voltage VREF.
[0029] In one embodiment, the dual-sampling array includes multiple sampling channels. Each sampling channel consists of a first sampler SA1, a second sampler SA2, and an XOR gate. The differential output of the first sampler SA1 serves as the differential input of the second sampler SA2, and the sampling clocks of the first sampler SA1 and the second sampler SA2 are out of phase. The first sampler SA1 receives the output of the variable gain amplifier and a threshold voltage as inputs, where both the output of the variable gain amplifier and the threshold voltage are differential signals. The differential signal output by the second sampler SA2 serves as the input of the XOR gate. The circuit structures of the first sampler SA1 and the second sampler SA2 are identical. The first sampler SA1 includes: a fifth NMOS transistor M21, a sixth NMOS transistor M22, a seventh NMOS transistor M23, an eighth NMOS transistor M24, a ninth NMOS transistor M25, a tenth NMOS transistor M26, an eleventh NMOS transistor M27, a seventh PMOS transistor M28, an eighth PMOS transistor M29, a ninth PMOS transistor M30, and a tenth PMOS transistor M31. The gate of the fifth NMOS transistor M21 is connected to a positive threshold voltage, and the gate of the eighth NMOS transistor M24 is connected to a negative threshold voltage. The sources of the fifth NMOS transistor M21, the sixth NMOS transistor M22, the seventh NMOS transistor M23, and the eighth NMOS transistor M24 are interconnected and connected to the drain of the ninth NMOS transistor M25. The gate of the sixth NMOS transistor M22 is connected to the positive output voltage of the transimpedance amplifier. The gate of the seventh NMOS transistor M23 is connected to the negative output voltage of the transimpedance amplifier. The drain of the fifth NMOS transistor M21 is connected to the drain of the sixth NMOS transistor M22 and the source of the tenth NMOS transistor M26. The drain of the seventh NMOS transistor M23 is connected to the drain of the eighth NMOS transistor M24 and the source of the tenth NMOS transistor M25. The source of the eleventh NMOS transistor M27; the gate of the tenth NMOS transistor M26 is connected to the gate of the eighth PMOS transistor M29, and is connected to the drain of the eleventh NMOS transistor M27, the drain of the ninth PMOS transistor M30, and the drain of the tenth PMOS transistor M31, serving as the positive output terminal of the sampler; the drain of the tenth NMOS transistor M26 is connected to the drain of the eighth PMOS transistor M29, the gate of the ninth PMOS transistor M30, the gate of the eleventh NMOS transistor M27, and the drain of the seventh PMOS transistor M28, serving as the negative output terminal of the sampler; the sources of the seventh PMOS transistor M28, the eighth PMOS transistor M29, the ninth PMOS transistor M30, and the tenth PMOS transistor M31 are respectively connected to the power supply voltage.
[0030] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram of the sampler circuit structure in one embodiment of the present invention. The gate of M21 is connected to the negative output voltage of the DAC; the gate of M22 is connected to the positive output of the front-end differential variable gain amplifier; the drains of M21 and M22 are connected, and their sources are connected; the gate of M23 is connected to the negative output of the front-end differential variable gain amplifier; the gate of M24 is connected to the positive output of the DAC; the drains of M23 and M24 are connected, and their sources are connected to the sources of M21 and M22, then connected to the drain of M25; the gate of M25 is connected to the clock signal, and its source is grounded. The drains of M21 and M22 are connected to the source of M26; the gates of M26 and M29 are connected, then connected to the drain of M30 and M27, and then connected to the positive output; the source of M31 is connected to the power supply voltage, its gate to the clock signal, and its drain to the positive output; the gates of M30 and M27 are connected to the drain of M26 and M29, then connected to the drain of M28 and the negative output; the source of M28 is connected to the power supply voltage, and its gate to the clock signal.
[0031] The dual sampling array uses differential input signals and differential output signals, and the two high-sensitivity samplers have opposite clocks.
[0032] In one embodiment, the optical receiver of the present invention is implemented using CMOS technology. The photodetector is an external PIN-type device connected to the front end of the chip via metal bonding wires, which have a certain equivalent inductance. The current signal generated by the photodetector is input to a multi-stage series transimpedance amplifier. This transimpedance amplifier adopts a multi-stage common-source stage structure and achieves inter-stage isolation and impedance matching through a source follower. The feedback resistor in the positive output path of the transimpedance amplifier can be 8.8kΩ, and this feedback resistor achieves a balance between high gain and controlled bandwidth through a three-stage parallel structure. It achieves a bandwidth corresponding to 25% of the data rate, and the pulse response at the output exhibits typical binary characteristics, providing good conditions for dual binary sampling. The transimpedance amplifier has a high overall gain, and the output common-mode voltage is controlled at a general power supply voltage, meeting the driving requirements of subsequent variable gain amplifiers and samplers.
[0033] In one embodiment, the transimpedance amplifier output signal is converted into a symmetrical differential signal via a single-ended to differential structure. The single-ended to differential structure module consists of an inverter loaded with an active current mirror and its simulated copy, ensuring both differential and wideband performance. This single-ended to differential structure has low total harmonic distortion and a high 3dB bandwidth. The differential output signal further enters a variable gain amplifier, which consists of a source-degraded CMOS differential pair and a transimpedance feedback amplifier, providing a wide gain adjustment range. The feedback resistor uses a 3-bit programmable resistor array, configured via a digital register. The variable gain amplifier internally employs a common-mode feedback circuit to maintain output common-mode stability and controls the tail current branch through an analog voltage reference to suppress process drift. The overall variable gain amplifier effectively compensates for the gain of the preceding transimpedance amplifier, ensuring sufficient voltage margin for the subsequent sampler. The output impulse response and eye diagram of the analog front-end (AFE) are as follows: Figure 5 and Figure 6 As shown.
[0034] In one embodiment, the sampling backend employs a four-phase 1 / 4 rate sampling structure, corresponding to four sub-channels. Each channel consists of two differential input high-sensitivity samplers and an XOR gate. The high-sensitivity samplers utilize a two-stage induction amplifier structure. The first stage acts as a preamplifier to enhance trigger sensitivity under small differential signal conditions, while the second stage latches and holds the output state. The two high-sensitivity samplers are configured with high and low threshold voltages, controlled by two sets of 7-bit current-to-analog converters, which, in conjunction with feedback resistors, generate the differential threshold voltages. The threshold generation circuit consists of two symmetrical parallel transimpedance amplifiers, with a structure identical to the main amplifier, ensuring that the threshold point matches the common mode of the differential signal under temperature drift and PVT variations, thereby achieving accurate mapping between the decision point and the reference threshold. The output of the high-sensitivity samplers enters the XOR gate to perform high-speed Boolean operations, completing binary decoding.
[0035] The optical receiver of this invention employs a controlled inter-symbol interference and dual-threshold sampling structure, overcoming the sensitivity of traditional DFE architectures to feedback path delay at high speeds, thus achieving higher data rates and energy efficiency. Furthermore, the system can achieve [data rate and energy efficiency ratio] with only 25% data rate bandwidth. The bit error rate of the 11.6 dBm OMA is better than 10. - The improved receiver sensitivity (¹²) significantly enhances the power-sensitivity performance boundary of the receiver. Furthermore, the elimination of large-resistance devices, continuous-time equalizers, or high-speed feedback networks significantly reduces system hardware complexity and reduces the integration area, making it suitable for on-chip deployment and large-scale integration. Finally, the use of dual-path sampling and precise threshold voltage control ensures the receiver exhibits excellent robustness under variations in process technology, voltage, and temperature, guaranteeing stable and reliable operation in real-world environments. Therefore, this invention possesses significant technical advantages and promotional value in realizing high-speed, low-power optical communication systems.
[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A low-bandwidth transimpedance amplifier with binary-sampled optical receiver, characterized by, include: Photodetector; A transimpedance amplifier is used to convert the current signal output by the photodetector into a differential voltage signal; A variable gain amplifier is used to amplify the differential voltage signal to different degrees and perform DC compensation to obtain an output signal; A dual sampling array is used to perform binary sampling on the compensated output signal, and binary decoding and output are completed through an XOR gate.
2. The low-bandwidth transimpedance amplifier and binary sampling optical receiver according to claim 1, characterized in that, The transimpedance amplifier includes a positive output path and a negative output path. The current signal generates a positive output voltage through the positive output path; the current signal generates a negative output voltage through the negative output path. The resistance value of the feedback resistor in the positive output path is adjustable. The negative output path consists of three series common-source amplifier stages and a single-ended slip stage, so that the negative output voltage is symmetrical with the positive output voltage, resulting in a symmetrical differential voltage signal.
3. The low-bandwidth transimpedance amplifier and binary sampling optical receiver according to claim 2, characterized in that, The feedback resistor is composed of multiple resistor branches connected in parallel. Each resistor branch consists of a transmission gate and a resistor connected in series, and the resistance value of the resistor connected in series in each resistor branch is different.
4. The low-bandwidth transimpedance amplifier and binary sampling optical receiver according to claim 3, characterized in that, The three common-source amplifier stages are connected in series and then in parallel with the feedback resistor. Each common-source amplifier stage includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected to serve as the input terminal of the corresponding common-source amplifier stage, and their drains are connected to each other to serve as the output terminal of the corresponding common-source amplifier stage. A transimpedance is connected in series between the input and output terminals of the last two common-source amplifier stages.
5. The low-bandwidth transimpedance amplifier and binary sampling optical receiver according to claim 4, characterized in that, The single-ended slip stage includes a first stage structure and a second stage structure connected in series. The first stage structure is connected to the output terminal of the multiple common-source amplifier stages, and the output terminal of the second stage structure outputs the negative output voltage. Both the first stage structure and the second stage structure include the structure of the first stage common-source amplifier stage, and the input terminal and output terminal of the second stage structure are directly connected.
6. The low-bandwidth transimpedance amplifier and binary-sampled optical receiver according to claim 4, characterized in that, The variable gain amplifier includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a common-mode feedback amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first current source, and a second current source. The gates of the first PMOS transistor and the first NMOS transistor are interconnected and connected to the positive output voltage of the transimpedance amplifier; the gates of the second PMOS transistor and the second NMOS transistor are interconnected and connected to the negative output voltage of the transimpedance amplifier; the source of the first PMOS transistor is connected to the drain of the fifth PMOS transistor and one end of the first resistor; the source of the first NMOS transistor is grounded through the first current source; the source of the second PMOS transistor is connected to the other end of the first resistor and the drain of the sixth PMOS transistor; the second resistor is connected in series between the sources of the first NMOS transistor and the second NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and connected to the gate of the third PMOS transistor, the gate of the third NMOS transistor, and one end of the third resistor; the source of the third PMOS transistor is connected to the power supply voltage, and its drain is connected to the drain of the third NMOS transistor and the other end of the third resistor as the variable gain amplifier. The negative output terminal of the variable gain amplifier is provided; the source of the third NMOS transistor is grounded; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the fourth PMOS transistor, one end of the fourth resistor, and the gate of the fourth NMOS transistor; the source of the fourth PMOS transistor is connected to the power supply voltage, and the drain is connected to the other end of the fourth resistor and the drain of the fourth NMOS transistor as the positive output terminal of the variable gain amplifier, and the source of the fourth NMOS transistor is grounded; one end of the fifth resistor is connected to the drain of the fourth PMOS transistor, and one end of the sixth resistor is connected to the drain of the third PMOS transistor; the other end of the fifth resistor is connected to the other end of the sixth resistor and connected to the inverting input terminal of the common-mode feedback amplifier; the non-inverting input terminal of the common-mode feedback amplifier is connected to the reference voltage, and the output terminal is connected to the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor; the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the power supply voltage.
7. The low-bandwidth transimpedance amplifier and binary-sampled optical receiver according to claim 1, characterized in that, The dual-sampling array includes multiple sampling channels. Each sampling channel consists of a first sampler, a second sampler, and an XOR gate. The differential output of the first sampler serves as the differential input of the second sampler, and the sampling clocks of the first sampler and the second sampler are out of phase. The first sampler receives the output of the variable gain amplifier and a threshold voltage as inputs, where both the output of the variable gain amplifier and the threshold voltage are differential signals. The differential signal output by the second sampler serves as the input of the XOR gate.
8. The low-bandwidth transimpedance amplifier and binary-sampled optical receiver according to claim 7, characterized in that, The first sampler has the same circuit structure as the second sampler. The first sampler includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor. The gate of the fifth NMOS transistor is connected to a positive threshold voltage, and the gate of the eighth NMOS transistor is connected to a negative threshold voltage. The sources of the fifth, sixth, seventh, and eighth NMOS transistors are interconnected and connected to the drain of the ninth NMOS transistor. The gate of the sixth NMOS transistor is connected to the positive output voltage of the transimpedance amplifier. The gate of the seventh NMOS transistor is connected to the negative output voltage of the transimpedance amplifier. The drain of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor and the source of the tenth NMOS transistor. The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor and the source of the tenth NMOS transistor. The source of the eleventh NMOS transistor; the gate of the tenth NMOS transistor is connected to the gate of the eighth PMOS transistor, and is connected to the drain of the eleventh NMOS transistor, the drain of the ninth PMOS transistor, and the drain of the tenth PMOS transistor, serving as the positive output terminal of the sampler; the drain of the tenth NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the eleventh NMOS transistor, and the drain of the seventh PMOS transistor, serving as the negative output terminal of the sampler; the sources of the seventh, eighth, ninth, and tenth PMOS transistors are respectively connected to the power supply voltage.