All-digital phased array active silencing loudspeaker system based on storage bus multiplexing
By using a fully digital phased array loudspeaker system, the hardware topology is simplified. High-precision time synchronization and direct drive without analog power amplifiers are achieved by using STM32H7 chips and GaN power devices. This solves the complexity and timing error problems of existing silencing loudspeaker systems and improves the silencing effect and frequency limit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGZHOU SHENGTUO ELECTRONICS CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-04-14
AI Technical Summary
Existing silencing loudspeaker systems have complex hardware topologies, require a large number of GPIO expansion chips or expensive FPGAs, and suffer from timing errors and phase lag issues, which affect the silencing effect.
A fully digital phased array active silencing loudspeaker system based on storage bus multiplexing is adopted, including a network digital audio acquisition module, a central processing control module, a signal distribution module, and a drive array module. It utilizes STM32H7 chips and GaN power devices to achieve high-precision time synchronization and direct drive without analog power amplifiers.
It greatly simplifies the hardware topology, provides a purer noise reduction effect, increases the upper frequency limit, ensures precise sound wave superposition, reduces latency to the nanosecond level, and eliminates the impact of phase drift.
Smart Images
Figure CN121865181A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of loudspeakers, and more specifically to a fully digital phased array active anechoic loudspeaker system based on memory bus multiplexing. Background Technology
[0002] A silencer loudspeaker system typically refers to a system that uses "active noise control" or has special acoustic structures, such as directional sound or metamaterials, to manage the range of sound propagation. It does more than just play sound; its core functions are "silencing" to reduce or cancel unwanted noise and "sound control" to precisely control the sound within a specific area.
[0003] Existing silencer systems have the following pain points and shortcomings: Traditional multi-channel systems require stacking a large number of GPIO expansion chips or using expensive FPGAs, resulting in extremely complex circuits and easy timing errors between channels. Traditional cardioid speakers rely on a "DAC + analog amplifier + LC filter". The analog LC filter inevitably introduces phase lag, causing high-frequency sound wave cancellation to fail. The conventional DSP solution outputs signals serially. There is a slight time difference between the signals received by the first speaker and the 20th speaker, which disrupts the focus of beamforming.
[0004] Therefore, existing technologies need to be improved, hardware topology simplified, noise reduction effect improved, and sound wave superposition enhanced. Summary of the Invention
[0005] To address the aforementioned technical issues, a fully digital phased array active noise cancellation loudspeaker system based on memory bus multiplexing is proposed, which simplifies the hardware topology, improves the noise reduction effect, and enhances sound wave superposition.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A fully digital phased array active silencing loudspeaker system based on storage bus multiplexing includes a network digital audio acquisition module, a central processing and control module, a signal distribution module, and a driver array module, wherein: The network digital audio acquisition module is used to receive digital audio data packets from Ethernet, perform protocol unpacking and data buffering, and recover high-precision global master clock signal and frame synchronization signal from the network data stream to form a serial digital audio signal that is transmitted to the central processing and control module. The central processing control module is used to calculate the differential delay and gain parameters required by the front and rear arrays of the received serial digital audio signal in real time according to the preset cardioid directivity strategy, and obtain a high-speed parallel bus data stream. The signal distribution module is used to receive a single high-speed parallel bus data stream from the central processing control module, expand the parallel bus into a multi-partition array control signal, and then "decode" and "latch" it into multiple independent and time-synchronized pulse control signals.
[0007] The drive array module is used to receive the pulse control signal and perform chopping modulation on the high-voltage DC bus using GaN power devices.
[0008] Specifically, the circuit principles of each module are as follows: The network digital audio acquisition module includes the Dante network audio interface unit.
[0009] Preferably, the main control chip of the central processing control module is an STM32H7, and the central processing control module is equipped with an external memory controller interface.
[0010] Preferably, the signal distribution module includes an address decoding unit and multiple sets of parallel latch units, wherein the address decoding unit uses a 74LVC1G139 or equivalent logic device.
[0011] Preferably, the driving array module includes multiple independent GaN half-bridge power stage units with identical structures.
[0012] Preferably, the physical signal input terminal of the network digital audio acquisition module is connected to the secondary coil of the network isolation transformer and is connected to an external Ethernet via an RJ45 interface; The digital audio signal output terminal of the network digital audio acquisition module establishes a communication connection with the serial audio interface pin of the central processing control module. The reset and status indication pins of the network digital audio acquisition module are connected to the general-purpose input / output pins of the central processing control module.
[0013] Preferably, the central processing control module is connected to the audio acquisition module through an internally integrated SAI interface controller; The central processing control module is connected to the data input terminals of all latch units in the signal distribution module via the 16-bit parallel data bus of the external memory controller. The central processing control module is connected to the control input terminal of the address decoder in the signal distribution module via the address bus and write enable signal line.
[0014] Preferably, the input terminal of the address decoding unit of the signal distribution module is connected to the address line and write control line of the central processing control module.
[0015] Preferably, the input terminal of each power stage unit of the drive array module is connected to the corresponding PWM output terminal of the signal distribution module.
[0016] Beneficial technical effects of the present invention: The central processing control module of this invention achieves independent control of 20 channels using a single bus, which greatly simplifies the hardware topology; The speaker is driven by a gallium nitride high-speed power stage direct switching. The delay from the central processing control module to the speaker voltage change is only on the nanosecond level, and there is no phase drift across the entire frequency band. This greatly improves the upper frequency limit of "back interference cancellation" and makes the noise reduction effect purer. Each bit of the data bus of the central processing control module is redefined as a switch trigger for each speaker in the space, achieving synchronization at the physical limit (error < 5ns), making the superposition of sound waves in the air as precise as a laser. Attached Figure Description
[0017] Figure 1 This is a circuit schematic diagram of the network digital audio acquisition module in this invention; Figure 2 This is a schematic diagram of the central processing control module circuit in this invention; Figure 3 This is a circuit schematic diagram of the signal distribution module in this invention; Figure 4 This is the circuit schematic of the driving array module in this invention. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments. However, the scope of protection of this invention is not limited to the specific embodiments described below.
[0019] like Figures 1 to 4 As shown, the all-digital phased array active silencing loudspeaker system based on storage bus multiplexing includes a network digital audio acquisition module, a central processing and control module, a signal distribution module, and a drive array module, wherein: The network digital audio acquisition module is used to receive digital audio data packets from Ethernet, perform protocol unpacking and data buffering, and recover high-precision global master clock signal and frame synchronization signal from the network data stream to form a serial digital audio signal that is transmitted to the central processing and control module. The central processing control module is used to calculate the differential delay and gain parameters required by the front and rear arrays of the received serial digital audio signal in real time according to the preset cardioid directivity strategy, and obtain a high-speed parallel bus data stream.
[0020] Specifically, the preset cardioid directivity strategy is based on the principle of acoustic wave interference and is achieved by configuring the delay and phase relationship between the front array and the rear array. Specifically, the front array is set as the main radiation source, outputting an audio signal with the original phase; the rear array is set as the cancellation source, outputting an inverted audio signal, and a specific acoustic delay Δt is superimposed on the rear array signal.
[0021] The delay Δt is equal to the physical distance d between the front and rear speaker arrays divided by the speed of sound c: that is, Δt = d / c. Through the above strategy, the sound waves emitted by the rear array are out of phase and time-aligned with the diffracted sound waves from the front array when propagating backward, thus causing destructive interference and achieving a cardioid directivity effect of back-side silence.
[0022] The specific calculation process is as follows: The central processing control module first copies the received single-channel serial PCM audio data into 20 parallel data streams; then, using internal ring buffer technology, it applies the sampling point offset corresponding to the acoustic delay Δt to the 4 data streams allocated to the rear array; at the same time, it multiplies the rear array data by a negative gain coefficient to achieve phase inversion and amplitude matching; finally, it converts the processed 20 high-bit-width PCM data into 20 1-bit high-speed switching signals through pulse density modulation or noise shaping algorithms to adapt to the output format of the parallel bus.
[0023] The signal distribution module is used to receive a single high-speed parallel bus data stream from the central processing control module, expand the parallel bus data stream into a multi-partition array control signal, and "decode" and "latch" it into multiple sets of independent and time-synchronized pulse control signals.
[0024] The drive array module is used to receive the pulse control signal and perform chopping modulation on the high-voltage DC bus using GaN power devices.
[0025] The principle and process of chopper modulation in this embodiment are as follows: GaN power devices integrate a half-bridge driver circuit. When a logic "1" high-level pulse signal is received, the upper transistor of the half-bridge is driven to turn on and the lower transistor to turn off, instantly raising the output potential to the high-voltage DC bus voltage (HV_BUS). When a logic "0" low-level pulse signal is received, the upper transistor is driven to turn off and the lower transistor to turn on, instantly lowering the output potential to power ground (GND). The modulation result is a high-energy square wave sequence at the output of the GaN device, with an amplitude equal to the high-voltage bus voltage and a duty cycle or pulse density varying with the audio signal amplitude. This square wave sequence is directly applied to the speaker load, using the inherent inductance of the speaker voice coil as a low-pass filter to restore the high-frequency square wave to an analog sound wave that drives air vibration, thus achieving direct digital drive without an analog power amplifier.
[0026] Specifically, the circuit principles of each module are as follows: like Figure 1 As shown, the network digital audio acquisition module includes a Dante network audio interface unit, whose input is connected to the network transformer and whose output establishes a communication connection with the main control module.
[0027] This module is configured to extract high-precision master clock signal MCLK, bit clock signal BCLK, and frame synchronization signal LRCLK from network data packets, and transmit the unpacked PCM digital audio data stream SD to the central processing control module in real time via the serial audio interface SAI / I2S. As the system's master clock source, the network digital audio acquisition module ensures strict synchronization between the subsequent signal processing links and the source sampling rate, eliminating phase noise caused by clock drift.
[0028] like Figure 2 As shown, the central processing control module uses an STM32H7 series microcontroller as its computing core and is equipped with an external memory controller interface. This module abandons the traditional audio DAC output path, configuring its external memory controller interface FMC / EMI as the output port for parallel control signals.
[0029] The microcontroller internally runs a beamforming and pulse density modulation (PDM) algorithm to decode the input single-channel audio signal into 20 independent spatial drive vectors in real time. The microcontroller outputs modulated switching instructions through its 16-bit parallel data bus and time-division multiplexing (TDM) switching instructions through the address bus FMC_A0.
[0030] This module utilizes the synchronous write capability of the parallel bus to ensure that control commands for all channels are physically aligned within a nanosecond time window.
[0031] like Figure 3 As shown, the signal distribution module includes an address decoding unit and multiple sets of parallel latch units. The address decoding unit uses a 74LVC1G139 or equivalent logic device.
[0032] The address decoding unit uses a 74LVC1G139 or equivalent logic device, and the input of the address decoding unit is connected to the write enable signal NWE and the address signal A0 of the microcontroller.
[0033] When the address signal is in the first logic state (e.g., low level), the decoding unit triggers the first latch clock (LATCH_CLK_FRONT), locking the bus data to the front array latch (16 channels); when the address signal is in the second logic state (e.g., high level), the decoding unit triggers the second latch clock (LATCH_CLK_BACK), locking the bus data to the rear cancelling array latch (4 channels). This circuit structure enables alternating refresh and independent control of the front and rear sound field arrays via a single bus.
[0034] like Figure 4 As shown, the drive array module includes multiple independent GaN half-bridge power stage units with identical structures. In this embodiment, the drive array module contains 20 independent GaN half-bridge power stage units with identical structures. The input terminal of each power stage unit is connected to the corresponding PWM output terminal of the signal distribution module.
[0035] Unlike traditional Class D amplifiers, this driver array module eliminates the need for a post-stage LC reconstruction filter, employing a direct-drive topology. The input signal, after being processed by a logic inverting and shaping circuit, generates complementary high / low-side drive signals to control the high-speed turn-on and turn-off of an integrated GaN power chip (such as the LMG5200). The high-voltage power supply terminal of the GaN power chip is connected to the DC bus (HV_BUS), and its output is directly coupled to the acoustic transducer (loudspeaker). The driver array module utilizes the inherent inductance of the loudspeaker's voice coil and the mechanical integration effect of air to reproduce sound waves, physically eliminating the group delay and phase distortion introduced by passive filters, thus ensuring the effectiveness of high-frequency interference silencing.
[0036] In this embodiment, the drive array module includes 20 independent and identical GaN half-bridge power stage units. The input terminal of each power stage unit is connected to the corresponding PWM output terminal of the signal distribution module.
[0037] The connections between the modules are as follows: The physical signal input terminal of the network digital audio acquisition module is connected to the secondary coil of the network isolation transformer and is connected to an external Ethernet (Dante network) via an RJ45 interface; the digital audio signal output terminal of the network digital audio acquisition module establishes a communication connection with the serial audio interface pin of the central processing control module; the reset and status indication pins of the network digital audio acquisition module are connected to the general purpose input / output (GPIO) pins of the central processing control module to realize system initialization handshake and status monitoring.
[0038] In this embodiment, the digital audio signal output terminal includes an SD data line, a BCLK bit clock line, an LRCLK frame clock line, and an MCLK master clock line.
[0039] The central processing control module, as the core of the system's computation, is located at the hub of the signal chain. The central processing control module is connected to the data input terminals of all latch units in the signal distribution module via the 16-bit parallel data bus of the external memory controller; the central processing control module is also connected to the control input terminal of the address decoder in the signal distribution module via the address bus and write enable signal line.
[0040] Specifically, the central processing control module's uplink connection is achieved through its internally integrated SAI interface controller, which acts as a slave to receive I2S format audio data streams from the audio acquisition module; the downlink data connection is achieved through its external memory controller's 16-bit parallel data bus, which connects to the data input terminals of all latch units in the signal distribution module; and the downlink control connection is achieved through its address bus (FMC_A0) and write enable signal line (FMC_NWE), which connects to the control input terminal of the address decoder in the signal distribution module, used to send time-division multiplexing switching commands.
[0041] The signal distribution module is located between the MCU and the power stage, and serves to perform logic splitting and signal latching.
[0042] The input terminal of the address decoding unit of the signal distribution module is connected to the address line and write control line of the central processing control module.
[0043] Specifically, the decoder is connected as follows: the input of the address decoder is connected to the address lines and write control lines of the central processing control module; its first output (Y0) is connected to the clock input (CLK) of the front array latch group, and its second output (Y1) is connected to the clock input (CLK) of the rear array latch group.
[0044] Latch input connections: The data input terminals (D terminals) of the front array latch group (16 channels) and the rear array latch group (4 channels) are all connected in parallel to the same 16-bit parallel data bus of the central processing control module.
[0045] Latch output connections: The 16 outputs (Q terminals) of the front array latch group are connected one-to-one to the power stage input terminal corresponding to the front speaker in the drive array module. The 4 outputs (Q terminals) of the rear array latch group are connected one-to-one to the power stage input terminal corresponding to the rear cancelling speaker in the drive array module.
[0046] The drive array module is the final stage actuator of the system, directly driving the physical load. The input terminal of each power stage unit of the drive array module is connected to the corresponding PWM output terminal of the signal distribution module.
[0047] Specifically, the signal input connection includes 20 independent GaN power stage units, and the logic input terminal (PWM_IN) of each unit is connected to the corresponding latch output pin of the signal distribution module.
[0048] Power Connections: The high-voltage power supply pins (VIN) of all power stage units are connected to the DC high-voltage bus (HV_BUS) and grounded through a large-capacity energy storage capacitor; the power supply pins of the GaN driver chip are connected to a 5V regulated power supply, while the power supply pins of the remaining logic control chips and microcontrollers are connected to a 3.3V regulated power supply.
[0049] Load connection: The output terminal (SW_Node) of the switching node of each power stage unit is directly electrically connected to the positive terminal of the speaker unit, and the negative terminal of the speaker unit is connected to the power ground (PGND), forming a direct drive loop without a filter.
[0050] The working principle of the fully digital phased array active silencing loudspeaker system based on memory bus multiplexing of this invention is as follows: First, the network digital audio acquisition module receives digital audio data packets (AoIP) from the Ethernet, performs protocol unpacking and data buffering; simultaneously, it recovers the high-precision global master clock signal (MCLK) and frame synchronization signal from the network data stream. The demodulated standard serial digital audio stream (PCM) is then transmitted in real-time to the central processing control module, ensuring that the signal processing of the entire array system maintains strict frequency locking and phase alignment with the source end, eliminating clock jitter in the transmission link.
[0051] The central processing and control module receives the input single-channel audio signal and, based on a preset cardioid directivity strategy, calculates the differential delay and gain parameters required by the front and rear arrays in real time. Innovatively, the central processing and control module converts the calculated acoustic parameters into high-frequency switching commands and utilizes the bit width characteristics of the parallel external memory interface to map the audio values in the time domain into multi-channel parallel drive vectors in the spatial domain, achieving precise, fully digital control of the sound field.
[0052] The signal distribution module receives parallel data and address instructions from the central processing control module and uses hardware decoding logic to perform nanosecond-level time-division switching of the control bus. This module "decodes" and "latches" a single high-speed parallel bus data stream into multiple sets of independent and time-synchronized pulse control signals, thereby achieving independent addressing and parallel refreshing of the front main array and the rear cancellation array with limited processor pin resources.
[0053] The drive array module receives low-voltage logic pulse control signals from the signal distribution module and directly chops and modulates the high-voltage DC bus using the extremely high switching speed characteristics of GaN power devices. This module directly drives multiple speaker units to physically vibrate without relying on traditional analog filters. It utilizes the low-pass filtering characteristics of air to reconstruct sound waves and achieves the desired cardioid directional sound field distribution through the superposition and interference of sound waves from multiple units in physical space.
[0054] Based on the disclosure and teachings of the foregoing specification, those skilled in the art can make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the invention should also fall within the protection scope of the claims of the present invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on the invention.
Claims
1. A fully digital phased array active silencing loudspeaker system based on memory bus multiplexing, characterized in that, It includes a network digital audio acquisition module, a central processing and control module, a signal distribution module, and a driver array module, among which: The network digital audio acquisition module is used to receive digital audio data packets from Ethernet, perform protocol unpacking and data buffering, and recover high-precision global master clock signal and frame synchronization signal from the network data stream to form a serial digital audio signal that is transmitted to the central processing and control module. The central processing control module is used to calculate the differential delay and gain parameters required by the front and rear arrays of the received serial digital audio signal in real time according to the preset cardioid directivity strategy, and obtain a high-speed parallel bus data stream. The signal distribution module is used to receive a single high-speed parallel bus data stream from the central processing control module, expand the parallel bus data stream into a multi-partition array control signal, and then form multiple sets of independent and time-synchronized pulse control signals. The drive array module is used to receive the pulse control signal and perform chopping modulation on the high-voltage DC bus using GaN power devices.
2. The all-digital phased array active anechoic speaker system based on memory bus multiplexing as described in claim 1, characterized in that, The network digital audio acquisition module includes the Dante network audio interface unit.
3. The all-digital phased array active anechoic speaker system based on storage bus multiplexing as described in claim 2, characterized in that, The main control chip of the central processing control module is STM32H7, and the central processing control module is equipped with an external memory controller interface.
4. The all-digital phased array active anechoic speaker system based on storage bus multiplexing as described in claim 3, characterized in that, The signal allocation module includes an address decoding unit and multiple sets of parallel latch units. The address decoding unit uses a 74LVC1G139 or equivalent logic device.
5. The all-digital phased array active silencing loudspeaker system based on storage bus multiplexing as described in claim 4, characterized in that, The driving array module includes multiple independent GaN half-bridge power stage units with identical structures.
6. The all-digital phased array active anechoic speaker system based on memory bus multiplexing as described in claim 5, characterized in that, The physical signal input terminal of the network digital audio acquisition module is connected to the secondary coil of the network isolation transformer and is connected to an external Ethernet via an RJ45 interface. The digital audio signal output terminal of the network digital audio acquisition module establishes a communication connection with the serial audio interface pin of the central processing control module. The reset and status indication pins of the network digital audio acquisition module are connected to the general-purpose input / output pins of the central processing control module.
7. The all-digital phased array active anechoic speaker system based on memory bus multiplexing as described in claim 6, characterized in that, The central processing control module is connected to the audio acquisition module through an internally integrated SAI interface controller; The central processing control module is connected to the data input terminals of all latch units in the signal distribution module via the 16-bit parallel data bus of the external memory controller. The central processing control module is connected to the control input terminal of the address decoder in the signal distribution module via the address bus and write enable signal line.
8. The all-digital phased array active anechoic speaker system based on memory bus multiplexing as described in claim 7, characterized in that, The input terminal of the address decoding unit of the signal distribution module is connected to the address line and write control line of the central processing control module.
9. The all-digital phased array active silencing loudspeaker system based on memory bus multiplexing as described in claim 8, characterized in that, The input terminal of each power stage unit of the drive array module is connected to the corresponding PWM output terminal of the signal distribution module.