Median filter circuit, filtering method and image based on random bit stream correlation
By using a median filter circuit based on the correlation of random bit streams, and leveraging a shared random number source and a three-level sorting operation, the hardware overhead and power consumption issues of the median filter circuit are resolved, resulting in a shorter critical path and lower circuit area, adapting to the needs of different data windows.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI UNIV OF TECH
- Filing Date
- 2026-03-02
- Publication Date
- 2026-06-09
AI Technical Summary
Existing median filter circuits have significant problems in terms of hardware overhead and power consumption. Especially when sharing a random number generator, the correlation between random bit streams increases the complexity of subsequent circuit design, and the hardware cost of traditional binary methods is high.
By employing a median filter circuit based on the correlation of random bit streams, and utilizing the positive correlation between random bit streams through a shared random number source and three-level sorting operations (column sorting, row sorting, and diagonal sorting), a simple logic gate structure is designed to achieve parallel sorting and reduce hardware overhead.
While ensuring computational accuracy, the critical path was shortened, the hardware overhead and power consumption of the circuit were reduced, different data window sizes were adapted, and the computational speed and overall circuit performance were improved.
Smart Images
Figure CN122178873A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of median filtering technology, specifically to a median filtering circuit, filtering method, and image based on the correlation of random bit streams. Background Technology
[0002] Filtering circuits are crucial in digital image / video processing, audio / speech processing, and wireless communication. Median filtering is a typical nonlinear filtering technique used to eliminate impulse noise, such as salt-and-pepper noise, in images or videos. Compared to mean filtering and Gaussian filtering algorithms, median filtering achieves higher edge preservation in images.
[0003] The typical goal of a median filter circuit is to sort the sampled values in a sliding window, find the median, and then replace the center pixel value in the window with the median. The most typical median filter uses a full sort, with each sort employing a Compare and Swap (CAS) module to compare the values of two pixels and swap them according to design requirements. However, implementing the CAS module in a traditional binary manner incurs significant hardware costs due to the design complexity of the digital comparator.
[0004] As an emerging computing paradigm, random computation (SC) replaces weighted binary computation (BC) with its unweighted data encoding mode, potentially reducing circuit design complexity. In "Computation on Stochastic Bit Streams Digital Image Processing Case Studies," Li proposed a sorting module that utilizes a tanh function based on random bit streams for computation, applying random computation to filtering circuits. While this reduces hardware overhead compared to traditional binary circuits, the need for a random number source (RNS) for each input data point during random number conversion leads to excessive power consumption in the random number conversion section, increasing its proportion of overall circuit power consumption.
[0005] In the field of random computing, hardware overhead can be reduced by sharing an RNS in a stochastic number generator (SNG). However, this approach results in strong correlation between the generated random bit streams, which increases the complexity of decorrelation design in subsequent circuits. Therefore, a feasible approach is to focus on utilizing the correlation between random bit streams and the simple logic gate functionality under positively correlated bit streams, rather than removing the correlation between bit streams, to design subsequent circuits, while sharing the RNS and obtaining lower hardware overhead.
[0006] Therefore, based on the shared RNS structure in random computing circuits and the premise of reducing the hardware overhead of random bit stream conversion, a median filter circuit structure implemented using random bit stream correlation and simple logic gates is proposed. Compared with traditional binary circuits and other existing non-shared RNS random circuit structures, it achieves a balance between shortening the critical path, computing speed and hardware resources while ensuring the same computational accuracy. This is a technical direction with research value. Summary of the Invention
[0007] The technical problem this invention aims to solve is to propose a median filter circuit based on random bitstream correlation with a topology-dependent structure that significantly reduces hardware overhead. This median filter circuit maintains the same precision as traditional binary computation while shortening the critical path through parallel sorting of input data and appropriate selection of the sorting unit topology. It also alleviates wiring congestion and reduces hardware overhead by sharing the RNS during random bitstream conversion, and its topology-dependent structure meets the application requirements of different computation window sizes.
[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0009] A median filtering circuit based on the correlation of random bit streams includes: a median filtering module; wherein the median filtering module includes a comparison and exchange module; based on a shared random number source, the random bit streams operated in the comparison and exchange modules are all positively correlated, and a three-level sorting operation is adopted, namely column sorting, row sorting and diagonal sorting, and the final output result is the random bit stream corresponding to the median value of the input data.
[0010] In this embodiment, the internal circuitry of the comparison and exchange module includes multiple logic gates AND and OR; The minimum input value is obtained through a multi-input AND gate; the comparison of two data paths in the multi-input AND gate is implemented as the first step to obtain the intermediate value; the results of all two-input AND gates are passed through a multi-input OR gate as the second step to obtain the final intermediate value; the maximum input value is obtained through a multi-input OR gate.
[0011] In this embodiment, the final output is a random bitstream corresponding to the intermediate value of the input data, including: Column sorting section: The bit stream corresponding to each column of data in the input window serves as the input to the same comparison and exchange module of the column sorting section. The output of the comparison and exchange module is the random bit stream corresponding to the sorted result of this column of data. Row sorting section: The random bit streams at the same sequence positions in the sorting outputs of the comparison and swapping modules in the column sorting section are used as the inputs of the same comparison and swapping module in the row sorting section. The outputs of the comparison and swapping modules in the row sorting section realize the row sorting based on the column sorting. Diagonal sorting section: Select data from the diagonal of the sorted window from the sorting output of the comparison and exchange module of the row sorting section. Group the data on each diagonal as a group and use it as the input of the same comparison and exchange module of the diagonal sorting section. The output is to obtain the intermediate value.
[0012] In this embodiment, when a single-layer diagonal sort cannot yield an intermediate value, the layers of the diagonal sort can be increased in the same way until an intermediate value is obtained.
[0013] In this embodiment, the median filtering circuit includes a random number generator and a counter. The random number generator converts the data in the window into corresponding random bit streams with positive correlation. The median filtering module outputs the random bit stream corresponding to the median value of the window data. Finally, the counter counts the number of times 1 appears in the random bit stream, thereby converting the random bit stream back to the original data mode and realizing the median filtering function.
[0014] In this embodiment, the random number generator includes a shared random number source and multiple comparators; the shift register in the random number source generates a random bit stream by feedback shifting after an initial seed bit stream is given; the random bit stream and the input window data are respectively used as inputs to multiple comparators, and by comparing the size of the input window data and the bit stream data, the comparator outputs a continuous but not fixed 0 / 1 sequence.
[0015] The present invention also provides a filtering method using the median filtering circuit based on random bitstream correlation described above, comprising: Based on a shared random number source, the random bit streams operated by the comparison and swapping modules in the median filtering module are all positively correlated. A three-level sorting operation is used, namely column sorting, row sorting and diagonal sorting, and the final output result is the random bit stream corresponding to the median value of the input data.
[0016] An image is subjected to the filtering method described above to eliminate impulse noise.
[0017] Compared with the prior art, the beneficial effects of the present invention are: Compared to conventional binary median filtering circuits and existing median filtering circuits in the field of random computation, the median filtering circuit based on random bitstream correlation proposed in this invention can achieve a shorter critical path or a balance between computation speed and circuit hardware overhead while ensuring the same computational accuracy. This can be achieved through parallel sorting of window input data and reasonable selection of the topology of sorting units. Furthermore, by reusing and replacing the proposed CAS module and sharing an RNS during the random bitstream conversion stage, smaller circuit area and hardware overhead can be achieved, thereby reducing the overall power consumption of the circuit.
[0018] The filtering circuit of this invention utilizes the positive correlation between random bit streams for processing. Under the premise of using the mature shared RNS scheme, unlike other inventions that consider removing correlation, it instead considers directly using correlation and simple logic gate structure to design subsequent circuits. This can reduce circuit hardware overhead, avoid the impact of designing and evaluating decorrelation circuits on the circuit, simplify the topology, and clarify the overall circuit architecture.
[0019] This invention has good versatility and integrability: for input data windows of different sizes, the CAS unit topology can be configured according to the number of sorted input data, and the topology can be adapted by reusing the CAS module. Furthermore, CAS modules with different numbers of input ports can be replaced, resulting in high layout reusability.
[0020] This invention provides a circuit structure based on the positive correlation of random bit streams, which is compatible with data windows of various sizes. The random bit stream conversion process of all input data shares a single RNS. Based on the positively correlated random bit streams, it achieves a trade-off between performance, area / power consumption, and accuracy, greatly reducing hardware overhead while ensuring computational accuracy. For error-tolerant scenarios such as image / video, voice / sensor signal processing, and fault-tolerant calculations, it significantly reduces latency and power consumption while meeting application layer quality indicators. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a median filter circuit based on the correlation of random bit streams according to an embodiment of the present invention.
[0022] Figure 2 This is a schematic diagram of the overall architecture of the median filter circuit based on random bit stream correlation according to an embodiment of the present invention.
[0023] Figure 3 This is a circuit diagram of the three-input comparison and switching module according to an embodiment of the present invention.
[0024] Figure 4 This is a flowchart illustrating the algorithm for obtaining values from window data as proposed in an embodiment of the present invention.
[0025] Figure 5 This is a comparison chart of the image processing effects of the median filtering circuit proposed in this invention, the traditional binary circuit, and other existing schemes based on random computation circuits, as shown in the embodiments of this invention. Detailed Implementation
[0026] To facilitate understanding of the technical solution of the present invention by those skilled in the art, the technical solution of the present invention will now be further described in conjunction with the accompanying drawings.
[0027] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0028] Please see Figure 1 As shown, this invention provides a median filtering circuit based on the correlation of random bit streams, including a median filtering module MF. The median filtering module MF includes a comparison and exchange module CAS, based on a shared random number source RNS. The random bit streams operated on in the comparison and exchange module CAS are all positively correlated, employing a three-level sorting operation: column sorting, row sorting, and diagonal sorting. The final output is the random bit stream corresponding to the median value of the input data.
[0029] Please see Figure 2 As shown, in one embodiment of the present invention, the median filtering circuit further includes a random number generator (SNG) and a counter. The random number generator (SNG) converts the data in the window into corresponding positively correlated random bit streams. These streams are then passed through the median filtering module (MF) and output as random bit streams corresponding to the median value of the window data. Finally, the counter counts the number of occurrences of '1' in the random bit stream, thereby converting the random bit stream back to the original data mode and achieving the median filtering function.
[0030] In this embodiment, the random number generator (SNG) converts the input window data into a corresponding random bit stream. An SNG includes a shared random number source (RNS) and multiple comparators (CMPs). The RNS includes a shift register that continuously generates new random bit streams through feedback shifting after an initial seed bit stream is given. The random bit stream and the input window data are used as inputs to the multiple CMPs, respectively. The output of each CMP is a continuous but not fixed-position 0 / 1 sequence, which represents the random bit stream corresponding to the input window data. During the bit stream conversion process, the generated random bit streams are designed to have maximum positive correlation and share the same random number source (RNS), significantly reducing the hardware overhead of the SNG.
[0031] Specifically, the random number source (RNS) uses a shift register with feedback. The XOR result of bits 0, 2, 3, and 7 is placed as the feedback value in the least significant bit of the shift register. All bitstream conversion processes of the input data share a single random number source (RNS), but each data has its own comparator (CMP).
[0032] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, the median filtering module MF uses the comparison and exchange module CAS as the basic unit to sort the window data by column, row and diagonal to obtain the random bit stream corresponding to the median value of the window data.
[0033] Please see Figure 3 As shown, in this embodiment, the comparison and exchange module CAS includes multiple logic gates AND and OR. For different numbers of input data, the comparison and exchange module can be expanded to include a three-input comparison and exchange module, a four-input comparison and exchange module, a five-input comparison and exchange module, and so on.
[0034] In this embodiment, the minimum input value is obtained by using a multi-input logic gate AND; the comparison of two data paths in the multi-input ...
[0035] More specifically, this invention is explained using the three-input comparison and switching module CAS3. Table 1 is the truth table of the three-input comparison and switching module CAS3, where a, b, and c are three input ports, and max, med, and min are three output ports. The CAS3 module sorts the three input values, which are a bitstream of random 0 / 1 values. The value of output port max is the maximum value among the three input ports, the value of output port med is the median value among the three input ports, and the value of output port min is the minimum value among the three input ports.
[0036] Table 1 Truth Table for the Three-Input Compare and Exchange Module
[0037] Figure 3 The circuit structure diagram of the three-input compare and switch module CAS3 is given. Figure 3 (a) is a module framework diagram, indicating that the module has three input ports and three output ports, and the output ports are the sorted results of the input port data; Figure 3 (b) shows the internal circuit structure of this module: The circuit includes four AND gates and two OR gates. The AND gates consist of three two-input AND gates and one three-input AND gate, while the OR gates consist of two three-input OR gates. The three input ports are connected to one of the three-input AND gates, which outputs the minimum value. The three input ports are also connected to one of the three-input OR gates, which outputs the maximum value. Two ends of each of the three ports are connected to the three two-input AND gates, and the outputs of these three two-input AND gates are connected to the other three-input OR gate, which outputs the intermediate value.
[0038] In this embodiment, as the number of input data increases, the comparison and exchange (CAS) module can be expanded on demand, while switching between CAS modules can be performed to achieve a balance between critical path length and hardware resources. For example, a four-input comparison and exchange module (CAS4) can be replaced with three three-input comparison and exchange modules (CAS3), and a five-input comparison and exchange module (CAS5) can be replaced with four three-input comparison and exchange modules (CAS3), etc.
[0039] In one embodiment of the present invention, the final output result is a random bit stream corresponding to the intermediate value of the input data, including: Column sorting section: The bit stream corresponding to each column of data in the input window serves as the input to the same comparison and exchange module in the column sorting section. The output of the comparison and exchange module is the random bit stream corresponding to the sorted result of this column of data.
[0040] Row sorting section: The random bitstreams at the same sequence positions in the sorting outputs of the comparison and swap modules in the column sorting section are used as inputs to the same comparison and swap module in the row sorting section. The outputs of each comparison and swap module in the row sorting section are used to perform row sorting based on the column sorting. Specifically, the maximum values in the outputs of the CAS modules of each comparison and swap module in the column sorting section are grouped into one group, the middle values into another group, the minimum values into another group, and so on. Each group serves as input to the same CAS module, and the outputs of each comparison and swap module in this section are used to perform row sorting based on the column sorting. Diagonal sorting section: Select data from the diagonal of the sorted window from the comparison and sorting output of the row sorting section. Group the data on each diagonal (including the main diagonal and the secondary diagonal) as a group, and use it as the input of the same comparison and sorting module for the diagonal sorting section. The output is to obtain the intermediate value.
[0041] For more details, please see Figure 4 The diagram shows the algorithm process for obtaining the median of a 3×3 window of data using the median filter circuit proposed in this invention. The algorithm comprises three stages: column sorting, row sorting, and diagonal sorting. Figure 4 The original data position shown in 'a' is used to perform column sorting. This is achieved by using the random bitstream corresponding to each column of data as input to the same comparison and exchange module (CAS module), thus generating... Figure 4 The sorted positions of the columns in b. Figure 4 In step b, the first row of data represents the maximum value of each column, the middle row represents the median value of each column, and the last row represents the minimum value of each column. Row sorting is then implemented based on this. The random bitstream corresponding to each row of data serves as input to the same comparison and exchange module (CAS module), which sorts each row of data and generates... Figure 4 The position of the rows in C after sorting. Figure 4 In C, the first column contains the maximum value of each row, the middle column contains the median value of each row, and the last column contains the minimum value of each row. At this point, O... 11 and O 33 These are the maximum and minimum values among all data; for O 12 and O 21 There must be at least 5 data points smaller than it; for O 23 and O 32 There must be at least 5 data points larger than it; therefore, the median value of the window data is generated at O. 13 O 22 and O 31 Data from three locations.
[0042] In this embodiment, the proposed invention utilizes a random bitstream from a shared random number source (RNS), leveraging its positive correlation and the cooperation of a sorting unit (CAS) to achieve lower energy consumption and area while ensuring circuit performance. The proposed CAS sorting unit can sort at least three data items. As the data window increases, the CAS unit topology can be adjusted to allow a single CAS unit to sort more than three data items simultaneously. By rationally selecting the CAS unit topology, the optimal number of sorting unit layers is achieved, resulting in a shorter critical path. Each CAS unit mainly consists of multiple logic gates. When designing the CAS unit topology, as the number of data items that can be sorted by a CAS unit increases, the number of logic gates constituting the CAS unit also increases. Rationally selecting the structure of the CAS unit topology further reduces energy consumption and area.
[0043] In this embodiment, the column sorting and row sorting parts can employ fully parallel processing structures or hierarchical parallel processing structures to achieve a balance between circuit calculation speed and circuit area. The diagonal part is expanded and adapted according to different data window sizes to achieve a balance between calculation latency and hardware overhead.
[0044] In one embodiment of the present invention, a counter is used to convert the random bit stream corresponding to the intermediate value of the sorted output. By counting the number of times 1 appears in the bit stream sequence, the result is the original data form corresponding to the bit stream, thus completing the final data output.
[0045] Please see Figure 1 As shown, an example structural diagram of the median filter circuit based on the correlation of random bitstreams proposed in this invention is used to illustrate the working principle of a median filter circuit suitable for a 3×3 window size designed based on the proposed architecture. This example uses a shared random number source (RNS) to construct a random number generator (SNG), generating a random bitstream with the maximum positive correlation corresponding to nine input data points within the window. Figure 1 As shown in (a), the SNG mainly consists of a random number source (RNS) and nine comparators. The RNS is mainly composed of an 8-bit shift register, and the feedback circuit is implemented through a logic gate XOR. The 8-bit random bit stream is compared with the nine input data by the CMP. When the input data is greater than the input random bit stream, the CMP outputs 1; otherwise, the CMP outputs 0. Each CMP generates a continuous but not fixed 0 / 1 sequence, which corresponds to the random bit stream of the nine input data. This sequence is then fed into the median filtering module MF.
[0046] like Figure 1As shown in (b), the sorting algorithm proposed in this invention is used for sorting: First, the input bitstream is sorted column-wise according to its original position in the window, obtaining the maximum, median, and minimum values of each column, which are then placed in the first, middle, and last rows of the window, respectively, generating new data positions after column sorting. Then, based on the column-sorted data positions, row sorting is performed, sorting each row of data to obtain the maximum, median, and minimum values of each row, which are then placed in the first, middle, and last columns of the window, respectively, generating new data positions after row sorting. Finally, analysis of the data at each position in the window shows that the median value is generated in the first row at the last column, the middle row at the middle column, and the last row at the first column. Based on this, the data at these three positions is further sorted, and the resulting median value is the median value of the window data. In the sorting stage, the three-input comparison and exchange module CAS3 is used as the basic sorting unit, such as... Figure 1(c) As shown: For example, the three input ports (the actual bit stream length in the circuit is 256, and the principle is explained here with a bit stream length of 10) are a bit stream 0001000001, b bit stream 0101000101, and c bit stream 1101100111. The three are positively correlated and enter a CAS3 module: (1) When a=1, b=1, c=1: a / b / c goes through three-input AND logic and the output result is 1; a / b or a / c or b / c goes through two-input AND logic and the output result is 1. The three intermediate results go through a three-input OR logic and the output result is 1; a / b / c goes through three-input OR logic and the output result is 1. (2) When a=0, b=0, c=1: a / b / c goes through three-input AND logic and the output result is 0; a / b goes through two-input AND logic and the output result is 0; a / c or b / c goes through two-input AND logic and the output result is 0; the three intermediate results go through one three-input OR logic and the output result is 0; a / b / c goes through three-input OR logic and the output result is 1. (3) When a=0, b=1, c=1: a / b / c goes through three-input AND logic and the output result is 0; b / c goes through two-input AND logic and the output result is 1; a / b or a / c goes through two-input AND logic and the output result is 0; the three intermediate results go through one three-input OR logic and the output result is 1; a / b / c goes through three-input OR logic and the output result is 1. (4) When a=0, b=0, c=0: a / b / c goes through three-input AND logic and the output result is 0; b / c or a / b or a / c goes through two-input AND logic and the output result is 0; the three intermediate results go through one three-input OR logic and the output result is 0; a / b / c goes through three-input OR logic and the output result is 0. According to the above circuit logic, the input bit stream is operated bit by bit. The maximum value port output is 1101100111; the intermediate value port output is 0101000101; and the minimum value port output is 0001000001, which can realize the sorting of the input bit stream. Using CAS3 as the basic unit, according to the sorting algorithm, the random bit stream corresponding to the intermediate value data is obtained from the window data bit stream. This bit stream is used as the input of the counter. By calculating the number of times 1 appears in the bit stream sequence, the counter can convert the bit stream data into the original data format, thus realizing median filtering.
[0047] Table 2 compares the hardware overhead of the median filter circuit based on random bitstream correlation proposed in this invention with that of a traditional binary median filter circuit and other existing median filter circuits based on random computation. The window size corresponding to the data in the table is 3×3, and the pixel range is 0~255. In the table, binary represents the traditional binary scheme, scc represents the non-shared RNS scheme based on random computation, and proposed represents the scheme proposed in this invention. Area includes three parts: total (overall area), SNG and core (core functional part), CDP is the critical path delay under consistent clock, and ADP and PDP are the circuit area delay product and power delay product calculated based on CDP and area, and CDP and power, respectively. The data shows that the median filter circuit proposed in this invention has improvements in area, power consumption and computation delay.
[0048] Table 2 Comparison of hardware overhead between the present invention and existing median filter circuits.
[0049] Figure 5 This image processing comparison chart shows the image processing performance of the median filter circuit proposed in this invention, a traditional binary circuit, and an existing non-shared RNS scheme based on random computation circuits. The processed image data window size is 3×3, and the pixel data range is 0~255. Figure 5 Based on the original image, it is assumed that 10% Gaussian salt-and-pepper noise is added to obtain... Figure 5 The image of b, then Figure 5 b is processed using a traditional binary median filter circuit, an existing non-shared RNS median filter circuit based on random computation circuits, and the median filter circuit proposed in this invention, respectively, to obtain... Figure 5 c. Figure 5 d、 Figure 5 e; Calculate the peak signal-to-noise ratio and structural similarity of the images processed by the three circuits. The results show that the median filtering circuit proposed in this invention can achieve the same computational accuracy as the former two.
[0050] The present invention also provides a filtering method using the median filter circuit based on random bitstream correlation described above, comprising: Based on a shared random number source, the random bit streams for comparison and module operations in the median filtering module are all positively correlated. A three-level sorting operation is used, namely column sorting, row sorting and diagonal sorting, and the final output is the random bit stream corresponding to the median value of the input data.
[0051] The present invention further provides an image in which the above-described filtering method is applied to eliminate impulse noise.
[0052] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.
[0053] The above embodiments are merely examples of implementation methods of the invention. The scope of protection of the present invention is not limited to the above embodiments. For those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention.
Claims
1. A median filter circuit based on the correlation of random bit streams, characterized in that, include: The median filtering module includes a comparison and exchange module. Based on a shared random number source, the random bit streams operated in the comparison and exchange modules are all positively correlated. A three-level sorting operation is used, namely column sorting, row sorting, and diagonal sorting. The final output is the random bit stream corresponding to the median value of the input data.
2. The median filtering circuit based on random bitstream correlation according to claim 1, characterized in that, The internal circuitry of the compare and exchange module includes multiple AND and OR logic gates; The minimum input value is obtained by using a multi-input AND gate; the comparison of two data paths in the multi-input AND gate is implemented as the first step to obtain the intermediate value; the results of all two-input AND gates are passed through a multi-input OR gate as the second step to obtain the final intermediate value. The maximum input value is obtained by using a multi-input logic gate OR.
3. The median filter circuit based on random bitstream correlation according to claim 1, characterized in that, The final output is a random bitstream corresponding to the intermediate values of the input data, including: Column sorting section: The bit stream corresponding to each column of data in the input window serves as the input to the same comparison and exchange module of the column sorting section. The output of the comparison and exchange module is the random bit stream corresponding to the sorted result of this column of data. Row sorting section: The random bit streams at the same sequence positions in the sorting outputs of the comparison and swapping modules in the column sorting section are used as the inputs of the same comparison and swapping module in the row sorting section. The outputs of the comparison and swapping modules in the row sorting section realize the row sorting based on the column sorting. Diagonal sorting section: Select data from the diagonal of the sorted window from the sorting output of the comparison and exchange module of the row sorting section. Group the data on each diagonal as a group and use it as the input of the same comparison and exchange module of the diagonal sorting section. The output is to obtain the intermediate value.
4. The median filter circuit based on random bitstream correlation according to claim 3, characterized in that, When a single-level diagonal sort cannot yield the intermediate value, the number of levels in the diagonal sort can be increased in the same way until the intermediate value is obtained.
5. The median filter circuit based on random bitstream correlation according to claim 1, characterized in that, The median filtering circuit includes a random number generator and a counter. The random number generator converts the data in the window into corresponding random bit streams with positive correlation. The median filtering module outputs the random bit stream corresponding to the median value of the window data. Finally, the counter counts the number of times 1 appears in the random bit stream, thereby converting the random bit stream back to the original data mode and realizing the median filtering function.
6. The median filter circuit based on random bitstream correlation according to claim 5, characterized in that, The random number generator includes a shared random number source and multiple comparators; the shift register in the random number source generates a random bit stream by feedback shifting after being given an initial seed bit stream; the random bit stream and the input window data are respectively used as inputs to multiple comparators, and by comparing the size of the input window data and the bit stream data, the comparator outputs a continuous but not fixed 0 / 1 sequence.
7. A filtering method using the median filter circuit based on random bitstream correlation as described in any one of claims 1-6, characterized in that, include: Based on a shared random number source, the random bit streams operated by the comparison and swapping modules in the median filtering module are all positively correlated. A three-level sorting operation is used, namely column sorting, row sorting and diagonal sorting, and the final output result is the random bit stream corresponding to the median value of the input data.
8. An image, characterized in that, The filtering method described in claim 7 is used to eliminate impulse noise.