Split-gate flash memory structure and forming method thereof
By forming source/drain trenches and source/drain doped regions below the floating gate structure of the gate-splitting flash memory cell, the crosstalk problem of the gate-splitting floating gate memory when the storage density is increased is solved, thereby improving storage performance and device reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-14
AI Technical Summary
The performance of existing segmented floating gate memories still needs to be improved, especially as storage density increases, the crosstalk caused by the reduced floating gate spacing between adjacent memory cells affects the storage performance of the device.
Source-drain trenches are formed below the floating gate structure of the gate-divided flash memory cell, and source-drain doped regions are formed in the substrate. The electron path length is increased by increasing the depth and length of the source-drain trenches. At the same time, a lightly doped region is formed below the source-drain trenches to reduce the electric field strength, reduce the generation and injection of hot carriers, and improve crosstalk.
By increasing the electron path length and reducing crosstalk between floating gates, storage performance and device integration are improved, while hot carrier generation is reduced, thus improving device reliability and read/write speed.
Smart Images
Figure CN121865624A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a gate-splitting flash memory structure and a method for forming the same. Background Technology
[0002] Floating gate splitting is a non-volatile memory technology mainly used in NOR flash memory and embedded flash memory. It physically decomposes the traditional single-transistor floating gate cell (such as the memory tube in Flash) into two series-connected and electrically independently coupled transistors. The two transistors can be used for information storage and are each other's selection transistors.
[0003] However, the performance of existing segmented floating gate memories still needs improvement. Summary of the Invention
[0004] The technical problem solved by this invention is how to improve the storage performance of storage devices.
[0005] To address the aforementioned technical problems, embodiments of the present invention provide a gate-splitting flash memory structure, comprising: a substrate, wherein the substrate has adjacent first gate-splitting flash memory cells and second gate-splitting flash memory cells; the first gate-splitting flash memory cells and the second gate-splitting flash memory cells share the same source-drain doped region; wherein each of the first gate-splitting flash memory cells and the second gate-splitting flash memory cells includes two memory bits, each memory bit including a floating gate structure; a source-drain trench is formed below the floating gate structure of adjacent memory bits of the first gate-splitting flash memory cells and the second gate-splitting flash memory cells, and the source-drain doped region is located within the substrate below the source-drain trench.
[0006] Optionally, the source / drain doped region includes: a heavily doped region located in the substrate below the source / drain trench; a first lightly doped region located on one side of the heavily doped region and below the floating gate structure of the first subdivided flash memory cell; and a second lightly doped region located on the other side of the heavily doped region and below the floating gate structure of the second subdivided flash memory cell.
[0007] Optionally, at least one of the first lightly doped region and the second lightly doped region has a doping concentration along the first direction that is greater than the doping concentration along the second direction, wherein the first direction is the channel direction and the second direction is perpendicular to the first direction.
[0008] Optionally, the gate-splitting flash memory structure further includes: sidewalls, the sidewalls being located on the sidewalls of the first gate-splitting flash memory cell and the second gate-splitting flash memory cell.
[0009] Optionally, the sidewall is at least partially located within the source / drain trench.
[0010] Accordingly, the present invention also provides a method for forming a gated flash memory structure, comprising: providing a substrate; forming adjacent first gated flash memory cells and second gated flash memory cells on the substrate; each of the first gated flash memory cells and the second gated flash memory cells includes two memory bits, each memory bit including a floating gate structure; forming source-drain trenches below the floating gate structures of adjacent memory bits of the first gated flash memory cells and the second gated flash memory cells; forming source-drain doped regions in the substrate below the source-drain trenches, wherein the first gated flash memory cells and the second gated flash memory cells share the same source-drain doped region.
[0011] Optionally, forming a source / drain doped region in the substrate below the source / drain trench includes: performing ion implantation on the substrate below the source / drain trench to form the source / drain doped region.
[0012] Optionally, ion implantation is performed on the substrate below the source / drain trench to form the source / drain doped region, including: performing a first ion implantation on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region; and performing a second ion implantation on the bottom surface of the trench to form a heavily doped region.
[0013] Optionally, the first ion implantation on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region includes: tilting ion implantation on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region.
[0014] Optionally, the concentration of tilted ion implantation on the first and second sidewall surfaces of the source-drain trench distributed along the first direction is greater than the concentration of tilted ion implantation on the third and fourth sidewall surfaces of the source-drain trench distributed along the second direction, wherein the first direction is the channel direction and the second direction is perpendicular to the first direction.
[0015] Optionally, a source-drain trench is formed below the floating gate structure of adjacent memory bits of the first and second gate flash memory cells, including: using the mask forming the first and second gate flash memory cells as a mask, etching the substrate between the first and second gate flash memory cells to form the source-drain trench.
[0016] Optionally, the method for forming the gated flash memory structure further includes: after forming the source-drain trench, forming a sidewall, wherein the sidewall is at least partially located within the source-drain trench.
[0017] Optionally, forming a source / drain doped region in the substrate below the source / drain trench includes: after forming the sidewall, using the sidewall as a mask to form the source / drain doped region.
[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0019] In this invention, by forming source-drain trenches below the floating gate structures of adjacent memory bits in the first and second gate flash memory cells, and forming source-drain doped regions in the substrate below the source-drain trenches, the electronic path length between adjacent gate flash memory cells is no longer limited by the substrate surface between them, but is determined by both the depth and length of the source-drain trenches. Thus, increasing the depth of the source-drain trenches increases the electronic path length between adjacent floating gates of adjacent gate flash memory cells, reduces crosstalk between adjacent floating gates, and improves the device's storage performance. Furthermore, with the same electronic path length, the channels formed below the source-drain trenches can reduce the spacing between adjacent floating gates, thereby improving the device's integration density.
[0020] Furthermore, when forming the source / drain doped regions, by forming a first lightly doped region and a second lightly doped region on both sides of the heavily doped region, the surface electric field strength of the source / drain trench can be reduced, the generation and injection of hot carriers can be reduced, and the crosstalk between adjacent floating gates can be further reduced. In addition, the lightly doped region can also reduce the peak electric field near the source / drain doped region and improve the reliability of the device.
[0021] Furthermore, when performing tilted ion implantation to form the first lightly doped region and the second lightly doped region, by changing the substrate rotation from four times to two times, the doping concentration of at least one of the first lightly doped region and the second lightly doped region along the first direction is greater than the doping concentration along the second direction. This avoids the implantation shadowing effect on the sidewalls of the source / drain trench in the direction perpendicular to the channel, thereby increasing the doping concentration of the sidewalls of the source / drain trench (i.e., the first and second doped regions) and the doping concentration between the channel and the floating gate structure connection under the same implantation dose. This reduces crosstalk between adjacent floating gates, increases read current, improves read / write speed, and improves the storage performance of the device. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a multi-gate flash memory structure;
[0023] Figures 2 to 9 This is a schematic diagram illustrating the formation process of a gate-splitting flash memory structure in one embodiment of the present invention;
[0024] Figure 10 This is a schematic diagram of the doping concentration distribution curves at different positions along the channel direction on the same gate flash memory cell;
[0025] Figure 11 A schematic diagram showing the decay rate of the nearest neighbor current for different gate-type flash memory cells.
[0026] Figure 12 This is a scatter plot showing the change of erase current as a function of erase threshold voltage for the same gate flash memory cell, with the X-axis representing the erase threshold voltage.
[0027] Figure 13 This is a scatter plot showing the change in write current as a function of write threshold voltage for the same gate flash memory cell. Detailed Implementation
[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0029] Currently, for multi-gate floating gate devices, as storage density increases, the spacing between floating gates of adjacent memory cells decreases, leading to crosstalk between adjacent floating gates and affecting the device's storage performance. The reasons for this deficiency are analyzed below:
[0030] Figure 1 This is a schematic diagram of a memory structure. (Reference) Figure 1 The memory structure includes: a substrate 100 having a plurality of arrayed gate flash memory cells on the substrate 100, and source / drain doped regions 103 located on the surface of the substrate 100 between adjacent gate flash memory cells.
[0031] The bit line length of the gate flash memory cell is the length of the source / drain doped region 103, and the length refers to the dimension in the direction parallel to the substrate 100.
[0032] The gated flash memory unit includes a first gated flash memory unit 101 and a second gated flash memory unit 102.
[0033] As storage density increases, the bit line length of the segmented flash memory cell decreases. When programming the selected first segmented flash memory cell 101, the adjacent second segmented flash memory cell 102 will be severely affected by crosstalk. Specifically, as the number of programming cycles for the first segmented flash memory cell 101 increases, more electrons enter the floating gate of the second segmented flash memory cell 102, which was originally in the erase state, resulting in a decrease in read current, a change in storage state, and device failure.
[0034] To address the aforementioned technical problems, this invention provides a gate-splitting flash memory structure and a method for forming the same, comprising: a substrate having adjacent first gate-splitting flash memory cells and second gate-splitting flash memory cells on the substrate; the first gate-splitting flash memory cells and the second gate-splitting flash memory cells sharing the same source / drain doped region; wherein each of the first gate-splitting flash memory cells and the second gate-splitting flash memory cells includes two memory bits, each memory bit including a floating gate structure; a source / drain trench is formed below the floating gate structure of adjacent memory bits of the first gate-splitting flash memory cells and the second gate-splitting flash memory cells, and the source / drain doped region is located within the substrate below the source / drain trench.
[0035] The source / drain trench is located below the floating gate structure of adjacent memory bits in the first and second gated flash memory cells, and the source / drain doped region is located in the substrate below the source / drain trench. The depth and length of the source / drain trench determine the electronic path length between adjacent gated flash memory cells. Therefore, by increasing the depth of the source / drain trench, the electronic path length between adjacent floating gates of adjacent gated flash memory cells can be increased, thereby reducing crosstalk between adjacent floating gates of adjacent gated flash memory cells and improving the storage performance of the device.
[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0037] refer to Figures 2 to 9 The diagram shows structural schematics of various steps in some embodiments of the method for forming a gated flash memory structure according to the present invention.
[0038] The forming method includes: providing a substrate 200; forming a floating gate dielectric material layer 2071 on the substrate 200; forming a floating gate material layer 2011 on the floating gate dielectric material layer 2071; forming a control gate dielectric material layer 2021 on the floating gate material layer 2011; forming a control gate material layer 2031 on the control gate dielectric material layer 2021; forming a mask layer 204 on the control gate material layer 2031; and forming a first sidewall 205 on the sidewall of the mask layer 204.
[0039] In some embodiments of the present invention, the substrate 200 may be made of silicon.
[0040] In other embodiments, the substrate 200 may be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 may be a silicon substrate on an insulator or a germanium substrate on an insulator.
[0041] For example, the substrate 200 includes a first active region I and a second active region II, wherein the first active region I is subsequently used to form a first gate flash memory cell, and the second active region II is subsequently used to form a second gate flash memory cell.
[0042] The floating gate dielectric material layer 2071 is used to provide a structural foundation for subsequent floating gate dielectric layers.
[0043] The floating grid material layer 2011 is used to provide a structural foundation for the subsequent floating grid structure.
[0044] The control gate dielectric material layer 2021 is used to provide a structural foundation for subsequent control gate dielectric layers.
[0045] The control gate material layer 2031 is used to provide a structural foundation for the subsequent control gate structure.
[0046] In some embodiments, the mask layer 204 has a first opening (not shown) that exposes the surface of the control gate material layer 2031.
[0047] The first opening is used to define the dimensions of the subsequently formed floating gate structure 201, control gate structure 203, and word line structure.
[0048] The dimension refers to the dimension in a first direction X, which is parallel to the surface of the substrate 200.
[0049] For example, the step of forming a first opening in the mask layer 204 includes: forming a mask material layer on the control gate material layer 2031; forming a first pattern layer (not shown) on the mask material layer; and etching the mask material layer using the first pattern layer as a mask to expose the surface of the control gate material layer 2031 to form a mask layer 204 with the first opening.
[0050] The first patterning layer is used to pattern the mask material layer to define the location of the first opening. The mask layer 204 can be a hard mask layer. The material of the mask layer 204 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and titanium nitride.
[0051] A second opening (not shown) is provided between adjacent first sidewalls 205. The second opening defines the dimensions of the subsequently formed word line structure, and the first sidewalls 205 define the dimensions of the subsequently formed control gate structure. The dimensions refer to the dimensions in a first direction X, which is parallel to the surface of the substrate 200.
[0052] In some embodiments, the floating gate dielectric material layer 2071 is formed using a thermal oxidation growth process, and the material of the floating gate dielectric material layer 2071 is silicon oxide.
[0053] In some embodiments, the floating gate material layer 2011, the control gate dielectric material layer 2021, the control gate material layer 2031, the mask layer 204, and the first sidewall 205 may be formed using chemical vapor deposition or physical vapor deposition processes.
[0054] Specifically, the floating gate material layer 2011 and the control gate material layer 2031 are made of polysilicon, the control gate dielectric material layer 2021 includes silicon oxide and silicon nitride, and the first sidewall 205 is made of silicon oxide.
[0055] The control gate dielectric material layer 2021 has an "ONO" structure.
[0056] In some embodiments, after the mask layer 204 is formed and before the first sidewall 205 is formed, ion implantation is performed on the substrate 200 using the mask layer 204 as a mask to form a first doped region 206.
[0057] The first doped region 206 is located between the subsequently formed source and drain doped regions, and the doping type of the first doped region 206 is the same as that of the substrate 200.
[0058] In some embodiments of the present invention, the first doped region 206 is a P-type doped region.
[0059] The first doped region 206 effectively suppresses the source-drain doped region punch-through effect that may occur due to the shortening of the channel length, ensuring the normal shutdown of the gate-dimming flash memory structure. Simultaneously, by precisely controlling its doping concentration and distribution, the initial threshold voltage of the gate-dimming flash memory structure can be set, providing a stable and reliable reference window for subsequent programming and erasing operations, thereby ensuring the reliability and performance of the entire gate-dimming flash memory cell.
[0060] refer to Figure 3 An adjacent first gate flash memory cell and a second gate flash memory cell are formed on the substrate 200; each of the first gate flash memory cell and the second gate flash memory cell includes two memory bits, and each memory bit includes a floating gate structure.
[0061] The first and second gated flash memory cells have the same structure and the same formation process.
[0062] For example, the steps of forming adjacent first and second gate flash memory cells include: using a mask layer 204 and a first sidewall 205 as masks, etching the control gate material layer 2031 and the control gate dielectric material layer 2021 to expose the surface of the floating gate material layer 2011; forming a second sidewall 208 on a portion of the sidewall surface of the first sidewall 205, the sidewall surface of the control gate material layer 2031, the sidewall surface of the control gate dielectric material layer 2021, and a portion of the surface of the floating gate material layer 2011; and using the mask layer 204, the first sidewall 205, and the second sidewall 208 as masks, etching the floating gate material layer 2011 to expose the surface of the floating gate dielectric material layer 2071.
[0063] For example, the floating gate material layer 2011 and the control gate dielectric material layer 2021 located on the first active region I constitute a first segmented flash memory cell, and the floating gate material layer 2011 and the control gate dielectric material layer 2021 located on the second active region II constitute a second segmented flash memory cell. The two storage bits in the first segmented flash memory cell refer to two separate floating gate material layers 2011 located at the bottom of the first sidewall 205 on the first active region I, and the two storage bits in the second segmented flash memory cell refer to two separate floating gate material layers 2011 located at the bottom of the first sidewall 205 on the first active region I.
[0064] Wherein, a storage bit in the first gate flash memory cell refers to either of the two discrete floating gate material layers 2011 in the first gate flash memory cell, and a storage bit in the second gate flash memory cell refers to either of the two discrete floating gate material layers 2011 in the second gate flash memory cell.
[0065] In some embodiments, the control gate material layer 2031, the control gate dielectric material layer 2021, and the floating gate material layer 2011 are etched using dry etching or wet etching methods.
[0066] There is a third opening (not shown in the figure) between adjacent second sidewalls 208.
[0067] The third opening is used to define the dimensions of the subsequently formed letter line structure, and the second sidewall 208 is used to define the dimensions of the subsequently formed floating grid structure 201.
[0068] The dimension refers to the dimension in a first direction X, which is parallel to the surface of the substrate 200.
[0069] In some embodiments, the second sidewall 208 is formed using a chemical vapor deposition process or a physical vapor deposition process.
[0070] The material of the second sidewall 208 is silicon oxide.
[0071] refer to Figure 4 A word line grid dielectric layer 209 is formed on the sidewall surface of a portion of the first sidewall 205, the sidewall surface of the first sidewall 205, the sidewall surface of the floating grid material layer 2011, and the surface of the floating grid dielectric material layer 2071; a word line grid structure 210 is formed by filling the third opening.
[0072] The word line gate structure 210 is used as a word line in the entire memory array of the gated flash memory structure.
[0073] The word line gate structure 210 is made of polycrystalline silicon, and the word line gate dielectric layer 209 is made of silicon oxide.
[0074] In some embodiments, the word line grid structure 210 and the word line grid dielectric layer 209 are formed using a chemical vapor deposition process or a physical vapor deposition process.
[0075] refer to Figure 5 Source-drain trenches 212 are formed below the floating gate structure 201 of adjacent memory bits of the first and second gate flash memory cells.
[0076] For example, in the step of forming the source-drain trench 212, a protective layer 211 is formed on top of the word line gate structure 210 and on top of the word line gate dielectric layer 209; the mask layer is removed to expose the control gate material layer 2031; using the protective layer 211 and the first sidewall 205 as a mask, the control gate material layer 2031, the control gate dielectric material layer 2021, the floating gate material layer 2011, the floating gate dielectric material layer 2071, and a portion of the substrate 200 are removed to form the control gate structure 203, the control gate dielectric layer 202, the floating gate structure 201, the floating gate dielectric layer 207, and the source-drain trench 212.
[0077] Specifically, the floating gate structure 201 in the first segmented flash memory cell formed behind the mask layer includes: a first storage bit 2181 and a second storage bit 2182, and the floating gate structure 201 in the second segmented flash memory cell includes: a third storage bit 2183 and a fourth storage bit 2184.
[0078] The source / drain trench 212 is located within the substrate between the second memory bit 2182 and the third memory bit 2183. In a projection direction perpendicular to the substrate surface, the sidewalls of the source / drain trench 212 may extend into the substrate below the second memory bit 2182 and into the substrate below the third memory bit 2183, but the sidewalls of the source / drain trench 212 do not exceed the projection range of the second memory bit 2182 and the third memory bit 2183.
[0079] In an embodiment of the present invention, in a projection direction perpendicular to the substrate surface, the sidewall of the source / drain trench 212 is flush with the edge of the second memory bit 2182 or the third memory bit 2183.
[0080] For example, the cross-sectional shape of the source-drain trench 212 is rectangular, and the corners of the rectangle can also be rounded, which can increase the implantation area during subsequent ion implantation and improve the uniformity of implantation.
[0081] The floating gate structure 201 is used to store data, the floating gate dielectric layer 207 is used to form isolation between the channel and the floating gate structure 201, the control gate structure 203 is used to apply different voltages to control the read, write and erase operations on the floating gate structure 201, and the control gate dielectric layer 202 is used to form isolation between the floating gate structure 201 and the control gate structure 203.
[0082] The source / drain trench 212 provides a structural basis for forming subsequent source / drain doped regions.
[0083] Specifically, the depth of the source / drain trench 212 ranges from 0 nanometers to 50 nanometers.
[0084] refer to Figure 6 , Figure 6 yes Figure 5 The top view of the structure shows that the source-drain trench 212 includes a first sidewall 2121 and a second sidewall 2122 distributed along the first direction X, and a third sidewall 2123 and a fourth sidewall 2124 distributed along the second direction Y.
[0085] refer to Figures 7 to 9 A source / drain doped region is formed in the substrate 200 below the source / drain trench 212, and the first gate flash memory cell and the second gate flash memory cell share the same source / drain doped region.
[0086] In some embodiments, forming a source / drain doped region in the substrate 200 below the source / drain trench 212 includes: performing ion implantation on the substrate 200 below the source / drain trench 212 to form the source / drain doped region.
[0087] like Figure 7 as well as Figure 8 As shown, in the step of forming the source / drain doped region, ion implantation is performed on the substrate 200 below the source / drain trench 212 to form the source / drain doped region, including: performing a first ion implantation on the sidewall surface of the source / drain trench 212 to form a first lightly doped region 213 and a second lightly doped region; forming a sidewall 214, the sidewall 214 being at least partially located within the source / drain trench 212; as shown Figure 8As shown, using the sidewall 214 as a mask, a second ion implantation is performed on the surface of the bottom 2151 of the trench to form a heavily doped region 215.
[0088] The side wall 214 has an "L" shaped structure.
[0089] like Figure 9 As shown, Figure 9 yes Figure 8 A top-down view, in which, Figure 9 The sidewall structure and part of the protective layer 211 are omitted to show a first lightly doped region 2131, a second lightly doped region 2132, and a heavily doped region 215. The first lightly doped region 2131 is located on the surface of the first sidewall 2121, and the second lightly doped region 2132 is located on the surface of the second sidewall 2122. The first lightly doped region 2131 and the second lightly doped region 2132 are used to form electronic paths between adjacent first and second gate flash memory cells.
[0090] When forming the source / drain doped regions, by forming a first lightly doped region 2131 and a second lightly doped region 2132 on both sides of the heavily doped region, the surface electric field intensity of the source / drain trench 212 can be reduced, the generation and injection of hot carriers can be reduced, and the crosstalk between adjacent floating gates can be further reduced. In addition, the lightly doped regions can also reduce the peak electric field near the source / drain doped regions and improve the reliability of the device.
[0091] In some embodiments, in the steps of forming the first lightly doped region 2131 and the second lightly doped region 2132, four angled first ion implantations are performed on the surfaces of the first sidewall 2121, the second sidewall 2122, the third sidewall 2123, and the fourth sidewall 2124, respectively, to form the corresponding first lightly doped region, second lightly doped region, third lightly doped region, and fourth lightly doped region. The tilt angle of the first ion implantation can range from 5 degrees to 25 degrees, for example, 10 degrees. The substrate rotation angle during the first ion implantation is 45 degrees, and the implantation concentration range is 1.0e14 atom / cm². 2 Up to 3.0e14 atom / cm 2 For example, 1.8e14 atom / cm 2 .
[0092] Here, the substrate rotation angle refers to the angle relative to a specific Norch crystal orientation (e.g., <110> The rotation angle of ).
[0093] In other embodiments, during the steps of forming the first lightly doped region 2121 and the second lightly doped region 2122, reference is made to... Figure 9The first sidewall 2121 and the second sidewall 2122 can be implanted with first ions at an angle twice, but the third sidewall 2123 and the fourth sidewall 2124 are not implanted with first ions, forming a first lightly doped region 2131 on the surface of the first sidewall 2121 and a second lightly doped region 2132 on the surface of the second sidewall 2122. The tilt angle of the first ion implantation can be from 5 degrees to 25 degrees, for example, 10 degrees, and the substrate rotation angle is 90 degrees during the first ion implantation. The implantation concentration of the first ion implantation is 1.0e14 atom / cm³. 2 Up to 3.0e14 atom / cm 2 For example, 1.8e14 atom / cm 2 .
[0094] Here, the substrate rotation angle refers to the angle relative to a specific Norch crystal orientation (e.g., <110> The rotation angle of ).
[0095] This allows the doping concentration on the surface of the first sidewall 2121 and the second sidewall 2122 to be greater than the doping concentration on the surface of the third sidewall 2123 and the fourth sidewall 2124, thereby increasing the doping concentration at the connection between the channel and the floating gate structure 201, reducing crosstalk between adjacent floating gates, and improving the storage performance of the device.
[0096] refer to Figure 10 , Figure 10 This is a schematic diagram of the doping concentration distribution curves at different positions along the channel direction (i.e., the first direction) on the same gate flash memory cell. The X-axis represents the distribution at different positions on the gate flash memory cell, the Y-axis represents the doping concentration, and the two edges of the X-axis represent the positions where the source / drain doped regions and the first doped region 206 are connected (i.e., the positions where the PN junction is located). L1 represents the doping concentration distribution curve at different positions on the gate flash memory cell of the passive drain trench 212, L2 represents the doping concentration distribution curve at different positions on the gate flash memory cell of the active drain trench 212 after four first ion implantations, and L3 represents the doping concentration distribution curve at different positions on the gate flash memory cell of the active drain trench 212 after two first ion implantations.
[0097] Depend on Figure 10It can be seen that at the location where the source / drain doped region and the first doped region 206 are connected, the L3 curve (specifically, the part of the L3 curve near the PN junction sidewall) is generally higher than the L2 curve and the L1 curve. That is, the doping concentration at the connection between the source / drain doped region and the first doped region 206 formed by two first ion implantations is greater than the doping concentration at the connection between the source / drain doped region and the first doped region 206 formed by four first ion implantations, as well as the doping concentration at the connection between the source / drain doped region and the first doped region 206 in the gate-divided flash memory cell of the passive drain trench 212. Therefore, forming the source / drain doped region by two first ion implantations can increase the doping concentration between the channel and the floating gate structure 201, increase the read current, improve the device read speed, and improve the device's storage performance.
[0098] Continue to refer to Figure 8 Before forming the heavily doped region 215, a sidewall 214 is formed, the sidewall 214 being at least partially located within the source / drain trench 212; the sidewall 214 is used as a mask to form the heavily doped region 215.
[0099] The sidewall 214 is located on the sidewalls of the first and second gate flash memory cells, as well as on the sidewalls and part of the bottom surface of the source-drain trench 212.
[0100] In some embodiments, the sidewall 214 is formed using a chemical vapor deposition process or a physical vapor deposition process.
[0101] Specifically, the sidewall 214 is made of silicon oxide and silicon nitride, wherein the sidewall 214 has an "ONO" structure.
[0102] In some embodiments, the angle of the first ion implantation is greater than the implantation angle of the second ion, and the implantation concentration of the first ion implantation is less than the implantation concentration of the second ion implantation. The tilt angle of the second ion implantation can range from 0 degrees to 10 degrees, for example, 0 degrees. The implantation concentration of the second ion ranges from 1.8e15 atom / cm². 2 Up to 5.8e15 atom / cm 2 For example, 3.8e15 atom / cm 2 .
[0103] By forming source-drain trenches 212 below the floating gate structures 201 of adjacent memory bits in the first and second gate flash memory cells, and forming source-drain doped regions in the substrate 200 below the source-drain trenches 212, the electronic path length between adjacent gate flash memory cells is no longer limited by the surface of the substrate 200 between adjacent gate flash memory cells, but is determined by both the depth and length of the source-drain trenches 212. Thus, increasing the depth of the source-drain trenches 212 increases the electronic path length between adjacent floating gates of adjacent gate flash memory cells, reduces crosstalk between adjacent floating gates of adjacent gate flash memory cells, and improves the storage performance of the device. Furthermore, with the same electronic path length, the channel formed below the source-drain trenches 212 can reduce the spacing between adjacent floating gates, thereby improving the device's integration density.
[0104] In some embodiments, the degree of crosstalk between adjacent first and second gate flash memory cells is detected by testing the attenuation ratio of the nearest neighbor 1 current of different gate flash memory cells.
[0105] Specifically, by labeling the nine different gate flash memory cells on the gate flash memory structure with different identifiers, such as identifiers 1-9, the nearest neighbor current of the gate flash memory cells with different identifiers is measured.
[0106] Here, the nearest neighbor current refers to the current interference generated on the nearest gate flash memory cell, for example, referring to... Figure 8 When writing to the first gate flash memory cell on the first active region, the current on the second gate flash memory cell on the second active region in the erasure state is measured, and the current is the nearest neighbor 1 current.
[0107] The attenuation ratio of the nearest neighbor 1 current is directly proportional to the degree of crosstalk; that is, the smaller the attenuation ratio of the nearest neighbor 1 current, the smaller the degree of crosstalk between the adjacent first gate flash memory cell and the second gate flash memory cell.
[0108] refer to Figure 11 , Figure 11 This diagram illustrates the decay rate of the nearest neighbor 1 current for different gate-type flash memory cells. The X-axis represents the identifier of the different gate-type flash memory cells, the Y-axis represents the decay rate of the nearest neighbor 1 current, and the N1 curve is shown below. Figure 1 The curves shown represent the decay rate of the nearest neighbor 1 current for different gate-type flash memory cells. The N2 curve is as follows: Figure 8 The curves showing the decay ratio of the nearest neighbor current for different gate flash memory cells are shown.
[0109] Depend on Figure 11As can be seen, for the same gate-type flash memory cell, the attenuation ratio of the nearest neighbor 1 current on the N1 curve is greater than that on the N2 curve. For example, for the gate-type flash memory cell labeled 6, the attenuation ratio of the nearest neighbor 1 current on the N1 curve is 19%, while that on the N2 curve is 5%. Therefore, forming source-drain doped regions within the source-drain trench 212 can increase the electron path length between adjacent floating gates of adjacent gate-type flash memory cells, reduce crosstalk between adjacent floating gates of adjacent gate-type flash memory cells, and improve the storage performance of the device.
[0110] Figure 12 This is a scatter plot illustrating the change in erase current as a function of erase threshold voltage for the same gated flash memory cell. The X-axis represents the erase threshold voltage, and the Y-axis represents the erase current. The red scatter points represent... Figure 1 The image shows a scatter plot of the erase current within a gated flash memory cell as a function of the erase threshold voltage. The green scatter plot represents... Figure 8 The scatter plot shows the change of erase current within a gated flash memory cell as a function of the erase threshold voltage.
[0111] Figure 13 This is a scatter plot illustrating the change in write current as a function of write threshold voltage for the same gate flash memory cell. The X-axis represents the write threshold voltage, and the Y-axis represents the write current. The red scatter points represent... Figure 1 The graph shows the write current within a gated flash memory cell as a function of the write threshold voltage. The green dots represent... Figure 8 The scatter plot shows the write current within a gated flash memory cell as a function of the write threshold voltage.
[0112] refer to Figure 12 and Figure 13 , Figure 1 and Figure 8 The scatter plot trends of the erase current within the gated flash memory cell as a function of the erase threshold voltage are basically the same. Figure 1 and Figure 8 The scatter plot trends of the write current in the gated flash memory cell with the write threshold voltage are basically the same, which shows that the gated flash memory cell with source-drain trench 212 can maintain the current storage performance while reducing crosstalk.
[0113] Accordingly, refer to Figure 8The present invention also provides a gate-splitting flash memory structure, comprising: a substrate 200 having adjacent first gate-splitting flash memory cells and second gate-splitting flash memory cells on the substrate 200; the first gate-splitting flash memory cells and the second gate-splitting flash memory cells sharing the same source-drain doped region; wherein, the first gate-splitting flash memory cells and the second gate-splitting flash memory cells each include two memory bits, each memory bit including a floating gate structure 201; a source-drain trench 212 is formed below the floating gate structure 201 of adjacent memory bits of the first gate-splitting flash memory cells and the second gate-splitting flash memory cells, and the source-drain doped region is located in the substrate 200 below the source-drain trench 212.
[0114] In some embodiments, the source / drain doped regions include: a heavily doped region 215 located within the substrate 200 below the source / drain trench 212; a first lightly doped region 2131 located on one side of the heavily doped region 215 and below the floating gate structure 201 of the first subdivided flash memory cell; and a second lightly doped region 2132 located on the other side of the heavily doped region 215 and below the floating gate structure 201 of the second subdivided flash memory cell.
[0115] In some embodiments, at least one of the first lightly doped region 2131 and the second lightly doped region 2132 has a doping concentration along the first direction X that is greater than the doping concentration along the second direction Y, wherein the first direction X is the channel direction and the second direction Y is perpendicular to the first direction X.
[0116] Specifically, when implanting the first lightly doped region 2131 and the second lightly doped region 2132, the conventional method of rotating the substrate four times is changed to rotating the substrate twice, and implantation is performed from the channel direction (i.e., the first direction). This can avoid the implantation shadowing effect generated by the sidewalls of the source / drain trench in the direction perpendicular to the channel direction (i.e., the second direction), and increase the doping concentration of the first lightly doped region and the second lightly doped region under the same implantation dose.
[0117] In some embodiments, the device further includes a sidewall 214 located on the sidewall of the first gate flash memory cell and the second gate flash memory cell.
[0118] In some embodiments, the sidewall 214 is at least partially located within the source drain trench 212.
[0119] In summary, the source-drain trench is located below the floating gate structure of adjacent memory bits in the first and second gated flash memory cells, and the source-drain doped region is located in the substrate below the source-drain trench. The depth and length of the source-drain trench determine the electronic path length between adjacent gated flash memory cells. Therefore, by increasing the depth of the source-drain trench, the electronic path length between adjacent floating gates of adjacent gated flash memory cells can be increased, thereby reducing crosstalk between adjacent floating gates of adjacent gated flash memory cells and improving the storage performance of the device.
[0120] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A gate-splitting flash memory structure, characterized in that, include: A substrate having adjacent first-gate flash memory cells and second-gate flash memory cells; the first-gate flash memory cells and the second-gate flash memory cells share the same source and drain doped region; The first and second gated flash memory units each include two memory bits, and each memory bit includes a floating gate structure. A source / drain trench is formed below the floating gate structure of adjacent memory bits in the first and second gated flash memory units, and the source / drain doped region is located in the substrate below the source / drain trench.
2. The gate-splitting flash memory structure as described in claim 1, characterized in that, The source / drain doped regions include: The heavily doped region is located within the substrate below the source / drain trench; The first lightly doped region is located on one side of the heavily doped region and below the floating gate structure of the first gate flash memory cell; And a second lightly doped region, located on the other side of the heavily doped region, and below the floating gate structure of the second gate flash memory cell.
3. The gate-splitting flash memory structure as described in claim 2, characterized in that, At least one of the first lightly doped region and the second lightly doped region has a doping concentration along the first direction that is greater than the doping concentration along the second direction, wherein the first direction is the channel direction and the second direction is perpendicular to the first direction.
4. The gate-splitting flash memory structure as described in claim 1, characterized in that, Also includes: Sidewalls, which are located on the sidewalls of the first and second gated flash memory cells.
5. The gate-splitting flash memory structure as described in claim 4, characterized in that, The sidewall is at least partially located within the source / drain trench.
6. A method for forming a multi-gate flash memory structure, characterized in that, include: Provide substrate; Adjacent first-gate flash memory cells and second-gate flash memory cells are formed on a substrate; each of the first-gate flash memory cells and the second-gate flash memory cells includes two memory bits, and each memory bit includes a floating gate structure; Source-drain trenches are formed below the floating gate structure of adjacent memory bits in the first and second segmented flash memory cells; A source / drain doped region is formed in the substrate below the source / drain trench, and the first and second gate flash memory cells share the same source / drain doped region.
7. The method for forming a multi-gate flash memory structure as described in claim 6, characterized in that, A source / drain doped region is formed in the substrate below the source / drain trench, including: Ion implantation is performed on the substrate below the source / drain trench to form the source / drain doped region.
8. The method for forming a multi-gate flash memory structure as described in claim 7, characterized in that, Ion implantation is performed on the substrate below the source / drain trench to form the source / drain doped region, including: A first ion implantation is performed on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region; A second ion implantation is performed on the bottom surface of the trench to form a heavily doped region.
9. The method for forming a multi-gate flash memory structure as described in claim 8, characterized in that, The first ion implantation on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region includes: Inclined ion implantation is performed on the sidewall surface of the source / drain trench to form a first lightly doped region and a second lightly doped region.
10. The method for forming a multi-gate flash memory structure as described in claim 9, characterized in that, The concentration of tilted ion implantation on the first and second sidewall surfaces of the source-drain trench distributed along the first direction is greater than the concentration of tilted ion implantation on the third and fourth sidewall surfaces of the source-drain trench distributed along the second direction, wherein the first direction is the channel direction and the second direction is perpendicular to the first direction.
11. The method for forming a multi-gate flash memory structure as described in claim 6, characterized in that, A source-drain trench is formed below the floating gate structure of adjacent memory bits in the first and second segmented flash memory cells, including: Using the mask forming the first gate flash memory cell and the second gate flash memory cell as a mask, the substrate between the first gate flash memory cell and the second gate flash memory cell is etched to form the source-drain trench.
12. The method for forming a multi-gate flash memory structure as described in claim 6, characterized in that, Also includes: After the source-drain trench is formed, a sidewall is formed, and the sidewall is at least partially located within the source-drain trench.
13. The method for forming a multi-gate flash memory structure as described in claim 12, characterized in that, A source / drain doped region is formed in the substrate below the source / drain trench, including: After the sidewalls are formed, the source and drain doped regions are formed using the sidewalls as masks.