Preparation method of semiconductor structure
By first forming a first low-k dielectric layer, then forming the top electrode, and finally covering it with a second low-k dielectric layer, the problem of void defects in oxygen vacancy devices is solved, and the device performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-14
Smart Images
Figure CN121865629A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure. Background Technology
[0002] Oxygen vacancy devices are a class of electronic devices that utilize the generation, migration, and annihilation of oxygen vacancies in a material to control its electrical properties (primarily resistance). The core principle is to precisely control the concentration and distribution of oxygen vacancies in the material through external electrical excitation (such as voltage), thereby achieving reversible switching between high-resistivity and low-resistivity states. The most typical and widely used oxygen vacancy device is resistive random access memory (RRAM or ReRAM).
[0003] Oxygen-vacancy devices typically consist of a lower electrode, an oxygen-vacancy resistive switching layer on the lower electrode, and an upper electrode on the oxygen-vacancy resistive switching layer. However, in the current fabrication process of oxygen-vacancy devices, after forming the upper electrode, during the formation of the low-k dielectric layer covering the upper electrode, void defects are easily generated in the low-k dielectric layer filling the spaces between adjacent upper electrodes due to the poor pore-filling ability of the low-k dielectric layer, thus affecting the performance of the oxygen-vacancy device. Summary of the Invention
[0004] Based on this, this application provides a method for fabricating a semiconductor structure to prevent the formation of void defects in the first low-k dielectric layer and the second low-k dielectric layer, thereby improving the performance of the device.
[0005] This application provides a method for fabricating a semiconductor structure, including:
[0006] A substrate is provided, in which a lower electrode is present;
[0007] An oxygen vacancy resistive switching layer is formed on the lower electrode;
[0008] A first low-k dielectric layer covering an oxygen vacancy resistive switching layer is formed on the substrate;
[0009] An opening is formed in the first low-k dielectric layer to expose the top surface of the oxygen vacancy resistive switching layer;
[0010] An upper electrode is formed in the opening;
[0011] A second low-k dielectric layer covering the top electrode is formed on the first low-k dielectric layer;
[0012] An upper contact plug electrically connected to the upper electrode is formed in the second low-k dielectric layer.
[0013] In some embodiments of this application, the first low-k dielectric layer and the second low-k dielectric layer are made of the same material.
[0014] In some embodiments of this application, the dielectric constant of the first low-k dielectric layer and the second low-k dielectric layer is less than or equal to 3.
[0015] In some embodiments of this application, the formation process of the oxygen vacancy resistive switching layer includes:
[0016] An oxygen vacancy resistive switching material layer is formed on the substrate;
[0017] A patterned mask layer is formed on the oxygen vacancy resistive switching material layer;
[0018] Using a patterned mask layer as a mask, an oxygen vacancy resistive switching material layer is etched to form an oxygen vacancy resistive switching layer.
[0019] In some embodiments of this application, the formation process of the upper electrode includes: forming an upper electrode material layer on a first low-k dielectric layer, wherein the upper electrode material layer fills the opening;
[0020] The upper electrode material layer outside the opening is removed by etching back, and the upper electrode is formed in the opening.
[0021] In some embodiments of this application, the substrate includes a substrate and multiple dielectric layers located on the substrate, with the lower electrode located in the uppermost dielectric layer.
[0022] In some embodiments of this application, the substrate further includes a lower contact plug and a first contact plug. The lower contact plug is located in the dielectric layer below the lower electrode and is electrically connected to the lower electrode. The first contact plug is located on one side of the lower contact plug.
[0023] A CMOS device is formed in or on the substrate, and the first contact plug is electrically connected to the CMOS device.
[0024] In some embodiments of this application, while an upper contact plug electrically connected to the upper electrode is formed in the second low-K dielectric layer, a second contact plug electrically connected to the first contact plug is formed in both the second low-K dielectric layer and the first low-K dielectric layer.
[0025] In some embodiments of this application, the thickness of the first low-k dielectric layer is 400-500 angstroms;
[0026] The thickness of the second low-K dielectric layer is 1100-1300 angstroms.
[0027] In some embodiments of this application, the thickness of the oxygen vacancy resistive switching layer is 35 angstroms to 60 angstroms;
[0028] Materials for oxygen vacancy resistive switching layers include HfO2 and TaO. X TiO2, ZrO2 or NiO.
[0029] The embodiments of this application may have, or at least have, the following advantages:
[0030] The semiconductor structure fabrication method in this application embodiment provides a substrate having a lower electrode; an oxygen vacancy resistive switching layer is formed on the lower electrode; a first low-k dielectric layer covering the oxygen vacancy resistive switching layer is formed on the substrate; an opening exposing the top surface of the oxygen vacancy resistive switching layer is formed in the first low-k dielectric layer; an upper electrode is formed in the opening; a second low-k dielectric layer covering the upper electrode is formed on the first low-k dielectric layer; and an upper contact plug electrically connected to the upper electrode is formed in the second low-k dielectric layer. In this application, the low-k dielectric layer covering the upper electrode includes a first low-k dielectric layer and a second low-k dielectric layer located on the first low-k dielectric layer. The first low-k dielectric layer is formed before the upper electrode, and the second low-k dielectric layer is formed after the upper electrode is formed. That is, after the first low-k dielectric layer covering the oxygen vacancy resistive switching layer is formed on the substrate 101, an opening exposing the top surface of the oxygen vacancy resistive switching layer is formed in the first low-k dielectric layer, then the upper electrode is formed in the opening, and then the second low-k dielectric layer covering the upper electrode is formed on the first low-k dielectric layer. Thus, in this application, when the first low-k dielectric layer is formed, the upper electrode is formed by the first low-k dielectric layer. Since the top electrode has not yet been formed, there are no high aspect ratio holes between adjacent top electrodes. When forming the first low-K dielectric layer, there is no need to fill the high aspect ratio holes, and the formed first low-K dielectric layer will not have void defects. When forming the second low-K dielectric layer, since the first low-K dielectric layer already exists in the high aspect ratio holes between adjacent top electrodes, there is no need to fill the high aspect ratio holes when forming the second low-K dielectric layer, and the formed second low-K dielectric layer will not have void defects, thereby improving the performance of the formed resistive switching memory.
[0031] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of the structure after the lower electrode is formed in the substrate in a method for fabricating a semiconductor structure according to some embodiments of this application;
[0034] Figure 2 This is a schematic diagram of the structure after forming an oxygen vacancy resistive switching layer in a method for fabricating a semiconductor structure according to some embodiments of this application;
[0035] Figure 3This is a schematic diagram of the structure after forming a first low-k dielectric layer in a method for fabricating a semiconductor structure according to some embodiments of this application;
[0036] Figure 4 This is a schematic diagram of the structure after forming an opening in the first low-k dielectric layer to expose the top surface of the oxygen vacancy resistive switching layer in a method for fabricating a semiconductor structure according to some embodiments of this application.
[0037] Figure 5 This is a schematic diagram of the structure after the upper electrode is formed in the opening in a method for fabricating a semiconductor structure according to some embodiments of this application;
[0038] Figure 6 This is a schematic diagram of the structure after forming a second low-k dielectric layer in a method for fabricating a semiconductor structure according to some embodiments of this application;
[0039] Figure 7 This is a schematic diagram of the structure after the upper contact plug is formed in a method for fabricating a semiconductor structure according to some embodiments of this application.
[0040] Explanation of reference numerals in the attached figures:
[0041] Substrate 101; First dielectric layer 101a; Second dielectric layer 101b; Third dielectric layer 101c; Lower contact plug 102; First contact plug 103; Lower electrode 104; Oxygen vacancy resistive switching layer 105; First low-K dielectric layer 106; Opening 107; Upper electrode 108; Second low-K dielectric layer 109; Upper contact plug 110; Second contact plug 111. Detailed Implementation
[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0043] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0047] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.
[0048] This application provides a method for fabricating a semiconductor structure. Figures 1-7The accompanying drawings are schematic diagrams illustrating the various stages of a semiconductor structure fabrication method according to some embodiments of this application. The semiconductor structure fabrication method will now be described in detail with reference to the accompanying drawings.
[0049] refer to Figure 1 A substrate 101 is provided, wherein a lower electrode 104 is provided in the substrate 101.
[0050] The lower electrode 104 serves as one of the electrodes in a memory cell of a resistive random access memory (RRAM or ReRAM). In one example, the material of the lower electrode 104 is a metal, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. There can be multiple lower electrodes 104. After forming an oxygen vacancy resistive switching layer on the corresponding lower electrode 104 and an upper electrode on the oxygen vacancy resistive switching layer, one lower electrode 104, one oxygen vacancy resistive switching layer, and one upper electrode can constitute one memory cell of multiple resistive random access memories, i.e., multiple memory cells of multiple resistive random access memories can be formed.
[0051] The substrate 101 includes a substrate (not shown) and multiple dielectric layers on the substrate, with the lower electrode 104 located in the uppermost dielectric layer. The multiple dielectric layers are stacked sequentially. In one example, such as... Figure 1 As shown, the multilayer dielectric layer includes a first dielectric layer 101a, a second dielectric layer 101b located on the first dielectric layer 101a, and a third dielectric layer 101c located on the second dielectric layer 101b, with the lower electrode 104 located in the third dielectric layer 101c.
[0052] The substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator.
[0053] The materials of the first dielectric layer 101a, the second dielectric layer 101b, and the third dielectric layer 101c can be the same or different. In some embodiments, the materials of the first dielectric layer 101a and the third dielectric layer 101c are the same, while the material of the second dielectric layer 101b is different from the materials of the first dielectric layer 101a and the third dielectric layer 101c. In a specific example, the materials of the first dielectric layer 101a and the third dielectric layer 101c include one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material of the second dielectric layer 101b includes one or more of silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant (K less than 2.5) material.
[0054] In some embodiments, the substrate 101 further includes a lower contact plug 102 and a first contact plug 103. The lower contact plug 102 is located in the dielectric layer below the lower electrode 104 and is electrically connected to the lower electrode 104. The first contact plug 103 is located on one side of the lower contact plug 102. In a specific example, the first contact plug 103 and the lower contact plug 102 are located in the first dielectric layer 101a and the second dielectric layer 101b. The materials of the first contact plug 103 and the lower contact plug 102 are one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.
[0055] A CMOS (Complementary Metal Oxide Semiconductor) device is formed in or on the substrate. The first contact plug 103 is electrically connected to the CMOS device. In a specific example, the CMOS device includes a PMOS transistor and / or an NMOS transistor. The PMOS transistor and NMOS transistor can serve as logic devices. In some examples, the lower contact plug 102 can also be electrically connected to a portion of the CMOS device. The writing or erasing of memory cells in the resistive switching memory is controlled by the portion of the CMOS device (by controlling the lower electrode 104 to apply electrical excitation to the subsequently formed oxygen vacancy resistive switching layer to regulate the concentration and distribution of oxygen vacancies in the oxygen vacancy resistive switching layer, thereby achieving reversible switching between high-resistivity and low-resistivity states). That is, in this application, the fabrication process of the resistive switching memory can be compatible with CMOS technology or the fabrication process of logic devices.
[0056] In some embodiments, the process of forming the lower electrode 104 in the third dielectric layer 101c includes: forming a plurality of openings in the third dielectric layer 101c that expose the lower contact plug 102;
[0057] A lower electrode material layer is formed in the opening and in the third dielectric layer 101c. The process for forming the lower electrode material layer includes sputtering.
[0058] Planarization removes the lower electrode material layer outside the opening and forms the lower electrode 104 in the opening. Planarization includes a chemical mechanical polishing process.
[0059] refer to Figure 2 An oxygen vacancy resistive switching layer 105 is formed on the lower electrode 104.
[0060] When the oxygen vacancy resistive switching layer 105 is electrically excited, the concentration and distribution of oxygen vacancies in the layer are modulated, thereby achieving reversible switching between a high-resistivity state and a low-resistivity state. In one example, when a sufficiently large positive voltage is applied to the oxygen vacancy resistive switching layer 105, the electric field drives oxygen ions in the layer to detach from the lattice and move towards the electrode, leaving oxygen vacancies in their original positions. These oxygen vacancies continuously accumulate and extend, eventually forming a conductive filament connecting the upper and lower electrodes. This filament is typically composed of reduced metal atoms (such as Hf reduced from HfO2) or localized electrons (at the oxygen vacancies), causing the resistance of the oxygen vacancy resistive switching layer 105 to drop sharply, i.e., the "on" state. When a reverse voltage is applied to the oxygen vacancy resistive switching layer 105, the electric field drives the oxygen ions to flow back, or the Joule heating effect causes the conductive filament to melt locally, the oxygen vacancy is refilled or dissipated, the conductive channel is destroyed, and the resistance of the oxygen vacancy resistive switching layer 105 returns to a high resistance state, i.e., the "off" state.
[0061] In some embodiments, the thickness of the oxygen vacancy resistive switching layer 105 is 35 angstroms to 60 angstroms; the material of the oxygen vacancy resistive switching layer 105 includes HfO2, TaO X TiO2, ZrO2 or NiO.
[0062] In some embodiments, the formation process of the oxygen vacancy resistive switching layer 105 includes:
[0063] An oxygen vacancy resistive switching material layer is formed on substrate 101;
[0064] A patterned mask layer is formed on the oxygen vacancy resistive switching material layer;
[0065] Using a patterned mask layer as a mask, an oxygen vacancy resistive switching material layer is etched to form an oxygen vacancy resistive switching layer 105.
[0066] refer to Figure 3 A first low-K dielectric layer 106 is formed on the substrate 101, covering an oxygen vacancy resistive switching layer 105.
[0067] An upper electrode is subsequently formed in a first low-k dielectric layer 106, the thickness of which defines the thickness of the subsequently formed upper electrode. The thickness of the first low-k dielectric layer 106 is less than the thickness of a subsequently formed second low-k dielectric layer, the thickness of which defines the thickness of the subsequently formed upper contact plug. In some embodiments, the thickness of the first low-k dielectric layer 106 is 400-500 angstroms.
[0068] The first low-k dielectric layer 106 uses a low-k dielectric material, which can reduce parasitic capacitance between lines, reduce power consumption, and reduce signal crosstalk, thereby improving the speed and performance of the device. The dielectric constant of the first low-k dielectric layer 106 is less than or equal to 3. In one example, the dielectric constant of the low-k dielectric layer 106 is in the range of 2-3. The material of the first low-k dielectric layer 106 includes porous dielectric materials, specifically including one or more of porous obsidian, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide).
[0069] refer to Figure 4 An opening 107 is formed in the first low-K dielectric layer 106 to expose the top surface of the oxygen vacancy resistive switching layer 105.
[0070] The number of openings 107 is the same as the number of upper electrodes to be formed, and the same as the number of lower electrodes 104 already formed.
[0071] An etching process is used to etch the first low-K dielectric layer 106 to form an opening 107 in the first low-K dielectric layer 106 that exposes the top surface of the oxygen vacancy resistive switching layer 105.
[0072] refer to Figure 5 At opening 107 (reference) Figure 4 The upper electrode 108 is formed in the middle.
[0073] The upper electrode 108 serves as another electrode for a storage cell in a resistive random access memory (RRAM or ReRAM). In one example, the upper electrode 108 is made of a metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.
[0074] In some embodiments, the formation process of the upper electrode 108 includes: forming an upper electrode material layer on a first low-k dielectric layer 106, wherein the upper electrode material layer fills the opening 107.
[0075] The upper electrode material layer outside the opening 107 is removed by back etching, and the upper electrode 108 is formed in the opening 107. Since the first low-k dielectric layer 106 is relatively soft, this embodiment uses back etching (rather than chemical mechanical polishing) to remove the upper electrode material layer outside the opening 107, which can avoid the residue of the upper electrode material layer on the surface of the first low-k dielectric layer 106 and reduce the risk of short circuit between adjacent upper electrodes 108.
[0076] refer to Figure 6 A second low-k dielectric layer 109 is formed on the first low-k dielectric layer 106 to cover the upper electrode 108.
[0077] An upper contact plug and a portion of a second contact plug are subsequently formed in the first low-k dielectric layer 106. The thickness of the second low-k dielectric layer 109 is greater than the thickness of the first low-k dielectric layer 106. In some embodiments, the thickness of the second low-k dielectric layer 109 is 1100 angstroms to 1300 angstroms.
[0078] The second low-k dielectric layer 109 uses a low-k dielectric material, which can reduce parasitic capacitance between lines, reduce power consumption, and reduce signal crosstalk, thereby improving the speed and performance of the device. The dielectric constant of the second low-k dielectric layer 109 is less than or equal to 3. In one example, the dielectric constant of the second low-k dielectric layer 109 is in the range of 2-3. The second low-k dielectric layer 109 is made of the same material as the first low-k dielectric layer 106. The material of the second low-k dielectric layer 109 includes a porous dielectric material, specifically including one or more of porous obsidian, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide).
[0079] In this application, the low-k dielectric layer covering the upper electrode 108 includes a first low-k dielectric layer 106 and a second low-k dielectric layer 109 located on the first low-k dielectric layer 106. The first low-k dielectric layer 106 is formed before the upper electrode 108, and the second low-k dielectric layer 109 is formed after the upper electrode 108 is formed. That is, after the first low-k dielectric layer 106 covering the oxygen vacancy resistive switching layer 105 is formed on the substrate 101, an opening is formed in the first low-k dielectric layer 106 exposing the top surface of the oxygen vacancy resistive switching layer 105. Then, the upper electrode 108 is formed in the opening, and then the second low-k dielectric layer 109 covering the upper electrode 108 is formed on the first low-k dielectric layer 106. Thus, in this application, after the formation of the first low-k dielectric layer 106, the second low-k dielectric layer 109 is formed after the upper electrode 108 is formed. When a low-K dielectric layer 106 is formed, since the upper electrode 108 has not yet been formed, there will be no high aspect ratio holes between adjacent upper electrodes 108. Therefore, there is no need to fill the high aspect ratio holes when forming the first low-K dielectric layer 106, and the formed first low-K dielectric layer 106 will not have void defects. When forming the second low-K dielectric layer 109, since the first low-K dielectric layer 106 already exists in the high aspect ratio holes between adjacent upper electrodes 108, there is no need to fill the high aspect ratio holes when forming the second low-K dielectric layer 109, and the formed second low-K dielectric layer 109 will not have void defects, thereby improving the performance of the formed resistive switching memory.
[0080] refer to Figure 7 An upper contact plug 110 electrically connected to the upper electrode 108 is formed in the second low-K dielectric layer 109.
[0081] In some embodiments, while an upper contact plug 110 electrically connected to the upper electrode 108 is formed in the second low-K dielectric layer 109, a second contact plug 111 electrically connected to the first contact plug 103 is formed in the second low-K dielectric layer 109 and the first low-K dielectric layer 106.
[0082] In a specific embodiment, the formation process of the upper contact plug 110 and the second contact plug 111 includes: sequentially etching the second low-k dielectric layer 109 and the first low-k dielectric layer 106; forming a first opening in the first low-k dielectric layer 106 to expose the upper electrode 108; forming a second opening in the second low-k dielectric layer 109 and the first low-k dielectric layer 106 to expose the first contact plug 103; the depth of the second opening is greater than the depth of the first opening; during the etching process, the upper electrode 108 can serve as a stop layer for forming the first opening; forming a metal material layer in the first and second openings and on the top surface of the second low-k dielectric layer 109; etching back to remove the metal material layer on the top surface of the second low-k dielectric layer 109; forming the upper contact plug 110 in the first opening; and forming the second contact plug 111 in the second opening.
[0083] In some embodiments, the upper contact plug 110 and the second contact plug 111 are made of one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.
[0084] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0086] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a semiconductor, characterized in that, include: A substrate is provided, wherein a lower electrode is present in the substrate; An oxygen vacancy resistive switching layer is formed on the lower electrode; A first low-k dielectric layer covering the oxygen vacancy resistive switching layer is formed on the substrate; An opening is formed in the first low-k dielectric layer to expose the top surface of the oxygen vacancy resistive switching layer; An upper electrode is formed in the opening; A second low-k dielectric layer covering the upper electrode is formed on the first low-k dielectric layer; An upper contact plug electrically connected to the upper electrode is formed in the second low-K dielectric layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first low-k dielectric layer and the second low-k dielectric layer are made of the same material.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The dielectric constants of the first low-k dielectric layer and the second low-k dielectric layer are less than or equal to 3.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation process of the oxygen vacancy resistive switching layer includes: An oxygen vacancy resistive switching material layer is formed on the substrate; A patterned mask layer is formed on the oxygen vacancy resistive switching material layer; Using the patterned mask layer as a mask, the oxygen vacancy resistive switching material layer is etched to form the oxygen vacancy resistive switching layer.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of forming the upper electrode includes: forming an upper electrode material layer on the first low-k dielectric layer, wherein the upper electrode material layer fills the opening; The upper electrode material layer outside the opening is removed by etching back, and the upper electrode is formed in the opening.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and multiple dielectric layers on the substrate, with the lower electrode located in the uppermost dielectric layer.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The substrate also includes a lower contact plug and a first contact plug. The lower contact plug is located in a dielectric layer below the lower electrode and is electrically connected to the lower electrode. The first contact plug is located on one side of the lower contact plug. A CMOS device is formed in or on the substrate, and the first contact plug is electrically connected to the CMOS device.
8. The method for preparing a semiconductor structure according to claim 8, characterized in that, While forming an upper contact plug electrically connected to the upper electrode in the second low-K dielectric layer, a second contact plug electrically connected to the first contact plug is formed in both the second low-K dielectric layer and the first low-K dielectric layer.
9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the first low-k dielectric layer is 400-500 angstroms; The thickness of the second low-K dielectric layer is 1100 angstroms to 1300 angstroms.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the oxygen vacancy resistive switching layer is 35 angstroms to 60 angstroms; The oxygen vacancy resistive layer is made of materials including HfO2 and TaO. X TiO2, ZrO2 or NiO.