Super-junction MOSFET device and processing method thereof

Abstract

The invention provides a super-junction MOSFET device and a processing method thereof, and the device comprises a substrate structure, a drain conductor, a voltage-withstanding region, a groove-type gate structure, a gate conductor, a second base region, a cut-off region, a first base region, a source region, and a high-k dielectric layer which penetrates through the cut-off region and is embedded into the second voltage-withstanding region. And the source conductor covers the top of the source region, the top of the first base region, the top of the cut-off region and the top of the high-k dielectric layer. When the device is in a voltage-withstanding state, the high-k dielectric layer can collect electric field lines generated by ionization donors in the first voltage-withstanding region of the first conduction type, so that electric field distribution in the super-junction structure becomes more uniform, the sensitivity of breakdown voltage of the device to charge balance is reduced, and even under the condition of unbalanced charges, the breakdown voltage of the device is reduced. And the breakdown voltage of the device can be ensured to a certain extent, the difficulty of process production can be reduced, and quality control guarantee can be realized.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor devices, and more specifically, to a superjunction MOSFET device and its fabrication method. Background Technology

[0002] Superjunction MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) offer advantages such as low on-resistance, fast switching speed, and low switching losses. They are suitable for various full-bridge and half-bridge circuits and hold a significant market share in consumer electronics, automotive electronics, and industrial control. Superjunction MOSFETs employ a superjunction structure in their breakdown region, consisting of alternating n-pillar and p-pillar regions arranged laterally. When reverse biased, a lateral electric field is generated at the PN junction of the n-pillar and p-pillar regions. Before breakdown, the entire n-pillar and p-pillar regions are nearly completely depleted laterally. This reduces the contribution of ionized impurities to the longitudinal electric field, increasing the breakdown voltage without affecting the specific on-resistance.

[0003] However, for traditional superjunction MOSFET devices, in order to ensure the breakdown voltage of the device, it is necessary to satisfy the condition of the n-pillar region (with a doping concentration of N). A ) and p-pillar region (doping concentration of N) D The charge balance condition of (N) is... A -N D ) / N D =0. However, in actual processing, it is impossible to completely guarantee (N) A -N D ) / N D =0, usually (N) A -N D ) / N D >0 or (N) A -N D ) / N D In the case where the value is less than 0, the breakdown voltage of the device decreases significantly in both scenarios. This indicates that the breakdown voltage of traditional superjunction MOSFETs is highly sensitive to the doping concentrations in the n-pillar and p-pillar regions. The charge balance of the doping concentrations in these regions significantly impacts the breakdown voltage, requiring precise control of the doping concentrations during manufacturing. This makes the manufacturing process too difficult and hinders the assurance of quality stability. Reducing the sensitivity of the device's breakdown voltage to charge balance would simplify manufacturing and improve quality control. Therefore, how to reduce the sensitivity of the device's breakdown voltage to charge balance has become a key challenge for those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a superjunction MOSFET device and its fabrication method to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a superjunction MOSFET device, the superjunction MOSFET device comprising: Drain conductor in contact with the bottom surface of the substrate structure; And a withstand voltage region disposed on the top of the substrate structure, the withstand voltage region including at least one first withstand voltage region belonging to a first conductivity type and at least one second withstand voltage region belonging to a second conductivity type, the first withstand voltage region and the second withstand voltage region being arranged in an adjacent columnar alternating manner on the upper layer of the substrate structure; A slotted gate structure is formed at the top of the first withstand voltage region, and a gate conductor is disposed on the surface of the slotted gate structure; A second base region is formed by doping at the top of the first breakdown voltage region, and a stop region is formed by doping at the top of the second breakdown voltage region; A first base region formed by doping near the cutoff region at the top of the second base region and a source region formed by doping near the trench gate structure at the top of the second base region; A high-k dielectric layer penetrates the cutoff region and is embedded in the second withstand voltage region; A source conductor covering the top of the source region, the top of the first base region, the top of the cutoff region, and the top of the high-k dielectric layer, wherein the source conductor does not completely cover the top of the source region.

[0006] Optionally, the substrate structure includes a substrate and an auxiliary layer; The drain conductor is in contact with the bottom surface of the substrate, the bottom of the auxiliary layer is in contact with the top surface of the substrate, and the withstand voltage region is disposed on the top of the auxiliary layer.

[0007] Optionally, the trench gate structure includes a gate oxide layer grown on the inner surface of the trench at the top of the first withstand voltage region and conductive polysilicon filling the trench containing the gate oxide layer.

[0008] Optionally, the lateral width of the high-k dielectric layer is 40% to 60% of the lateral width of the second pressure-resistant region.

[0009] Optionally, the longitudinal depth of the high-k dielectric layer embedded in the second pressure-resistant region is 40% to 60% of the longitudinal depth of the second pressure-resistant region.

[0010] Optionally, the longitudinal depth of the high-k dielectric layer embedded in the second withstand voltage region is 50% of the longitudinal depth of the second withstand voltage region.

[0011] Optionally, the doping concentration of the cutoff region is lower than the doping concentration of the second base region.

[0012] Optionally, the doping concentration of the cutoff region is higher than that of the second breakdown voltage region.

[0013] In a second aspect, embodiments of the present invention provide a method for fabricating a superjunction MOSFET device, the method comprising: Step 1: After the auxiliary layer in the substrate structure is set, an initial withstand voltage region of the first conductivity type is epitaxially grown on the auxiliary layer. After the initial withstand voltage is formed, the initial withstand voltage is etched at a set interval to form a first withstand voltage region with multiple grooves and protrusions. The grooves formed by the initial withstand voltage are backfilled with a conductor material of the first conductivity type to form a second withstand voltage region. Step 2: A slotted gate structure is formed on top of the first withstand voltage region; Step 3: A second base region is generated by doping on the top of the first breakdown voltage region, and a stop region is generated by doping on the top of the second breakdown voltage region; Step 4: A first base region is formed by doping near the top of the second base region and close to the cutoff region, and a source region is formed by doping near the top of the second base region and close to the trench gate structure. Step 5: Create a groove that penetrates the cutoff area and is embedded in the second pressure-resistant area, and fill it with a high-k dielectric material to form a high-k dielectric layer; Step 6: A source conductor is disposed on the top of the source region, the first base region, the cutoff region, and the high-k dielectric layer; a gate conductor is disposed on the surface of the trench gate structure; and a drain conductor is disposed on the lower surface of the substrate of the substrate structure.

[0014] Compared to existing technologies, the superjunction MOSFET device and its fabrication method provided in this invention include: a substrate structure, a drain conductor, a breakdown voltage region, a trench gate structure, a gate conductor, a second base region, a cutoff region, a first base region, a source region, and a through-cutoff region, with a high-k dielectric layer embedded in the second breakdown voltage region, and a source conductor covering the top of the source region, the top of the first base region, the top of the cutoff region, and the top of the high-k dielectric layer. When the device is in a breakdown voltage state, the high-k dielectric layer can collect the electric field lines generated by ionized donors in the first breakdown voltage region of the first conductivity type, making the electric field distribution in the superjunction structure more uniform, reducing the sensitivity of the device breakdown voltage to charge balance, and even under charge imbalance conditions, it can guarantee the device breakdown voltage to a certain extent, reducing the difficulty of process manufacturing and facilitating quality control assurance.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic cross-sectional view of a two-dimensional structure of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of a two-dimensional structure of a comparative MOSFET device provided in an embodiment of the present invention; Figure 3 A schematic diagram of the initial breakdown voltage region structure of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram showing the distribution of the breakdown region structure of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 5 A schematic diagram of the trench gate structure of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 6 A schematic diagram showing the second base region and cutoff region of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 7 A schematic diagram showing the source region and the first base region of a superjunction MOSFET device provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the high-k dielectric layer setting region of the superjunction MOSFET device provided in an embodiment of the present invention; Figure 9 This is a schematic diagram comparing the sensitivity of the breakdown voltage of a superjunction MOSFET device to charge balance according to an embodiment of the present invention. Figure 10 This is a schematic diagram comparing the reverse recovery current waveform of the superjunction MOSFET device provided in an embodiment of the present invention.

[0018] In the figure: 1-Drain conductor; 2-Gate conductor; 3-Source conductor; 10-Substrate; 20-Auxiliary layer; 30-First breakdown voltage region; 40-Source region; 31-Second breakdown voltage region; 32-High-k dielectric layer; 41-First base region; 42-Second base region; 43-Stop region; 50-Conductive polysilicon; 51-Gate oxide layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Please refer to Figure 1 , Figure 1 This is a two-dimensional cross-sectional schematic diagram of a superjunction MOSFET device provided in an embodiment of the present invention. The superjunction MOSFET device includes: a drain conductor 1 in contact with the bottom surface of a substrate structure; The voltage withstand region is disposed on the top of the substrate structure. The voltage withstand region includes at least one first voltage withstand region 30 belonging to the first conductivity type and at least one second voltage withstand region 31 belonging to the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. The first voltage withstand region 30 and the second voltage withstand region 31 are columnar voltage withstand regions, which can also be called columnar regions. The first voltage withstand region 30 and the second voltage withstand region 31 are arranged in an adjacent and alternating columnar manner on the upper layer of the substrate structure (auxiliary layer 20). That is, there is a second voltage withstand region 31 between two first voltage withstand regions 30 and a first voltage withstand region 30 between two second voltage withstand regions 31.

[0026] The slotted gate structure is formed at the top of the first withstand voltage region 30. The distance between the sidewall of the slotted gate structure and the sidewall of the first withstand voltage region 30 exceeds a preset distance value. Optionally, the slotted gate structure is located in the middle of the top of the first withstand voltage region 30, and the gate conductor 2 is disposed on the surface of the slotted gate structure.

[0027] A second base region 42 is formed by doping at the top of the first breakdown region 30 (which can be achieved through ion implantation), and a stop region 43 is formed by doping at the top of the second breakdown region 31 (which can be achieved through ion implantation). The first base region 41, which is formed by doping near the top of the second base region 42 and the second base region 42, which is formed by doping near the top of the trench gate structure (which can be formed by doping), is used as a base region of a first conductivity type, and the second base region 42 is used as a base region of a second conductivity type. A high-k dielectric layer 32 penetrates the cutoff region 43 and is embedded in the second pressure-resistant region 31. There is a certain gap between the bottom of the high-k dielectric layer 32 and the bottom of the second pressure-resistant region 31, and there is a certain gap between the sidewall of the high-k dielectric layer 32 and the sidewall of the second pressure-resistant region 31.

[0028] The source conductor 3 covers the top of the source region 40, the top of the first base region 41, the top of the cutoff region 43, and the top of the high-k dielectric layer 32, but the source conductor 3 does not completely cover the top of the source region 40.

[0029] A source conductor 3 is disposed on the surface of the source region 40 and the first base region 41 between the two slotted gate structures. The gate conductor 2 and the source conductor 3 are not connected.

[0030] Taking a superjunction MOSFET device with N-type as the first conductivity type and P-type as the second conductivity type as an example, when the voltage across the gate and source is zero, regardless of whether the drain-source voltage is forward-biased or reverse-biased, there is always a reverse-biased PN junction in the semiconductor, preventing the device from conducting. When a forward voltage is applied across the gate and source and V... GS When the voltage rises to the threshold, an inversion layer is formed in the P region, creating a path between the source and drain, at which point the MOSFET turns on.

[0031] In this embodiment of the invention, a high-k dielectric refers to a material with a high dielectric constant, which is greater than that of silicon (11.7). The dielectric constant, denoted by the symbol k, is a measure of the capacitance of a material relative to a vacuum or air in an electric field. High-k dielectrics have a higher dielectric constant than conventional insulating materials.

[0032] To better illustrate the advantages of the superjunction MOSFET device provided in the embodiments of the present invention, the embodiments of the present invention also provide a comparative MOSFET device, please refer to... Figure 2 , Figure 2 This is a schematic cross-sectional view of a two-dimensional structure of a comparative MOSFET device provided in an embodiment of the present invention. Figure 2 and Figure 1 The only difference is the absence of a cutoff region 43 and a high-k dielectric layer 32. Figure 2 The first base area 41 is continuously connected.

[0033] like Figure 2 The superjunction MOSFET device structure shown has n-pillar regions (first breakdown region 30) and p-pillar regions (second breakdown region 31) arranged alternately in the lateral direction when the first conductivity type is N-type and the second conductivity type is P-type. When subjected to reverse bias, this structure generates a lateral electric field at the PN junction of the n-pillar and p-pillar regions. Before breakdown, the entire n-pillar and p-pillar regions are nearly completely depleted in the lateral direction. This reduces the contribution of bulk ionized impurities to the longitudinal electric field, increasing the breakdown voltage of the device without affecting its specific on-resistance. However, the breakdown voltage of this device is highly sensitive to the doping concentration of the n-pillar and p-pillar regions; these regions must meet charge balance conditions, otherwise, it will significantly affect the breakdown voltage. Furthermore, the alternating lateral arrangement of the n-pillar and p-pillar regions significantly increases the PN junction area of ​​the body diode, resulting in more charge carriers stored inside the device during forward injection, leading to increased reverse recovery charge (Q0). rrThe refractive index (RI) increases significantly. Furthermore, the n-pillar and p-pillar regions are rapidly depleted during reverse recovery, making the reverse recovery of the body diode stiffer and the softness factor (S) too small.

[0034] To address the above problems, the structure and related construction of the second withstand voltage region and the high-k dielectric layer have been improved in this embodiment of the invention, specifically as follows: Figure 1 As shown. When the device is in the withstand voltage state, the high-k dielectric layer can collect the electric field lines generated by ionized donors in the first withstand voltage region of the first conductivity type, which can make the electric field distribution in the superjunction structure more uniform, reduce the sensitivity of the device breakdown voltage to charge balance, and even under the condition of charge imbalance, can ensure the breakdown voltage of the device to a certain extent, which can reduce the difficulty of process manufacturing and help to achieve quality control assurance.

[0035] In addition, a high-k dielectric layer is provided at the top center of the second withstand voltage region, making the top region of the second withstand voltage region relatively narrower. During the reverse recovery process of the body diode, the top region of the second withstand voltage region will be depleted in advance, increasing the resistance on the hole extraction path during the reverse recovery process, slowing down the hole extraction speed during the reverse recovery process, thereby improving the reverse recovery softness and suppressing the reverse recovery oscillation.

[0036] Furthermore, the contact area between the source conductor and the first base region is reduced, while the contact area with the cutoff region and the high-k dielectric is increased. The high-k dielectric provides insulation, and the doping concentration in the cutoff region is lower than that in the first base region. When the device operates in reverse conduction mode, the source conductor collects electrons injected from the first breakdown region into the cutoff layer. This reduces the hole injection efficiency in reverse conduction mode, decreases the number of non-equilibrium carriers in the body diode, and thus reduces the reverse recovery charge Q of the body diode. rr .

[0037] Please continue to refer to this. Figure 1 The substrate structure includes a substrate 10 and an auxiliary layer 20.

[0038] The drain conductor 1 is in contact with the bottom surface of the substrate 10, and the bottom of the auxiliary layer 20 is in contact with the top surface of the substrate 10. The doping concentration of the auxiliary layer 20 is lower than that of the substrate 10. The auxiliary layer 20 withstands an applied voltage of no more than 20% in the device blocking state, and the withstand voltage region is located on the top of the auxiliary layer 20.

[0039] Please continue to refer to this. Figure 1 The trench gate structure includes a gate oxide layer 51 grown on the inner surface of the trench at the top of the first withstand voltage region 30 and a conductive polysilicon 50 filled in the combined trench of the gate oxide layer 51, and the gate conductor 2 is disposed on the upper surface of the conductive polysilicon 50.

[0040] Optionally, the lateral width of the high-k dielectric layer 32 is 40% to 60% of the lateral width of the second pressure-resistant region 31, and the longitudinal depth of the high-k dielectric layer 32 embedded in the second pressure-resistant region 31 is 40% to 60% of the longitudinal depth of the second pressure-resistant region 31. Alternatively, the longitudinal depth of the high-k dielectric layer 32 embedded in the second pressure-resistant region 31 is 50% of the longitudinal depth of the second pressure-resistant region 31.

[0041] When the width of the high-k dielectric layer 32 is 40% to 60% of the width of the second withstand voltage region 31, and the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 is 40% to 60% of the depth of the second withstand voltage region 31, the reverse recovery performance optimization effect can be achieved within this range, and the sensitivity of the device breakdown voltage to charge balance can be reduced.

[0042] When the width of the high-k dielectric layer 32 is 50% of the width of the second withstand voltage region 31, and when the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 changes, the dielectric constant of the high-k dielectric layer 32 can also effectively ensure the withstand voltage capability of the device and reduce the sensitivity of the device breakdown voltage to charge balance.

[0043] For example, when the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 is 40% of the depth of the second withstand voltage region 31, adjusting the dielectric constant of the high-k dielectric layer 32 to 15~20 can ensure the withstand voltage capability of the device and reduce the sensitivity of the device breakdown voltage to charge balance.

[0044] When the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 is 50% of the depth of the second withstand voltage region 31, adjusting the dielectric constant of the high-k dielectric layer 32 to 20~25 can ensure the withstand voltage capability of the device and reduce the sensitivity of the device breakdown voltage to charge balance.

[0045] When the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 is 60% of the depth of the second withstand voltage region 31, adjusting the dielectric constant of the high-k dielectric layer 32 to 25~30 can ensure the withstand voltage capability of the device and reduce the sensitivity of the device breakdown voltage to charge balance.

[0046] When the width of the high-k dielectric layer 32 is 40% to 60% of the width of the second breakdown region 31, the reverse recovery performance of the superjunction MOSFET conductor gradually improves as the vertical depth of the high-k dielectric layer 32 embedded in the second breakdown region 31 gradually increases. Simulation calibration tests show that when the width of the high-k dielectric layer 32 is 50% of the width of the second breakdown region 31, and the vertical depth of the high-k dielectric layer 32 embedded in the second breakdown region 31 exceeds 50% of the depth of the second breakdown region 31, the breakdown voltage performance of the superjunction MOSFET conductor deteriorates as the vertical depth of the high-k dielectric layer 32 embedded in the second breakdown region 31 increases.

[0047] Therefore, when the width of the high-k dielectric layer 32 is 50% of the width of the second withstand voltage region 31, the longitudinal depth of the high-k dielectric layer 32 embedded in the second withstand voltage region 31 is 50% of the depth of the second withstand voltage region 31, which is a preferred embodiment. In this case, the withstand voltage performance of the superjunction MOSFET conductor is not affected, and the reverse recovery performance is relatively excellent.

[0048] Optionally, the doping concentration of the cutoff region 43 is lower than that of the second base region 42, that is, the doping concentration of the first base region 41 is greater than that of the second base region 42, which is greater than that of the cutoff region 43. Since the doping concentration of the cutoff region is lower than that of the second base region, when the device operates in reverse conduction mode, electrons can easily be injected from the first breakdown region into the cutoff layer and then collected by the source conductor. This reduces the hole injection efficiency in reverse conduction mode, thereby reducing the reverse recovery charge Q of the body diode. rr .

[0049] Optionally, the doping concentration of the cutoff region 43 is higher than that of the second breakdown voltage region 31, so that electrons can pass through the cutoff region 43 and avoid punch-through in the device.

[0050] This invention also provides a method for fabricating a superjunction MOSFET device, comprising: Step 1: After the auxiliary layer in the substrate structure is set, an initial withstand voltage region of the first conductivity type is epitaxially grown on the auxiliary layer. After the initial withstand voltage is formed, the initial withstand voltage is etched at a set interval to form a plurality of trenches and protrusions in the first withstand voltage region. The trenches formed by the initial withstand voltage are backfilled with a conductor material of the first conductivity type to form a second withstand voltage region. The first withstand voltage region and the second withstand voltage region are arranged in an adjacent and alternating columnar configuration on the upper layer of the auxiliary layer.

[0051] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the initial breakdown voltage region structure of the superjunction MOSFET device provided in an embodiment of the present invention. Figure 4 This is a schematic diagram showing the distribution of the breakdown voltage region structure of the superjunction MOSFET device provided in an embodiment of the present invention. The initial breakdown voltage region has the same conductivity type as the first breakdown voltage region 30. After etching, the retained portion is the first breakdown voltage region 30. The second breakdown voltage region 31 is formed by backfilling the trench formed by the initial breakdown voltage region with a conductor material of the first conductivity type.

[0052] Step 2: A slotted gate structure is formed on top of the first withstand voltage region.

[0053] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the trench gate structure of a superjunction MOSFET device provided in an embodiment of the present invention.

[0054] Step 3: A second base region is generated by doping at the top of the first breakdown voltage region, and a cutoff region is generated by doping at the top of the second breakdown voltage region.

[0055] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the second base region and cutoff region of the superjunction MOSFET device provided in an embodiment of the present invention.

[0056] Step 4: A first base region is generated by doping near the cutoff region at the top of the second base region, and a source region is generated by doping near the trench gate structure at the top of the second base region.

[0057] Optionally, in this embodiment of the invention, the doping process can be completed by ion implantation.

[0058] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the source region and the first base region of a superjunction MOSFET device provided in an embodiment of the present invention.

[0059] Step 5: Create a groove that penetrates the cutoff area and embeds the second pressure-resistant area, and fill it with high-k dielectric material to form a high-k dielectric layer.

[0060] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the high-k dielectric layer setting region of the superjunction MOSFET device provided in an embodiment of the present invention.

[0061] Step 6: A source conductor is disposed on the top of the source region, the first base region, the cutoff region, and the high-k dielectric layer; a gate conductor is disposed on the surface of the trench gate structure; and a drain conductor is disposed on the lower surface of the substrate of the substrate structure. The source conductor does not completely cover the top of the source region.

[0062] Based on the superjunction MOSFET device fabrication method provided in this embodiment of the invention, the above-mentioned superjunction MOSFET device can be obtained, specifically as follows: Figure 1 As shown, the relevant technical effects will not be elaborated here.

[0063] Please refer to Figure 9 and Figure 10 , Figure 9 This is a schematic diagram comparing the sensitivity of the breakdown voltage of a superjunction MOSFET device to charge balance according to an embodiment of the present invention. Figure 10 This is a schematic diagram comparing the reverse recovery current waveform of the superjunction MOSFET device provided in an embodiment of the present invention.

[0064] like Figure 9As shown, considering the sensitivity of device breakdown voltage to charge balance, the novel superjunction MOSFET device provided in this invention is analyzed and compared with a traditional superjunction MOSFET device. The horizontal axis represents (N... A -N D ) / N D , where N A The doping concentration of N in the first breakdown voltage region 30 is... D The doping concentration of the second breakdown voltage region 31 is represented by the vertical axis, and the breakdown voltage V is represented by the vertical axis. B The unit is V.

[0065] like Figure 9 As shown, to satisfy the breakdown voltage V B >600V is the standard, and the traditional superjunction MOSFET (N) A -N D ) / N D The range is -13.1% to 15.4%, while the new superjunction MOSFET's (N A -N D ) / N D The ranges are -19.0% to 21.9%. While meeting the 600V withstand voltage requirement, the new superjunction MOSFET has a greater process margin for the doping concentration of the n-pillar and p-pillar regions, which reduces the sensitivity of the device breakdown voltage to the charge balance of the n-pillar and p-pillar regions.

[0066] like Figure 10 As shown, the reverse recovery current is I. SD The voltage between the drain and source of a MOSFET device is V. DS As can be seen, during the reverse recovery phase, traditional superjunction MOSFETs exhibit the following characteristics: longer reverse recovery duration, larger peak reverse recovery current and reverse recovery charge, and significant current and voltage oscillations, which can lead to device failure and compromise device reliability. Compared to traditional superjunction MOSFETs, the superjunction MOSFET device provided in this embodiment of the invention reduces the peak reverse recovery current by 30% and the reverse recovery charge by 50%, without exhibiting current and voltage oscillations. The reverse recovery performance and reliability of the device are thus greatly improved.

[0067] In summary, the superjunction MOSFET device and its fabrication method provided by this invention include: a substrate structure, a drain conductor, a breakdown voltage region, a trench gate structure, a gate conductor, a second base region, a cutoff region, a first base region, a source region, and a through-cutoff region, with a high-k dielectric layer embedded in the second breakdown voltage region, and a source conductor covering the top of the source region, the top of the first base region, the top of the cutoff region, and the top of the high-k dielectric layer. When the device is in a breakdown voltage state, the high-k dielectric layer can collect the electric field lines generated by ionized donors in the first breakdown voltage region of the first conductivity type, making the electric field distribution in the superjunction structure more uniform, reducing the sensitivity of the device breakdown voltage to charge balance, and even under charge imbalance conditions, it can guarantee the device breakdown voltage to a certain extent, reducing the difficulty of process manufacturing and facilitating quality control assurance.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0069] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A superjunction MOSFET device, characterized in that, The superjunction MOSFET device includes: Drain conductor in contact with the bottom surface of the substrate structure; And a withstand voltage region disposed on the top of the substrate structure, the withstand voltage region including at least one first withstand voltage region belonging to a first conductivity type and at least one second withstand voltage region belonging to a second conductivity type, the first withstand voltage region and the second withstand voltage region being arranged in an adjacent columnar alternating manner on the upper layer of the substrate structure; A slotted gate structure is formed at the top of the first withstand voltage region, and a gate conductor is disposed on the surface of the slotted gate structure; A second base region is formed by doping at the top of the first breakdown voltage region, and a stop region is formed by doping at the top of the second breakdown voltage region; A first base region formed by doping near the cutoff region at the top of the second base region and a source region formed by doping near the trench gate structure at the top of the second base region; A high-k dielectric layer penetrates the cutoff region and is embedded in the second withstand voltage region; A source conductor covering the top of the source region, the top of the first base region, the top of the cutoff region, and the top of the high-k dielectric layer, wherein the source conductor does not completely cover the top of the source region.

2. The superjunction MOSFET device as described in claim 1, characterized in that, The substrate structure includes a substrate and an auxiliary layer; The drain conductor is in contact with the bottom surface of the substrate, the bottom of the auxiliary layer is in contact with the top surface of the substrate, and the withstand voltage region is disposed on the top of the auxiliary layer.

3. The superjunction MOSFET device as described in claim 1, characterized in that, The trench gate structure includes a gate oxide layer grown on the inner surface of the trench at the top of the first withstand voltage region and conductive polysilicon filling the trench containing the gate oxide layer.

4. The superjunction MOSFET device as described in claim 1, characterized in that, The lateral width of the high-k dielectric layer is 40% to 60% of the lateral width of the second pressure-resistant zone.

5. The superjunction MOSFET device as described in claim 1, characterized in that, The longitudinal depth to which the high-k dielectric layer is embedded in the second pressure-resistant region is 40% to 60% of the longitudinal depth of the second pressure-resistant region.

6. The superjunction MOSFET device as described in claim 5, characterized in that, The longitudinal depth of the high-k dielectric layer embedded in the second withstand voltage zone is 50% of the longitudinal depth of the second withstand voltage zone.

7. The superjunction MOSFET device as described in claim 1, characterized in that, The doping concentration of the cutoff region is lower than that of the second base region.

8. The superjunction MOSFET device as described in claim 1, characterized in that, The doping concentration in the cutoff region is higher than that in the second breakdown voltage region.

9. A method for fabricating a superjunction MOSFET device, characterized in that, The method includes: Step 1: After the auxiliary layer in the substrate structure is set, an initial withstand voltage region of the first conductivity type is epitaxially grown on the auxiliary layer. After the initial withstand voltage is formed, the initial withstand voltage is etched at a set interval to form a first withstand voltage region with multiple grooves and protrusions. The grooves formed by the initial withstand voltage are backfilled with a conductor material of the first conductivity type to form a second withstand voltage region. Step 2: A slotted gate structure is formed on top of the first withstand voltage region; Step 3: A second base region is generated by doping on the top of the first breakdown voltage region, and a stop region is generated by doping on the top of the second breakdown voltage region; Step 4: A first base region is formed by doping near the top of the second base region and close to the cutoff region, and a source region is formed by doping near the top of the second base region and close to the trench gate structure. Step 5: Create a groove that penetrates the cutoff area and is embedded in the second pressure-resistant area, and fill it with a high-k dielectric material to form a high-k dielectric layer; Step 6: A source conductor is disposed on the top of the source region, the first base region, the cutoff region, and the high-k dielectric layer; a gate conductor is disposed on the surface of the trench gate structure; and a drain conductor is disposed on the lower surface of the substrate of the substrate structure.

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