Differential pair signal lightning suppression chip and manufacturing method thereof

Abstract

The invention discloses a differential pair signal thunder and lightning suppression chip and a manufacturing method, the differential pair signal thunder and lightning suppression chip comprises a packaging substrate, a silicon wafer is arranged on the packaging substrate, the silicon wafer is connected with the packaging substrate, a first diode, a second diode, a third diode, a fourth diode and a transient suppression diode which form a rectifier bridge are integrated on the silicon wafer, and the diodes are mutually connected. And the pins are connected with the pins of the packaging substrate. The method comprises the following steps: selecting a P-type semiconductor silicon wafer as a substrate, and preparing PN junctions of all diodes on the silicon wafer substrate; metallization is carried out on the silicon wafer, and the bottom surface of the metallized silicon wafer is connected with the packaging substrate; the silicon wafer is connected with the pins of the packaging substrate through the bonding wires, finally, the packaging substrate is wrapped with a plastic packaging material, and the plastic packaging material is cured. According to the invention, the problems of inconsistent clamping voltage of the differential end and relatively large parasitic capacitance of the semiconductor discharge tube in the prior art are solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip technology, specifically relating to a differential pair signal lightning suppression chip and its manufacturing method. Background Technology

[0002] The differential pair signal lightning suppression chip provides an integrated lightning suppressor that can address the lightning protection requirements of high-speed differential pair signals. Existing lightning suppressors for high-speed differential pair signals typically employ protection circuit diagrams as shown below. Figure 1 and Figure 2 As shown, the protective components use devices with small parasitic capacitance, such as gas discharge tubes (GDTs), glass discharge tubes (SPGs), and semiconductor discharge tubes (TSSs). These devices are mounted on a printed circuit board, and the protective circuit is connected in parallel between the high-speed differential pair signal line and the housing ground via a connector. When a transient lightning interference voltage is induced on the high-speed signal line, the gas discharge tube, glass discharge tube, semiconductor discharge tube, etc., connected between the high-speed differential pair signal line and the housing ground, clamp the transient lightning interference voltage on the high-speed differential pair signal line within a certain range and discharge the interference current, thus clamping the voltage on the high-speed differential pair signal line to a lower range and protecting the downstream transceiver from damage by transient lightning interference voltage.

[0003] When using gas discharge tubes or glass discharge tubes in high-speed differential pair signal lightning protection circuits, the advantage lies in the very small parasitic capacitance of the selected gas discharge tubes or glass discharge tubes, typically around 1 pF; for example... Figure 3 As shown, the use of gas discharge tubes or glass discharge tubes as protective devices has almost no impact on signal integrity during high-speed signal transmission, and the signal is a near-standard square wave.

[0004] However, it has certain problems. First, the protective devices for the positive and negative terminals of the high-speed differential pair signal have different electrical performance characteristics. This results in asynchronous clamping of the positive and negative terminals, and the clamping voltage values ​​are also different. This can cause errors in signal transmission or even damage the transceiver. Second, when using gas discharge tubes or glass discharge tubes, their response time is generally in the microsecond range due to their inherent characteristics, and the response time varies significantly between devices. The signal rate of a high-speed differential pair is generally above 20MHz, with one cycle lasting 50 nanoseconds, far exceeding the switching time of gas discharge tubes and glass discharge tubes. Assuming a 1-microsecond activation time, by the time the device activates, at least 20 bits of data have already been transmitted on the high-speed differential pair signal line. Adding the recovery time of the gas discharge tube or glass discharge tube, this leads to significant data loss, severely impacting signal transmission.

[0005] While high-speed differential pair signal lightning protection circuits using semiconductor discharge tubes offer excellent protection for high-speed signal lines due to the extremely short response time of the tubes and the high consistency of response times between devices (typically in the picosecond range), and the good self-clamping effect, differences in the electrical performance of the protection devices between the positive and negative terminals of the high-speed differential pair signal and the ground can still lead to inconsistent clamping voltages, potentially causing signal transmission errors. Furthermore, semiconductor discharge tubes have relatively large parasitic capacitances; a typical parasitic capacitance of a 6V P0800SC semiconductor discharge tube is around 82pF. This capacitance value significantly impacts signal transmission, affecting factors such as… Figure 4 As shown, the use of semiconductor discharge tube devices has a significant impact on the signal integrity of high-speed signal transmission. The signal changes from a square wave to a sawtooth wave or a triangular wave, and the signal has been severely distorted. Summary of the Invention

[0006] The purpose of this invention is to provide a differential pair signal lightning suppression chip, which solves the problems of inconsistent clamping at the differential terminals and large parasitic capacitance of the semiconductor discharge tube in the prior art.

[0007] Another object of the present invention is to provide a method for manufacturing a differential pair signal lightning suppression chip.

[0008] The first technical solution adopted in this invention is a differential pair signal lightning suppression chip, including a packaging substrate, on which a silicon wafer is disposed. The bottom surface of the silicon wafer is connected to the packaging substrate by conductive adhesive or solder. The silicon wafer integrates a first diode, a second diode, a third diode, and a fourth diode that form a rectifier bridge. The first diode, the second diode, the third diode, and the fourth diode are connected to the pins on the packaging substrate by bonding wires. The silicon wafer also integrates a transient suppression diode, which is connected to the packaging substrate and also to the first diode, the second diode, the third diode, and the fourth diode.

[0009] The first technical solution of the present invention is further characterized in that, The rectifier bridge is connected as follows: the anode of the second diode is connected to the cathode of the fourth diode, and the anode of the first diode is connected to the cathode of the third diode; the cathodes of the first and second diodes converge and are connected to the cathode of the transient suppression diode, and the anodes of the third and fourth diodes converge and are connected to the anode of the transient suppression diode.

[0010] The anode of the first diode and the cathode of the third diode, as well as the anode of the second diode and the cathode of the fourth diode, form pads that are connected to the pins on the package substrate via bonding wires.

[0011] The packaging substrate has pins a, b, c, d, e, and f. Pins a and f are connected to the pads formed by the anode of the second diode and the cathode of the fourth diode via bonding wires; pins c and d are connected to the pads formed by the anode of the first diode and the cathode of the third diode via bonding wires.

[0012] The packaging substrate is provided with a heat sink pad. The anode of the transient suppression diode is connected to the heat sink pad through conductive glue or solder. The heat sink pad is connected to pin b and pin e to dissipate the heat generated when the silicon wafer is working.

[0013] The packaging substrate is wrapped with molding compound.

[0014] The second technical solution adopted in this invention is a method for manufacturing a differential pair signal lightning suppression chip, comprising the following steps: S1, Select a P-type semiconductor silicon wafer as the chip substrate, etch and implant N-type semiconductor material in the middle region of the P-type semiconductor silicon wafer to form the PN junction of the transient suppression diode; S2, etching and implantation are performed on both sides of the transient suppression diode on the silicon wafer to form the PN junction of the first diode, the second diode, the third diode, and the fourth diode; S3, metallize the front and bottom surfaces of the silicon wafer respectively, and connect the metallized bottom surface of the silicon wafer to the packaging substrate; S4 connects the bonding pads formed after the front side of the silicon wafer is metallized to the pins of the packaging substrate through bonding wires, so that the bonding pads and pins are electrically connected. S5, wrap the outer side of the encapsulation substrate with molding compound and cure the molding compound.

[0015] The second technical solution of the present invention is further characterized in that, The specific steps for forming the PN junctions of the first diode, second diode, third diode, and fourth diode in step S2 are as follows: S201, N-type semiconductor material is injected into the etched area on one side of the transient suppression diode to form the PN junction of the third diode. After etching the area adjacent to the third diode, oxidation treatment is performed to form a silicon dioxide isolation insulating layer. Then, P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of the first diode. S202, N-type semiconductor material is injected into the etched area on the other side of the transient suppression diode to form the PN junction of the fourth diode; after etching the area adjacent to the fourth diode, oxidation treatment is performed to form a silicon dioxide isolation insulating layer, and then P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of the second diode.

[0016] Step S3 is as follows: S301, on the front side of the silicon wafer, the anode of the second diode and the cathode of the fourth diode are connected by metallization to form the first pad; the anode of the first diode and the cathode of the third diode are connected by metallization to form the second pad; S302, the bottom surface of the silicon wafer is metallized as a whole to form a bottom electrode. The bottom electrode is electrically connected to the anode of the transient suppression diode, the anode of the third diode, and the anode of the fourth diode to form a bottom surface pad of the silicon wafer. S303 connects the bottom pads of the silicon wafer to the heat sink pads on the packaging substrate using conductive adhesive or solder.

[0017] In step S4, the connection between the bonding pads formed after metallizing the front side of the silicon wafer and the pins of the packaging substrate using bonding wires is specifically as follows: The first pad is connected to pins a and f on the package substrate using bonding wires. Pins a and f are connected to the positive terminals of the differential pair signal of the high-speed signal. Connect the second pad to pins c and d on the package substrate. Pins c and d are connected to the negative terminals of the differential pair signal of the high-speed signal.

[0018] The beneficial effects of this invention are: (1) The differential pair signal lightning suppression chip of the present invention uses the Zener breakdown effect or avalanche breakdown effect of semiconductor silicon material to replace the traditional gas discharge principle. It does not need to rely on gas glow discharge to achieve protection. On the one hand, it greatly speeds up the protection response speed and can quickly clamp the transient interference voltage of lightning, avoiding data packet loss due to response lag. On the other hand, the doping concentration and film thickness are precisely controlled during the silicon wafer manufacturing process, which can ensure that the clamping characteristics of the positive and negative terminals of the differential pair signal are highly consistent, eliminating the risk of signal transmission error. Moreover, there is no problem of gas molecule structure change, achieving long-term stable protection and breaking through the life limit of traditional gas discharge devices.

[0019] (2) The differential pair signal lightning suppression chip of the present invention integrates the protection circuit into a single chip through integrated circuit technology. Compared with discrete semiconductor discharge tubes, it not only significantly reduces parasitic capacitance and avoids high-speed signal distortion caused by excessive parasitic capacitance, but also effectively ensures the integrity of high-speed differential signal transmission. At the same time, a single chip can realize the protection of one differential pair signal without the need for multiple devices to be combined, which significantly improves the integration, reduces the space occupied by the protection device, optimizes the convenience of subsequent wiring and mounting, and is also more conducive to controlling the impedance characteristics of high-speed signals.

[0020] (3) The integrated design of the differential pair signal lightning suppression chip of the present invention makes the protection device smaller and lighter, eliminating the need for complex discrete device layout and simplifying the overall design process of the high-speed differential signal protection system; and because of its high protection performance consistency and long lifespan, it can reduce the frequency of device replacement during later maintenance, thereby reducing maintenance costs and operational pressure in long-term applications.

[0021] (4) The present invention adopts a substrate-type packaging combined with plastic encapsulation design. Compared with the traditional discrete device assembly scheme, it can effectively isolate the influence of complex external environmental factors and can stably adapt to extreme climate scenarios such as low temperature, high temperature, high humidity, and low air pressure, avoiding fluctuations in protection performance caused by environmental interference. Attached Figure Description

[0022] Figure 1 This is a lightning protection circuit diagram for high-speed differential pair signals using gas discharge tubes or glass discharge tubes. Figure 2 This is a lightning protection circuit diagram for high-speed differential pair signals using semiconductor discharge tubes; Figure 3 This is a graph showing the effect of a gas discharge tube on a signal at a frequency of 100MHz. Figure 4 This is a diagram showing the effect of a semiconductor discharge tube on a signal at a frequency of 100MHz. Figure 5 This is a schematic diagram of the differential pair signal lightning suppression chip of the present invention; Figure 6 This is a circuit diagram of the differential pair signal lightning suppression chip of the present invention; Figure 7 This is a lightning protection circuit diagram of the differential pair signal lightning suppression chip of the present invention; Figure 8 This is the current-voltage characteristic curve of a semiconductor discharge tube; Figure 9 This is a graph showing the current-voltage characteristic of the differential pair signal lightning suppression chip of this invention. Figure 10 This is a schematic diagram of the side structure of the silicon wafer in the differential pair signal lightning suppression chip of the present invention; Figure 11 This is a top view of the silicon wafer in the differential pair signal lightning suppression chip of the present invention.

[0023] In the figure, 1. silicon wafer, 2. bonding wire, 3. molding compound, 4. packaging substrate, 5. pin a, 6. pin b, 7. pin c, 8. pin d, 9. pin e, 10. pin f, 11. first diode, 12. second diode, 13. third diode, 14. fourth diode, 15. transient suppression diode. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Example 1 This invention relates to a differential pair signal lightning suppression chip, such as... Figure 5 As shown, the package includes a packaging substrate 4, on which a silicon wafer 1 is disposed. The silicon wafer 1 serves as the core functional carrier of the chip and is tightly assembled in the preset mounting area of ​​the packaging substrate 4. The bottom surface of the silicon wafer 1 is connected to the packaging substrate 4 by conductive adhesive or solder. By means of the conductive properties of the conductive adhesive or solder, an electrical path is constructed between the silicon wafer 1 and the packaging substrate 4.

[0026] The silicon wafer 1 integrates a first diode 11, a second diode 12, a third diode 13, and a fourth diode 14 that form a rectifier bridge. The core function of the rectifier bridge is to regulate the current direction of the high-speed differential pair signal, adapt to the signal transmission requirements of different polarities, and provide a directional conduction path for lightning transient interference current.

[0027] The first diode 11, the second diode 12, the third diode 13, and the fourth diode 14 are connected to the pins on the packaging substrate 4 via bonding wire 2. The bonding wire 2 serves as a flexible conductive connector, precisely bonding between the metallized pads of each diode on the silicon wafer 1 and the pins of the packaging substrate 4.

[0028] The silicon wafer 1 also integrates a transient suppression diode 15 that performs lightning transient suppression. On the one hand, the transient suppression diode 15 is electrically connected to the packaging substrate 4 and can conduct lightning interference current to the external grounding structure through the packaging substrate 4. On the other hand, the transient suppression diode 15 is also connected to the first diode 11, the second diode 12, the third diode 13, and the fourth diode 14 that form the rectifier bridge.

[0029] Furthermore, to ensure the stable operation of the chip in complex environments, the packaging substrate 4 is also completely wrapped with molding compound 3: the molding compound 3 completely covers the top surface, sides and all exposed areas of the silicon wafer 1 and bonding wire 2 of the packaging substrate 4, forming a sealed protective layer.

[0030] Example 2 This embodiment is based on the above embodiment 1, such as... Figure 6As shown, in this invention, the connection relationship of the rectifier bridge is as follows: the anode of the second diode 12 is connected to the cathode of the fourth diode 14, and the anode of the first diode 11 is connected to the cathode of the third diode 13; the cathodes of the first diode 11 and the second diode 12 converge and are connected to the cathode of the transient suppression diode 15, and the anodes of the third diode 13 and the fourth diode 14 converge and are connected to the anode of the transient suppression diode 15.

[0031] Furthermore, the anode of the first diode 11 and the cathode of the third diode 13, the anode of the second diode 12 and the cathode of the fourth diode 14 respectively form pads and are connected to the pins on the package substrate 4 via bonding wire 2.

[0032] Furthermore, combined Figure 5 and Figure 6 As shown, the packaging substrate 4 is provided with pins a5, b6, c7, d8, e9 and f10; Pins a5 and f10 are connected to the pads formed by the anode of the second diode 12 and the cathode of the fourth diode 14 via bonding wire 2; pins c7 and d8 are connected to the pads formed by the anode of the first diode 11 and the cathode of the third diode 13 via bonding wire 2.

[0033] Furthermore, such as Figure 7 As shown, pins a5 and f10 are connected to the positive terminal of the differential pair signal of the high-speed signal, and pins c7 and d8 are connected to the negative terminal of the differential pair signal of the high-speed signal.

[0034] Furthermore, the packaging substrate 4 used in this embodiment has a built-in heat sink pad. The anode of the transient suppression diode 15 is connected to the heat sink pad through conductive glue or solder. The heat sink pad is connected to pins b6 and e9 to dissipate the heat generated by the silicon wafer 1 during operation.

[0035] The basic principle of gas discharge tubes (GDTs) and glass discharge tubes (SPGs) is that a gas with a specific formula is encapsulated in a ceramic or glass tube, and different electrodes are led out. After glow discharge of the gas inside the tube, the tube conducts and clamps the gas. Due to differences in gas concentration, electrode spacing, sealing, and the degree of gas molecule leakage during use, the electrical performance of discharge tubes varies considerably. Because the gas molecule structure changes after gas discharge, the lifespan of the discharge tube has an upper limit.

[0036] This invention utilizes the Zener breakdown effect or avalanche breakdown effect of semiconductor silicon material, resulting in a faster response speed and the absence of glow discharge gas and glow discharge within the differential pair signal lightning suppression chip. Furthermore, the silicon wafer 1 exhibits precise doping concentration control and high thin-film consistency during fabrication, leading to good clamping consistency between the positive and negative terminals of the finished lightning suppression chip signal differential pair, and good clamping consistency across different differential pairs.

[0037] Currently, existing semiconductor discharge tubes (TSS) are mainly composed of a copper frame, silicon wafer, solder, and molding compound. The front and back sides of the silicon wafer are connected to the copper frame using solder, and a layer of molding compound is applied to the outside. The structure is simple, such as... Figure 2 As shown, a differential pair signal requires protection using two semiconductor discharge tubes. The differential pair signal lightning suppression chip in this embodiment is as follows: Figure 7 As shown, a single differential pair signal can be protected using a single lightning suppression chip.

[0038] Furthermore, the main differences in electrical performance between the differential pair signal lightning suppression chip and the semiconductor discharge tube provided in this embodiment are their different current-voltage characteristic curves and junction capacitances. The current-voltage characteristic curve of the semiconductor discharge tube is shown below. Figure 8 As shown, the current of the semiconductor discharge tube increases with increasing voltage. When the voltage reaches a certain value, the current increases sharply and then turns downward. The voltage decreases to a lower voltage value after the voltage turns downward as the current increases. Figure 8 The first quadrant shows the positive voltage versus current curve, while the third quadrant shows the negative voltage versus current curve. The absolute values ​​of voltage and current in the first and third quadrant graphs are almost the same.

[0039] like Figure 9 The figure shows the volt-ampere characteristic curve of the differential pair signal lightning suppression chip in this embodiment. In the first quadrant, it can be seen that as the voltage increases, the current gradually increases as well. When the voltage reaches the turn-on voltage of the lightning suppression chip, the current flow increases exponentially, but unlike the curve of the semiconductor discharge tube, there is no inflection point. In the third quadrant, as the voltage increases in the opposite direction, the current increases exponentially, and the absolute values ​​of voltage and current are different from those in the first quadrant. Therefore, it is evident that the volt-ampere characteristic curves of the semiconductor discharge tube and the differential pair signal lightning suppression chip of this invention are different. The semiconductor discharge tube is non-polarized during use, while the differential pair signal lightning suppression chip has designated pins during use.

[0040] Furthermore, the DC operating voltage and power of the differential pair signal lightning suppression chip of this invention are close to those of the semiconductor discharge tube, specifically the P0080SC model. The typical junction capacitance of the P0080SC semiconductor discharge tube is 80pF, while the typical line-to-ground junction capacitance of the differential pair signal lightning suppression chip is 30pF; the typical line-to-line junction capacitance is 15pF. This demonstrates that the capacitance value of the differential pair signal lightning suppression chip of this invention is significantly smaller than that of existing semiconductor discharge tubes. This avoids high-speed signal distortion caused by excessive parasitic capacitance and effectively ensures the integrity of high-speed differential signal transmission.

[0041] Example 3 The present invention discloses a method for manufacturing a differential pair signal lightning suppression chip, comprising the following steps: S1, as Figure 10 As shown, a P-type semiconductor silicon wafer is selected as the chip substrate. An N-type semiconductor material is implanted into the middle region of the P-type semiconductor silicon wafer to form the PN junction of the transient suppression diode 15. Specifically, before etching the P-type semiconductor silicon wafer, the surface of the silicon wafer 1 needs to be pretreated to remove impurities and oxide layers. The pretreatment includes degreasing cleaning, acid washing, pure water rinsing and drying in sequence. A dilute hydrochloric acid solution is used during acid washing to remove metal impurities and natural oxide layers from the surface of the P-type semiconductor silicon wafer.

[0042] S2, etching and implantation are performed on both sides of the transient suppression diode 15 on the silicon wafer 1 to form the PN junction of the first diode 11, the second diode 12, the third diode 13, and the fourth diode 14; S3, metallize the front and bottom surfaces of silicon wafer 1 respectively, and connect the metallized bottom surface of silicon wafer to the packaging substrate 4; S4, the bonding wire 2 is used to connect the pads formed after the front side of the silicon wafer 1 is metallized to the pins of the packaging substrate 4, so that the bonding pads and pins are electrically connected. S5, the molding compound 3 is wrapped around the outside of the packaging substrate and cured. After the molding compound 3 is cured, the chip mark is printed on the surface of the molding compound 3 to complete the manufacturing of the differential pair signal lightning suppression chip.

[0043] Example 4 Based on Embodiment 3 above, the specific steps in step S2 of the manufacturing method of the differential pair signal lightning suppression chip of the present invention for forming the PN junction of the first diode 11, the second diode 12, the third diode 13, and the fourth diode 14 are as follows: S201, N-type semiconductor material is injected into the etched area on one side of transient suppression diode 15 to form the PN junction of third diode 13. After etching the area adjacent to third diode 13, oxidation treatment is performed to form silicon dioxide isolation insulating layer. Then, P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of first diode 11. Specifically, when etching the area adjacent to the third diode 13, the etched area should be larger than the area of ​​the third diode 13. This is to facilitate the formation of the silicon dioxide isolation insulating layer and to ensure that after the P-type semiconductor material is implanted, there is still enough area to implant the N-type semiconductor material to form the PN junction of the first diode 11.

[0044] S202, N-type semiconductor material is injected into the etched area on the other side of transient suppression diode 15 to form the PN junction of the fourth diode 14; after etching the area adjacent to the fourth diode 14, oxidation treatment is performed to form a silicon dioxide isolation insulating layer, and then P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of the second diode 12.

[0045] Similarly, when etching the area adjacent to the fourth diode 14, the etched area should be larger than the area of ​​the fourth diode 14. This is to facilitate the later formation of the silicon dioxide isolation insulating layer and to ensure that after the P-type semiconductor material is implanted, there is still enough area to implant the N-type semiconductor material to form the PN junction of the second diode 12.

[0046] In this embodiment, when fabricating the first diode 11, the second diode 12, the third diode 13, and the fourth diode 14, the parasitic capacitance of the silicon wafer 1 can be reduced by controlling the reduction of the area of ​​the diode PN junction, thus satisfying the control of parasitic capacitance on the signal line.

[0047] Furthermore, during the implantation of N-type semiconductor material, the breakdown characteristics of the PN junction of the transient suppression diode 15 can be modulated by controlling the doping concentration of the N-type semiconductor material. When the N-type semiconductor doping concentration is high, the depletion layer of the PN junction is thinner, making Zener breakdown more likely, resulting in a lower breakdown voltage and higher clamping accuracy. When the doping concentration is low, the depletion layer is thicker, making avalanche breakdown more likely, resulting in a higher breakdown voltage and stronger current dissipation capability. By controlling the doping concentration, the protection requirements of high-speed differential signals can be precisely matched, and the turn-on voltage and clamping threshold can be set to suit the application scenario, avoiding the problem of insufficient protection due to excessively high breakdown voltage or the impact on normal signal transmission due to excessively low breakdown voltage.

[0048] Furthermore, controlling the uniformity of N-type semiconductor doping concentration can ensure that the PN junction characteristics of transient suppression diode 15 are consistent in the same silicon wafer and different batches of chips, enabling synchronous clamping of the positive and negative terminals of the differential pair signal and improving the consistency of protection effect.

[0049] In this embodiment, etching, control of N-type semiconductor doping concentration, and oxidation treatment are all existing mature technologies, and will not be described in detail in this embodiment.

[0050] Example 5 Based on Embodiment 3 above, step S3 of the manufacturing method of the differential pair signal lightning suppression chip of the present invention specifically includes: S301, such as Figure 11 As shown, on the front side of silicon wafer 1, metallization is performed using sputtering or evaporation processes to connect the anode of the second diode 12 and the cathode of the fourth diode 14 through metallization to form the first pad PAD1; and the anode of the first diode 11 and the cathode of the third diode 13 are connected through metallization to form the second pad PAD2. Furthermore, the first pad PAD1 serves as the access interface for the positive terminal of the high-speed differential pair signal, and the second pad PAD2 serves as the access interface for the negative terminal of the high-speed differential pair signal. Both need to have their edges trimmed through photolithography and etching processes to ensure that the shape and size of the pads are compatible with the subsequent bonding wire connection requirements, and to avoid bonding problems caused by edge burrs or defects.

[0051] S302, the bottom surface of silicon wafer 1 is metallized as a whole to form a bottom electrode. The bottom electrode is electrically connected to the anode of transient suppression diode 15, the anode of third diode 13, and the anode of fourth diode 14 to form a silicon wafer bottom pad PAD. Furthermore, the pads on the bottom surface of the silicon wafer serve two purposes: first, as a discharge channel for lightning transient interference current, the interference current is conducted to the external grounding structure through subsequent connection with the packaging substrate 4; second, as an electrical connection interface between the silicon wafer 1 and the packaging substrate 4, ensuring that the protection circuit formed by the rectifier bridge and the transient suppression diode 15 can achieve a complete current loop through the bottom surface, while providing a conduction path for heat dissipation of the silicon wafer 1.

[0052] S303 connects the bottom pads of the silicon wafer to the heat sink pads on the packaging substrate 4 using conductive adhesive or solder.

[0053] Furthermore, the packaging substrate 4 is selected to have heat sink pads. The bottom electrode of the silicon wafer is attached to the heat sink pads of the packaging substrate 4 with conductive adhesive or solder. The conductive adhesive or solder is heated and cured according to the curing process to achieve the fixation and electrical connection between the silicon wafer 1 and the packaging substrate 4.

[0054] Example 6 Based on Embodiment 3 above, in step S4 of the manufacturing method of the differential pair signal lightning suppression chip of the present invention, the connection between the bonding pads formed after the front side of the silicon wafer 1 is metallized and the pins of the packaging substrate 4 via the bonding wire 2 is specifically as follows: The first pad PAD1 is connected to pins a5 and f10 on the package substrate 4 using bonding wire 2. Pins a5 and f10 are connected to the positive terminal of the differential pair signal of the high-speed signal. Connect the second pad PAD2 to pins c7 and d8 on the package substrate 4. Pins c7 and d8 are connected to the negative terminals of the differential pair signal of the high-speed signal.

[0055] Furthermore, the bonding wire 2 is made of gold or copper wire, and the bonding process uses ultrasonic bonding technology to ensure the bonding strength between the bonding wire 2 and the pads and the pins of the packaging substrate, and to avoid poor soldering or desoldering.

[0056] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0057] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A differential pair signal lightning suppression chip, characterized in that, The package includes a packaging substrate (4), on which a silicon wafer (1) is disposed. The bottom surface of the silicon wafer (1) is connected to the packaging substrate (4) by conductive adhesive or solder. The silicon wafer (1) integrates a first diode (11), a second diode (12), a third diode (13), and a fourth diode (14) that form a rectifier bridge. The first diode (11), the second diode (12), the third diode (13), and the fourth diode (14) are connected to the pins on the packaging substrate (4) by bonding wires (2). A transient suppression diode (15) is also integrated on the silicon wafer (1). The transient suppression diode (15) is connected to the packaging substrate (4) and is also connected to the first diode (11), the second diode (12), the third diode (13), and the fourth diode (14).

2. The differential pair signal lightning suppression chip according to claim 1, characterized in that, The rectifier bridge is connected as follows: the anode of the second diode (12) is connected to the cathode of the fourth diode (14), and the anode of the first diode (11) is connected to the cathode of the third diode (13); the cathodes of the first diode (11) and the second diode (12) converge and are connected to the cathode of the transient suppression diode (15); the anodes of the third diode (13) and the fourth diode (14) converge and are connected to the anode of the transient suppression diode (15).

3. The differential pair signal lightning suppression chip according to claim 2, characterized in that, The anode of the first diode (11) and the cathode of the third diode (13), the anode of the second diode (12) and the cathode of the fourth diode (14) respectively form pads and are connected to the pins on the packaging substrate (4) by bonding wire (2).

4. The differential pair signal lightning suppression chip according to claim 3, characterized in that, The packaging substrate (4) is provided with pins a (5), b (6), c (7), d (8), e (9) and f (10). Pins a (5) and f (10) are connected to the pads formed by the anode of the second diode (12) and the cathode of the fourth diode (14) via bonding wire (2); pins c (7) and d (8) are connected to the pads formed by the anode of the first diode (11) and the cathode of the third diode (13) via bonding wire (2).

5. The differential pair signal lightning suppression chip according to claim 4, characterized in that, The packaging substrate (4) is provided with a heat sink pad. The anode of the transient suppression diode (15) is connected to the heat sink pad through conductive glue or solder. The heat sink pad is connected to pin b (6) and pin e (9) to dissipate the heat generated by the silicon wafer (1) during operation.

6. The differential pair signal lightning suppression chip according to claim 1, characterized in that, The packaging substrate (4) is wrapped with a molding compound (3).

7. A method for manufacturing a differential pair signal lightning suppression chip, comprising the following steps: S1, select a P-type semiconductor silicon wafer as the chip substrate, etch and implant N-type semiconductor material in the middle region of the P-type semiconductor silicon wafer to form the PN junction of the transient suppression diode (15); S2, etching and implantation are performed on both sides of the transient suppression diode (15) on the silicon wafer (1) to form the PN junction of the first diode (11), the second diode (12), the third diode (13), and the fourth diode (14); S3, the front and bottom surfaces of the silicon wafer (1) are metallized respectively, and the bottom surface of the metallized silicon wafer is connected to the packaging substrate (4); S4, the bonding pads formed after the front side of the silicon wafer (1) is metallized are connected to the pins of the packaging substrate (4) by bonding wire (2) so that the bonding pads and pins are electrically connected; S5, wrap the molding compound (3) around the outside of the packaging substrate and cure the molding compound (3).

8. The method for manufacturing a differential pair signal lightning suppression chip according to claim 7, wherein the formation of the PN junction of the first diode (11), the second diode (12), the third diode (13), and the fourth diode (14) in step S2 is specifically as follows: S201, N-type semiconductor material is injected into the etched area on one side of the transient suppression diode (15) to form the PN junction of the third diode (13). After etching the area adjacent to the third diode (13), oxidation treatment is performed to form a silicon dioxide isolation insulating layer. Then, P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of the first diode (11). S202, N-type semiconductor material is injected into the etched area on the other side of the transient suppression diode (15) to form the PN junction of the fourth diode (14); After etching the area adjacent to the fourth diode (14), an oxidation process is performed to form a silicon dioxide isolation insulating layer. Then, P-type semiconductor material is injected into the isolation insulating layer. Subsequently, the P-type semiconductor material is etched and N-type semiconductor material is injected to form the PN junction of the second diode (21).

9. The method for manufacturing a differential pair signal lightning suppression chip according to claim 7, wherein step S3 specifically comprises: S301, on the front side of the silicon wafer (1), the anode of the second diode (12) and the cathode of the fourth diode (14) are connected by metallization to form the first pad; the anode of the first diode (11) and the cathode of the third diode (13) are connected by metallization to form the second pad; S302, the bottom surface of the silicon wafer (1) is metallized as a whole to form a bottom electrode. The bottom electrode is electrically connected to the anode of the transient suppression diode (15), the anode of the third diode (13), and the anode of the fourth diode (14) to form a bottom pad of the silicon wafer. S303, the bottom pads of the silicon wafer are connected to the heat sink pads on the packaging substrate (4) using conductive adhesive or solder.

10. The method for manufacturing a differential pair signal lightning suppression chip according to claim 9, wherein in step S4, the connection of the bonding pads formed after the front side of the silicon wafer (1) is metallized with bonding wire (2) to the pins of the packaging substrate (4) is specifically as follows: The first pad is connected to pin a (5) and pin f (10) on the packaging substrate (4) using bonding wire (2). Pin a (5) and pin f (10) are connected to the positive terminal of the differential pair signal of the high-speed signal. Connect the second pad to pins c (7) and d (8) on the package substrate (4), and pins c (7) and d (8) are connected to the negative terminal of the differential pair signal of the high-speed signal.

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