TBC battery structure and preparation method thereof, and TBC battery

Abstract

The invention discloses a TBC battery structure, a preparation method thereof and a TBC battery, in the structure, a P region and an N region are respectively provided with a P-type / N-type doped polycrystalline silicon passivation layer, and an oxygen-doped polycrystalline silicon layer is arranged between the P region and the N region. The preparation method comprises the step of preparing the P-type / N-type doped polycrystalline silicon passivation layer and the oxygen-doped polycrystalline silicon layer on the P region and the N region. In the structure, the oxygen-doped polycrystalline silicon layer is arranged between the P region and the N region, so that the P region and the N region can be effectively separated, an excellent shadow shielding resisting function of a corresponding assembly can be realized, and the generating capacity of the assembly in a shadow shielding environment can be further improved. According to the preparation method, the design of depositing multiple tunneling oxide layers and polycrystalline silicon layers at a time, the design of a laminated mask, a new isolation mode, an efficient cleaning process and the like are adopted, the problems that an existing TBC battery preparation process is tedious, boron-doped polycrystalline silicon laser ablation residues exist, the investment and generation cost is high and the like are effectively solved, and the preparation method is a brand-new TBC battery route.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, and relates to a TBC cell structure and its preparation method, and a TBC cell. Background Technology

[0002] TBC (Tunneling Oxide Passivated Contact Back Contact Cell) is a new generation of high-efficiency N-type photovoltaic cell technology. Its core design combines the high carrier selective passivation advantage of Tunneling Oxide Passivated Contact Cell (TOPCon) with the back electrode structure characteristics of back contact (BC) cells. By completely transferring the electrode pattern to the back side, an unshaded area is achieved on the front side, maximizing the light absorption area to increase the short-circuit current (Isc). At the same time, the passivation contact interface formed by the ultra-thin tunneling oxide layer (SiO2) and the doped polycrystalline silicon layer in the TOPCon structure is used to reduce the surface passivation rate and obtain a high open-circuit voltage (Voc).

[0003] The general fabrication process of current TBC cells is as follows: First, a tunneling oxide layer and intrinsic polysilicon are deposited on the back side of a polished N-type silicon wafer. Then, high-temperature boron diffusion is performed to form a boron-doped polysilicon layer and a borosilicate glass (BSG) layer, which serves as a mask for subsequent processes. Next, a first laser is used to pattern the BSG mask, exposing the boron-doped polysilicon layer. The exposed boron-doped polysilicon layer and the underlying tunneling oxide layer are removed by wet etching. The untreated BSG mask protects the boron-doped polysilicon and tunneling oxide layer in its covered area from damage. Then, a tunneling oxide layer and intrinsic polysilicon layer are deposited on the back side of the silicon wafer using LPCVD equipment, followed by phosphorus diffusion to form a phosphorus-doped polysilicon layer and a phosphorus-silicon glass (PSG) layer. A second laser is used to remove the boron-doped polysilicon and the PSG layer directly above the gap region (GAP) patterned area. Wet etching is then performed on both sides of the silicon wafer to complete the wraparound plating and removal of exposed polysilicon, front-side texturing, and mask (BSG and PSG) removal, achieving P… Poly and N-poly are isolated; finally, the front and back passivation protective layers are deposited and metallized through processes such as ALD, PECVD, and screen printing. It can be seen that the existing TBC battery manufacturing technology has shortcomings such as complex process, long process time, low production capacity, and low yield. In addition, it requires two LPCVD depositions of tunneling oxide layer + intrinsic polycrystalline silicon, and multiple wet cleaning processes, resulting in high investment and production costs.

[0004] To address the aforementioned issues of complex processes, long processing times, low production capacity, low yield, and high investment and production costs, a method for fabricating TBC cells has been proposed in the prior art. This involves a single LPCVD deposition of a tunneling oxide layer and an intrinsic polycrystalline silicon layer, followed by screen printing of boron paste and phosphorus paste, and then annealing and sintering to form N-type and P-type doped polycrystalline silicon layers. However, the boron and phosphorus paste methods used in this method are not mature, exhibiting poorer results than conventional boron and phosphorus diffusion methods, and requiring specific cleaning techniques, leading to higher material and manufacturing costs. Furthermore, the annealing and sintering method used is insufficient to improve the effective doping concentration and diffusion depth. Simultaneously, in this TBC cell, using intrinsic polycrystalline silicon as the isolation region (GAP) still results in low contact resistance, easily causing short circuits in the N / P region.

[0005] Furthermore, in existing fabrication methods, laser ablation of boron-doped polysilicon easily leads to the formation of molten boron-doped polysilicon residue, requiring wet cleaning. This results in excessive thinning of the silicon wafer edges, increasing the risk of fragmentation and reducing mechanical strength. Simultaneously, the use of a single SiNx or SiO2 mask layer lacks a buffer layer at the polysilicon interface. Using a thick, high-refractive-index SiNx layer as a mask makes thickness control difficult, and the residual SiNx is challenging to clean, requiring high-concentration acid etching, which can lead to uneven corrosion and increased cleaning costs. A single-layer SiO2 mask has poor barrier properties and cannot effectively isolate the high-temperature diffusion of elements such as boron and phosphorus. Furthermore, when using LPCVD to prepare the tunneling oxide layer and polycrystalline silicon layer, a single-slot double-intercalation silicon wafer is used. In this case, the non-coated surfaces of the silicon wafers are not tightly bonded, which inevitably leads to polycrystalline silicon wrapping around the amorphous silicon at the front edge and sides. These wrapping layers have uneven thickness and strong adhesion to the substrate, thus placing higher demands on cleaning. Removing the wrapping layer requires the use of a suitable HF or KOH solution. If the treatment is not appropriate, color differences and black edges on the electroluminescence (EL) may easily occur. If the etching rate is different during cleaning, local over-etching may occur, forming an edge damage layer, which greatly reduces the carrier lifetime and ultimately leads to a significant loss in cell conversion efficiency compared to the theoretical value.

[0006] For the reasons stated above, this invention is proposed. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a TBC battery structure and its preparation method, as well as a TBC battery.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A TBC battery structure includes a silicon substrate, the back side of which includes alternating P-regions and N-regions, a P-type doped polycrystalline silicon passivation layer disposed on the P-region, an N-type doped polycrystalline silicon passivation layer disposed on the N-region, and an isolation region comprising an oxygen-doped polycrystalline silicon layer between the P-regions and the N-region.

[0009] In a further improvement to the aforementioned TBC battery structure, the oxygen surface doping concentration in the oxygen-doped polycrystalline silicon layer is 10. 18 / cm 3 ~10 20 / cm 3 The thickness of the oxygen-doped polycrystalline silicon layer is 30 nm to 240 nm; the width of the oxygen-doped polycrystalline silicon layer is 30 μm to 1000 μm.

[0010] In a further improvement to the aforementioned TBC battery structure, the thickness of the P-type doped polycrystalline silicon passivation layer is 65 nm to 220 nm; the P-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first boron-doped polycrystalline silicon film, a second SiO2 film, and a second boron-doped polycrystalline silicon film; the boron doping concentration in the first boron-doped polycrystalline silicon film is lower than that in the second boron-doped polycrystalline silicon film; the boron doping concentration in the first boron-doped polycrystalline silicon film exhibits a gradient distribution; and the boron doping concentration in the second boron-doped polycrystalline silicon film is 1 × 10⁻⁶. 19 / cm 3 ~3×10 20 / cm 3 The thickness of the first boron-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; and the thickness of the second boron-doped polycrystalline silicon film is 60 nm to 160 nm.

[0011] In a further improvement to the aforementioned TBC battery structure, the thickness of the N-type doped polycrystalline silicon passivation layer is 65 nm to 240 nm; the N-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first phosphorus-doped polycrystalline silicon film, a second SiO2 film, and a second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film is lower than that in the second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film exhibits a gradient distribution; and the phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon film is 1 × 10⁻⁶. 20 / cm 3 ~1×10 21 / cm 3 The thickness of the first phosphorus-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; and the thickness of the second phosphorus-doped polycrystalline silicon film is 60 nm to 180 nm.

[0012] In a further improvement to the aforementioned TBC battery structure, the silicon substrate comprises an N-type silicon wafer; the resistivity of the N-type silicon wafer is 1 Ω·cm to 50 Ω·cm.

[0013] As a general technical concept, the present invention also provides a method for preparing a TBC battery structure, comprising the following steps: S1. Pre-treat the silicon substrate; S2. Tunneling oxide films and intrinsic polycrystalline silicon films are alternately deposited on the back side of a silicon substrate to form a tunneling oxide / intrinsic polycrystalline silicon passivation stack; the tunneling oxide / intrinsic polycrystalline silicon passivation stack consists of, from the inside out, a first tunneling oxide film, a first intrinsic polycrystalline silicon film, a second tunneling oxide film, a second intrinsic polycrystalline silicon film, a third tunneling oxide film, and a third intrinsic polycrystalline silicon film; S3. Sequentially deposit a silicon dioxide thin film and a silicon nitride thin film on the back side of the silicon substrate to form a silicon dioxide / silicon nitride stacked mask layer; S4. Laser grooving is performed on the back side of the silicon substrate to remove the silicon dioxide / silicon nitride stacked mask layer, the third tunneling oxide film, and the third intrinsic polycrystalline silicon film above the preset P area on the back side of the silicon wafer. S5. Boron diffusion and oxidation are performed on the back side of the silicon substrate to form a P-type doped polysilicon passivation layer and a BSG layer in the trench area. The thickness of the BSG layer above the P region is more than 80nm. The silicon nitride mask in the non-P region is oxidized and a boron doped BSG mask layer is formed simultaneously. S6. Laser grooving is performed on the back side of the silicon substrate to remove the BSG mask layer, silicon dioxide mask layer, third intrinsic polycrystalline silicon thin film, and third tunneling oxide thin film above the preset N region on the back side of the silicon wafer. S7. Phosphorus diffusion and oxidation are performed on the back side of the silicon substrate to form an N-type doped polysilicon passivation layer and a PSG layer in the trench area, and a BPSG layer is formed on the surface of the non-N region. S8. Perform chain cleaning on the back of the silicon substrate to remove the BPSG layer and silicon dioxide stacked mask layer on the front and sides. S9. Perform a tank cleaning on the silicon substrate to remove the tunneling oxide / intrinsic polysilicon passivation stack on the front edge and side. S10. Acid pickling is performed on the front side of the silicon substrate to remove the BPSG layer, PSG layer and silicon dioxide mask layer on the back side.

[0014] In a further improvement to the above preparation method, step S1 includes the following pretreatment: pre-cleaning, alkaline texturing, polishing, post-cleaning, water washing, and drying of the silicon substrate; the alkaline solution used in the polishing process is either KOH or NaOH; the mass concentration of the alkaline solution is 3%–5%; the polishing is performed at a temperature of 30°C–98°C; the polishing time is 100s–600s; and the cleaning is performed in a tank cleaning machine to remove the cutting damage layer on the surface.

[0015] In a further improvement to the above preparation method, in step S2, a tunneling oxide film and an intrinsic polycrystalline silicon film are alternately deposited on the back side of a silicon substrate using an LPCVD device, or a tunneling oxide film and an intrinsic polycrystalline silicon film are alternately deposited on the back side of a silicon substrate using a PECVD method combined with boron diffusion. When alternatingly depositing the tunneling oxide film and the intrinsic polycrystalline silicon film on the back side of a silicon substrate using an LPCVD device, the deposition process parameters for the tunneling oxide film are: the reactant gas is O2, the gas flow rate is 5000 sccm to 20000 sccm, the deposition time is 120 s to 1800 s, and the deposition temperature is 500℃ to 700℃. The deposition process parameters for the intrinsic polycrystalline silicon film are: the reactant gas is SiH4, the gas flow rate is 200 sccm to 20000 sccm. The deposition temperature is 500℃ to 700℃, with a deposition time of 1000s to 2000s and a deposition temperature of 500℃ to 700℃. The thickness of the tunneling oxide / intrinsic polysilicon passivation stack is 100nm to 295nm. The thickness of the first tunneling oxide film is 1nm to 2.5nm. The thickness of the first intrinsic polysilicon film is 5nm to 60nm. The thickness of the second tunneling oxide film is 0.3nm to 2nm. The thickness of the second intrinsic polysilicon film is 80nm to 200nm. The thickness of the third tunneling oxide film is 1.5nm to 3nm. The thickness of the third intrinsic polysilicon film is 10nm to 30nm. The first tunneling oxide film, the second tunneling oxide film, and the third tunneling oxide film are all SiO2 films.

[0016] In a further improvement to the above preparation method, in step S3, a silicon dioxide thin film and a silicon nitride thin film are sequentially deposited on the back side of a silicon substrate using a PECVD device. The deposition process parameters for the silicon dioxide thin film are: the reactant gases are SiH4 and N2O, the flow rate of SiH4 is 100 sccm to 1000 sccm, the flow rate of N2O is 3000 sccm to 12000 sccm, the RF power is 6000 W to 18000 W, and the deposition temperature is 350℃ to 550℃. The deposition process parameters for the silicon nitride thin film are: the reactant gases are SiH4 and NH3, the flow rate of SiH4 is 100 sccm to 1000 sccm, the flow rate of NH3 is 3000 sccm to 12000 sccm, the RF power is 6000 W to 18000 W, and the deposition temperature is 350℃ to 550℃. The thickness of the silicon dioxide / silicon nitride stacked mask layer is 60 nm to 210 nm. nm; the thickness of the silicon dioxide film is 30 nm to 90 nm, and the thickness of the silicon nitride film is 30 nm to 120 nm; the refractive index of the silicon nitride film is 2.1 to 2.3; In a further improvement to the above preparation method, in step S4, the laser grooving linewidth is 60μm to 1000μm.

[0017] In a further improvement to the above preparation method, in step S5, a diffusion furnace is used to perform boron diffusion and oxidation on the back side of the silicon substrate; the process parameters for the boron diffusion are: temperature 960℃~1050℃, reaction source BCl3 and O2, BCl3 flow rate 200 sccm~500 sccm, O2 flow rate 10000 sccm~30000 sccm; and the thickness of the BSG mask layer is 80 nm~130 nm.

[0018] In a further improvement to the above preparation method, in step S6, the laser grooving linewidth is 60μm to 800μm.

[0019] In a further improvement to the above preparation method, in step S7, a diffusion furnace is used to perform phosphorus diffusion on the back side of the silicon substrate; the process parameters for phosphorus diffusion are: temperature 800℃~950℃, phosphorus source is POCl3, time is 1000s~2400s, O2 flow rate is 10000 sccm~30000 sccm; and the thickness of the PSG layer is 20 nm~60 nm.

[0020] In a further improvement to the above preparation method, in step S8, an HF solution is used to perform a chain cleaning of the back side of the silicon substrate; the mass concentration of the HF solution is 3% to 40%.

[0021] In a further improvement to the above preparation method, in step S9, an alkaline solution is used to perform a tank cleaning of the silicon substrate; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; and the alkaline solution also contains a mask protection additive.

[0022] In a further improvement to the above preparation method, in step S10, the front side of the silicon substrate is acid-washed with an HF solution; the mass concentration of the HF solution is 3% to 40%.

[0023] The above preparation method, in a further improvement, also includes the following steps: S11. Texturing the front side of the silicon substrate to form a pyramidal textured surface structure. S12. Deposit aluminum oxide passivation layers on the front and back sides of the silicon substrate; S13. Deposit a front passivation protective layer and a back passivation protective layer on the front and back sides of the silicon substrate, respectively; S14. Fabricate a metal electrode on the back side of a silicon substrate.

[0024] In a further improvement to the above preparation method, in step S11, an alkaline solution is used to texturize the front side of the silicon substrate; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 1% to 5%; and the alkaline solution also contains a mask protection additive.

[0025] In a further improvement to the above preparation method, in step S12, an aluminum oxide passivation layer is deposited on the front and back sides of a silicon substrate using the ALD method; the deposition process parameters of the aluminum oxide passivation layer are: the aluminum source and oxygen source are trimethylaluminum and pure water, respectively, the process temperature is 250℃~300℃; and the thickness of the aluminum oxide passivation layer is 3 nm~15 nm. In a further improvement to the above preparation method, in step S13, a front passivation protective layer and a back passivation protective layer are deposited on the front and back sides of the silicon substrate using a PECVD device. The deposition process parameters for the front passivation protective layer are: SiH4 flow rate of 1000 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 15000 sccm, and deposition temperature of 380℃ to 500℃. The deposition process parameters for the back passivation protective layer are: SiH4 flow rate of 500 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 18000 sccm, and N2O flow rate of 8000 sccm. The deposition thickness is sccm to 15000 sccm, and the deposition temperature is 380℃ to 500℃; the front passivation protective layer is one of SiNx thin films, SiNOx thin films, and SiOx thin films, or a passivation film formed by stacking them; the total thickness of the front passivation protective layer is 65nm to 85nm, and the refractive index of the front passivation protective layer is 2.0 to 2.2; the back passivation protective layer is a SiNx thin film; the total thickness of the back passivation protective layer is 70nm to 90nm, and the refractive index of the back passivation protective layer is 2.0 to 2.3.

[0026] The above-mentioned preparation method is further improved in step S14, which includes the following steps for preparing a metal electrode on the back side of the silicon substrate: printing silver paste or aluminum paste on the P-region of the back side of the silicon substrate by screen printing, printing silver paste on the N-region, and sintering.

[0027] In a further improvement of the above-described preparation method, the TBC battery structure includes a silicon substrate, the back side of which includes alternating P-regions and N-regions, a P-type doped polycrystalline silicon passivation layer is disposed on the P-region, an N-type doped polycrystalline silicon passivation layer is disposed on the N-region, and an isolation region is disposed between the P-region and the N-region, the isolation region including an oxygen-doped polycrystalline silicon layer.

[0028] A further improvement to the above preparation method is that the oxygen surface doping concentration in the oxygen-doped polycrystalline silicon layer is 10. 18 / cm 3 ~10 20 / cm 3 The thickness of the oxygen-doped polycrystalline silicon layer is 30 nm to 240 nm; the width of the oxygen-doped polycrystalline silicon layer is 30 μm to 1000 μm.

[0029] In a further improvement to the above preparation method, the thickness of the P-type doped polycrystalline silicon passivation layer is 65 nm to 220 nm; the P-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first boron-doped polycrystalline silicon thin film, a second SiO2 thin film, and a second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film is lower than that in the second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film exhibits a gradient distribution; and the boron doping concentration in the second boron-doped polycrystalline silicon thin film is 1 × 10⁻⁶. 19 / cm 3 ~3×10 20 / cm 3 The thickness of the first boron-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; and the thickness of the second boron-doped polycrystalline silicon film is 60 nm to 160 nm.

[0030] In a further improvement to the above preparation method, the thickness of the N-type doped polycrystalline silicon passivation layer is 65 nm to 240 nm; the N-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first phosphorus-doped polycrystalline silicon film, a second SiO2 film, and a second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film is lower than that in the second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film exhibits a gradient distribution; and the phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon film is 1 × 10⁻⁶. 20 / cm 3 ~1×10 21 / cm 3 The thickness of the first phosphorus-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 60 nm to 180 nm. In a further improvement to the above preparation method, the silicon substrate comprises an N-type silicon wafer; the resistivity of the N-type silicon wafer is 1 Ω·cm to 50 Ω·cm.

[0031] As a general technical concept, the present invention also provides a TBC battery, which includes the TBC battery structure described above, or the TBC battery structure prepared by the above preparation method.

[0032] Compared with the prior art, the advantages of the present invention are as follows: (1) In view of the shortcomings of existing TBC batteries, such as low resistivity of the isolation region, and the resulting defects such as easy short circuit in the P and N regions, difficulty in improving the passivation uniformity and adhesion stability of the passivation layer, and difficulty in improving conversion efficiency, this invention creatively provides a TBC battery structure, including a silicon substrate, with alternating P and N regions on the back side of the silicon substrate, a P-type doped polycrystalline silicon passivation layer on the P region, and an N-type doped polycrystalline silicon passivation layer on the N region. The P-type doped polycrystalline silicon passivation layer is a boron doped polycrystalline silicon layer with different diffusion concentrations and different diffusion depths, in the form of a p-poly / ultra-thin SiO2 / p+-poly stacked structure. As the battery emitter, it can effectively control the boron doping concentration and reduce the thickness of the polycrystalline silicon, reduce the parasitic absorption of long-wavelength light by the battery, and improve the battery efficiency. At the same time, the N-type doped polycrystalline silicon passivation layer is used to effectively control the boron doping concentration and reduce the thickness of the polycrystalline silicon, reduce the parasitic absorption of long-wavelength light by the battery, and improve the battery efficiency. The layer is also a phosphorus-doped polycrystalline silicon layer with different diffusion concentrations and diffusion depths, exhibiting an n-poly / ultra-thin SiO2 / n+-poly stacked structure, forming a high-low junction N+ region as the electron collection region of the battery. This effectively controls the phosphorus doping concentration and reduces the thickness of the polycrystalline silicon, thereby reducing the parasitic absorption of long-wavelength light by the battery and improving battery efficiency. It can be seen that the combined effect of the P-type doped polycrystalline silicon passivation layer and the N-type doped polycrystalline silicon passivation layer can significantly improve the efficiency of the battery. More importantly, compared with conventional intrinsic polycrystalline silicon layers, this invention provides an isolation region between the P-region and the N-region, and the isolation region includes an oxygen-doped polycrystalline silicon layer with higher resistivity, which can effectively isolate the P and N regions. By setting the isolation region with a specific width, the corresponding module can achieve excellent anti-shading function, which is beneficial to further improve the power generation of the module in the shaded environment.

[0033] (2) This invention also provides a method for preparing a TBC battery structure. It innovatively proposes a design for depositing a multilayer tunneling oxide layer and a polycrystalline silicon layer in one step, a stacked mask design, a new isolation method, and an efficient cleaning process. This effectively solves the problems of cumbersome existing TBC battery preparation processes, residual boron-doped polycrystalline silicon laser ablation, and high investment and production costs. The stacked mask structure is optimized to improve the mask blocking effect, reduce the cross-regional interdiffusion effect of dopants, and mitigate passivation layer damage. By cleaning in stages to remove PSG, BPSG, silicon oxide, and the polycrystalline silicon layer, the front texturing and back PSG, BPSG, and silicon oxide layer removal are completed. Ultimately, a new breakthrough in TBC battery technology and effective control of production costs are achieved. As a brand-new TBC battery route, it can bring the following unexpected technical effects: (a) It greatly simplifies the TBC cell manufacturing process by replacing the traditional two-stage deposition with a single-stage deposition of a stacked tunneling oxide layer and an intrinsic amorphous silicon structure. This simplifies the process flow (LPCVD, cleaning, and laser), reduces process contamination from secondary deposition, lowers equipment investment and manufacturing costs, and improves product yield.

[0034] (b) The SiO2 / SiNx stacked mask layer prepared by PECVD on the back side effectively blocks the interdiffusion of boron and phosphorus dopants, preventing short circuit leakage in the PN region. At the same time, oxygen-doped polysilicon is generated at the interface between SiO2 and polysilicon in the bottom layer of the mask in the Gap region, which improves the resistivity of the region.

[0035] (c) During the high-temperature treatment of boron and phosphorus diffusion, the mask SiNx is oxidized to form a BPSG layer, which is easier to clean later. The P+ and N+ regions are formed by two precise laser grooving processes. Since the laser consumes the third tunneling oxide film (SiO2) / third intrinsic polycrystalline silicon film (i-poly), the damage of the laser to the silicon substrate is reduced.

[0036] (d) Using oxygen-doped polycrystalline silicon to replace traditional laser physical isolation reduces one laser physical isolation process and lowers equipment investment costs.

[0037] (e) The chain cleaning and tank cleaning processes are adopted. The chain cleaning protects the back side and removes the PSG, BPSG and SiO2 around the front edge. The tank cleaning removes the polycrystalline silicon layer around the edge and then performs texturing on the front side. This can improve the cleaning of the LPCVD secondary deposition and the color difference of the cell appearance. Attached Figure Description

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of the cross-sectional structure of the TBC battery structure in Embodiment 1 of the present invention.

[0040] Figure 2 This is a flowchart illustrating the fabrication process of the TBC battery structure in Embodiment 1 of the present invention.

[0041] Legend: 1. Silicon substrate; 2. Tunneling oxide layer; 3. P-region; 4. N-region; 5. Isolation region; 6. Back passivation layer; 7. Front passivation layer; 8. Electrode. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0043] In the following embodiments of the present invention, unless otherwise specified, the materials and instruments used are commercially available, the equipment used is conventional equipment, and the data obtained are the average values ​​of more than three repeated experiments.

[0044] Example 1: like Figure 1 As shown, a TBC battery structure includes a silicon substrate 1, with alternating P-regions 3 and N-regions 4 on the back side of the silicon substrate 1. A P-type doped polycrystalline silicon passivation layer is disposed on the P-region 3, and an N-type doped polycrystalline silicon passivation layer is disposed on the N-region 5. An isolation region 5 is disposed between the P-region 3 and the N-region 4, and the isolation region 5 includes an oxygen-doped polycrystalline silicon layer.

[0045] In this embodiment, the oxygen surface doping concentration in the oxygen-doped polycrystalline silicon layer is 1×10⁻⁶. 18 / cm 3 ~3×10 18 / cm 3 .

[0046] In other embodiments, the surface doping concentration of oxygen in the oxygen-doped polysilicon layer can also be 2 × 10⁻⁶. 18 / cm 3 ~8×10 19 / cm 3 5×10 18 / cm 3 ~1×10 19 / cm 3 8×10 18 / cm 3 ~1.2×10 19 / cm 3 1×10 19 / cm 3 ~3×10 19 / cm 3 2×10 19 / cm 3 ~7×10 19 / cm 3 8×10 19 / cm 3 ~1×10 20 / cm 3 However, it is not limited to this.

[0047] In this invention, the oxygen doping concentration is optimized to 10. 18 / cm 3 ~10 20 / cm 3 This method is beneficial for improving the barrier effect of oxygen-doped polycrystalline silicon layers and has lower process requirements. When the surface doping concentration of oxygen in the oxygen-doped polycrystalline silicon layer is low, its barrier effect as a barrier layer is poor. However, when the oxygen doping concentration is too high, it will increase the difficulty of the fabrication process and make it difficult to achieve. In particular, using PECVD technology to deposit a silicon oxide / amorphous silicon repeating stack structure to increase the oxygen doping concentration, excessive oxygen doping will lead to material embrittlement.

[0048] In this embodiment, the thickness of the oxygen-doped polycrystalline silicon layer is 150 nm to 180 nm, and the width is 80 μm to 120 μm.

[0049] In other embodiments, the thickness of the oxygen-doped polycrystalline silicon layer may be 30 nm to 50 nm, 40 nm to 70 nm, 60 nm to 90 nm, 80 nm to 100 nm, 100 nm to 130 nm, 140 nm to 170 nm, 180 nm to 210 nm, 200 nm to 230 nm, or 210 nm to 230 nm, but is not limited to these.

[0050] In other embodiments, the width of the oxygen-doped polysilicon layer used is 30μm-80μm, 90μm-120μm, 180μm-230μm, 300μm-380μm, 430μm-500μm, 550μm-620μm, 700μm-780μm, 820μm-900μm, 920μm-1000μm, but is not limited to these.

[0051] In this invention, by providing an isolation region 5 between the P region 3 and the N region 4, short circuits in the N / P region can be prevented. At the same time, by optimizing the oxygen doping concentration in the oxygen-doped polycrystalline silicon layer and the width of a portion of the isolation region, the corresponding component can achieve excellent anti-shadowing function, which is beneficial to improving the battery conversion efficiency.

[0052] In this embodiment, the total thickness of the P-type doped polysilicon passivation layer is 100 nm to 150 nm. The N-type doped polysilicon passivation layer comprises, from the inside out, a first boron-doped polysilicon film, a second SiO2 film, and a second boron-doped polysilicon film. The boron doping concentration in the first boron-doped polysilicon film is lower than that in the second boron-doped polysilicon film. The boron doping concentration in the first boron-doped polysilicon film exhibits a gradient distribution, gradually decreasing towards the inside, with a concentration range of 5 × 10⁻⁶. 17 / cm 3 ~3×10 19 / cm 3 The thickness of the first SiO2 film is 1.8 nm to 2.2 nm, and the boron doping concentration in the second boron-doped polycrystalline silicon film is 5 × 10⁻⁶. 19 / cm 3 ~1×10 20 / cm 3 The thickness of the first boron-doped polycrystalline silicon film is 20 nm to 30 nm, the thickness of the second SiO2 film is 0.8 nm to 1.6 nm, and the thickness of the second boron-doped polycrystalline silicon film is 80 nm to 120 nm.

[0053] In this invention, the p-type doped polycrystalline silicon passivation layer is a boron-doped polycrystalline silicon layer with different diffusion concentrations and different diffusion depths, exhibiting a p-poly / ultra-thin SiO2 / p+-poly stacked structure. As the emitter of the battery, it can effectively control boron doping and reduce the thickness of the polycrystalline silicon, thereby reducing the parasitic absorption of long-wavelength light by the battery and improving battery efficiency.

[0054] In this embodiment, the total thickness of the N-type doped polysilicon passivation layer is 120 nm to 160 nm. This N-type doped polysilicon passivation layer comprises, from the inside out, a first phosphorus-doped polysilicon film, a second SiO2 film, and a second phosphorus-doped polysilicon film. The phosphorus doping concentration in the first phosphorus-doped polysilicon film is lower than that in the second phosphorus-doped polysilicon film. The phosphorus doping concentration in the first phosphorus-doped polysilicon film exhibits a gradient distribution, gradually decreasing towards the inside, with a concentration range of 3 × 10⁻⁶. 19 / cm 3 ~6×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 3×10⁻⁶. 20 / cm 3 ~6×10 20 / cm 3 The thickness of the first phosphorus-doped polycrystalline silicon film is 20 nm to 30 nm, the thickness of the second SiO2 film is 0.8 nm to 1.6 nm, and the thickness of the second phosphorus-doped polycrystalline silicon film is 110 nm to 150 nm.

[0055] In this invention, the N-type doped polycrystalline silicon passivation layer is a phosphorus-doped polycrystalline silicon layer with different diffusion concentrations and different diffusion depths, exhibiting an n-poly / ultra-thin SiO2 / n+-poly stacked structure, forming a high-low junction N+ region as the electron collection region of the battery. This effectively controls phosphorus doping and reduces the thickness of the polycrystalline silicon, thereby reducing the parasitic absorption of long-wavelength light by the battery and improving battery efficiency.

[0056] In this embodiment, the silicon substrate 1 used is an N-type silicon wafer with a resistivity of 5 Ω·cm to 30 Ω·cm and a minority carrier lifetime greater than 3 ms.

[0057] In this embodiment, a tunneling oxide layer 2 is provided on the back side of the silicon substrate 1. A P-type doped polysilicon passivation layer, an N-type doped polysilicon passivation layer, and an oxygen-doped polysilicon layer are provided on the tunneling oxide layer 2. The outer surfaces of the P-type doped polysilicon passivation layer, the N-type doped polysilicon passivation layer, and the oxygen-doped polysilicon layer are in the same plane. A back passivation layer 6 is provided on the P-type doped polysilicon passivation layer, the N-type doped polysilicon passivation layer, and the oxygen-doped polysilicon layer. The back passivation layer 6 consists of an aluminum oxide passivation layer and a back passivation protection layer from the inside to the outside.

[0058] In this embodiment, the tunneling oxide layer 2 is a silicon oxide thin film with a thickness of 1.8-2.2 nm.

[0059] In this embodiment, the alumina passivation layer used is an AlOx thin film with a thickness of 4.5 nm to 6 nm.

[0060] In this embodiment, the back passivation protective layer is a SiNx thin film with a thickness of 80-90 nm.

[0061] In this embodiment, the front side of the silicon substrate has a pyramid-structured textured surface, and a front passivation layer 7 is provided on the textured surface of the front side of the silicon substrate. The front passivation layer 7 consists of an aluminum oxide passivation layer and a front passivation protection layer from the inside to the outside.

[0062] In this embodiment, the alumina passivation layer used is an AlOx thin film with a thickness of 4.5 nm to 6 nm.

[0063] In this embodiment, the front passivation protection layer is a SiNx thin film with a thickness of 70-75 nm.

[0064] In this invention, passivation layers are applied to the front and back sides of the silicon substrate, and their thickness is optimized, which can improve the problem of ultraviolet degradation in batteries.

[0065] In this embodiment, an electrode 8 is also provided on the back side of the silicon substrate. The electrode 8 is a silver electrode. After passing through the back passivation layer 6, the silver electrode forms an ohmic contact with the corresponding P-type doped polycrystalline silicon passivation layer and N-type doped polycrystalline silicon passivation layer, respectively.

[0066] A method for preparing a TBC battery structure according to the above embodiments of the present invention is shown in the following process flow diagram. Figure 2 As shown, it includes the following steps: S1. Pre-treatment of the silicon substrate, including pre-cleaning, micro-texturing, polishing, and post-cleaning, specifically: After pre-cleaning, a NaOH solution with a mass concentration of 0.5% to 0.8% and an additive volume concentration of 0.5% to 0.6% is used to microtexture the silicon substrate. The microtexturing is carried out at a temperature of 80℃ to 85℃ for 280s to 360s.

[0067] The silicon substrate was polished using a NaOH solution with a mass concentration of 0.6% to 1.2% at a temperature of 60℃ to 70℃ for a time of 180s to 240s.

[0068] The silicon substrate was post-cleaned using a NaOH solution with a mass concentration of 0.4-0.5% and a hydrogen peroxide mass concentration of 10-12%. The post-cleaning temperature was 60-65℃ and the post-cleaning time was 90-120s.

[0069] Finally, a mixed acid was used to clean the silicon substrate to remove oxides, silicates, and metal ions from the silicon wafer surface.

[0070] In step S1, the silicon substrate 1 used is an N-type silicon wafer with a resistivity of 5 Ω·cm to 30 Ω·cm and a minority carrier lifetime greater than 3 ms.

[0071] S2. Using an LPCVD device, tunneling oxide thin films and intrinsic polycrystalline silicon thin films are alternately deposited on the back side of a silicon substrate. Specifically, from the inside out, a first tunneling oxide thin film, a first intrinsic polycrystalline silicon thin film, a second tunneling oxide thin film, a second intrinsic polycrystalline silicon thin film, a third tunneling oxide thin film, and a third intrinsic polycrystalline silicon thin film are deposited sequentially to form a tunneling oxide / intrinsic polycrystalline silicon passivation stack.

[0072] In step S2, the deposition process parameters for the tunneling oxide film are: the reaction gas is O2, the flow rate is 5000 sccm to 20000 sccm, the deposition time is 120 s to 1800 s, and the deposition temperature is 500 ℃ to 700 ℃.

[0073] In step S2, the deposition process parameters for the intrinsic polycrystalline silicon thin film are as follows: the reaction gas is SiH4, the flow rate is 200sccm~2000sccm, the deposition time is 1000s~2000s, and the deposition temperature is 500℃~700℃.

[0074] In step S2, the total thickness of the tunneling oxide / intrinsic polysilicon passivation stack is 100 nm to 295 nm.

[0075] In step S2, the thickness of the first tunneling oxide film is 1.8 nm to 2.2 nm, the thickness of the first intrinsic polycrystalline silicon film is 20 nm to 30 nm, the thickness of the second tunneling oxide film is 0.8 nm to 1.6 nm, the thickness of the second intrinsic polycrystalline silicon film is 80 nm to 120 nm, the thickness of the third tunneling oxide film is 1.5 nm to 3 nm, and the thickness of the third intrinsic polycrystalline silicon film is 10 nm to 30 nm.

[0076] In step S2, the first tunneling oxide film, the second tunneling oxide film, and the third tunneling oxide film are all SiO2 films.

[0077] In step S2, by sequentially depositing the first tunneling oxide film, the first intrinsic polycrystalline silicon film, the second tunneling oxide film, the second intrinsic polycrystalline silicon film, the third tunneling oxide film, and the third intrinsic polycrystalline silicon film, the uneven diffusion is facilitated by the first tunneling oxide film, the second tunneling oxide film, and the third tunneling oxide film, and the tunneling structure is prevented from being damaged to varying degrees. This is beneficial to improving the passivation efficiency and conversion efficiency of the battery. At the same time, the structure has a higher metallization window, which is beneficial to improving the yield and efficiency of the battery.

[0078] In step S2, in other embodiments, a tunneling oxide film and an intrinsic polycrystalline silicon film can be alternately deposited on the back side of a silicon substrate using a combination of PECVD and boron diffusion. Specifically, a tunneling oxide film and an amorphous silicon film are alternately deposited on the surface of a silicon substrate using PECVD. After boron diffusion and heating, the amorphous silicon is crystallized and polycrystalline silicon is formed to obtain an intrinsic polycrystalline silicon film.

[0079] S3. A silicon dioxide thin film and a silicon nitride thin film are sequentially deposited on the back side of a silicon substrate using a PECVD device to form a silicon dioxide / silicon nitride stacked mask layer.

[0080] In step S3, the deposition process parameters for the silicon dioxide thin film are as follows: the reaction gases are SiH4 and N2O, the flow rate of SiH4 is 100sccm to 1000sccm, the flow rate of N2O is 3000sccm to 12000sccm, the RF power is 6000W to 18000W, and the deposition temperature is 350℃ to 550℃.

[0081] In step S3, the deposition process parameters for the silicon nitride thin film are as follows: the reaction gases are SiH4 and NH3, the flow rate of SiH4 is 100 sccm to 1000 sccm, the flow rate of NH3 is 3000 sccm to 12000 sccm, the RF power is 6000 W to 18000 W, and the deposition temperature is 350 °C to 550 °C.

[0082] In step S3, the thickness of the silicon dioxide / silicon nitride stacked mask layer is 60 nm to 210 nm.

[0083] In step S3, the thickness of the silicon dioxide film is 30 nm to 90 nm.

[0084] In step S3, the thickness of the silicon nitride film is 30 nm to 120 nm, and the refractive index is 2.1 to 2.3.

[0085] In step S3, the passivation film formed by stacking silicon dioxide and silicon nitride films serves as a mask layer, which can effectively block the diffusion of boron and phosphorus atoms during subsequent boron and phosphorus diffusion processes. In particular, in the Gap region, the mask layer and the tunneling oxide / intrinsic polysilicon passivation stack can effectively prevent boron and phosphorus atoms from diffusing into the intrinsic polysilicon in the Gap region. At the same time, under high temperature, oxygen in silicon dioxide will diffuse into the polysilicon, which is beneficial to improving the resistivity of the material in the Gap region.

[0086] S4. Laser grooving is performed on the back side of the silicon substrate. The grooving linewidth is 60-1000μm. The silicon dioxide / silicon nitride stacked mask layer, the third intrinsic polycrystalline silicon film and the third tunneling oxide film above the preset P area on the back side of the silicon wafer are precisely removed according to the preset pattern to expose the second intrinsic polycrystalline silicon film and form a boron diffusion contact window.

[0087] S5. Boron diffusion and oxidation are performed on the back side of the silicon substrate using a diffusion furnace. The process parameters for boron diffusion are: temperature 960℃~1050℃, reaction source BCl3 and O2, BCl3 flow rate 200 sccm~500 sccm, and O2 flow rate 10000 sccm~30000 sccm. In this invention, boron atoms diffuse into the intrinsic polycrystalline silicon thin film through boron diffusion, forming a P-type doped polycrystalline silicon passivation layer in the trenched region (P-region); through boron diffusion and oxidation, the silicon nitride mask in the non-P-region is oxidized, and a boron-doped BSG mask layer is formed simultaneously.

[0088] S6. Laser grooving is performed on the back side of the silicon substrate. The grooving linewidth is 60-800μm. The BSG mask layer, silicon dioxide / silicon nitride stacked mask layer, third intrinsic polycrystalline silicon thin film, third tunneling oxide thin film and part of the second intrinsic polycrystalline silicon thickness above the preset N region on the back side of the silicon wafer are precisely removed according to the preset pattern to expose the second intrinsic polycrystalline silicon thin film and form a phosphorus diffusion window.

[0089] S7. Phosphorus diffusion is performed on the back side of the silicon substrate. The process parameters for phosphorus diffusion are: temperature 800℃~950℃, phosphorus source POCl3, time 1000s~2400s, and O2 flow rate 10000 sccm~30000 sccm. In this invention, phosphorus diffusion allows phosphorus atoms to diffuse into the intrinsic polycrystalline silicon thin film and form an N-type doped polycrystalline silicon passivation layer in the trenched region (N-region). Simultaneously, phosphorus diffusion also forms a PSG layer on the exposed polycrystalline silicon surface (front, back, and surrounding areas), and phosphorus doping is performed on the BSG layer to form a BPSG layer.

[0090] In this invention, during the boron and phosphorus diffusion processes, oxygen atoms in the first and second tunneling oxide films can diffuse into the intrinsic polycrystalline silicon film. Combined with high-temperature diffusion at the silicon oxide / intrinsic polycrystalline silicon interface, an oxygen-doped polycrystalline silicon layer can be formed in the preset isolation region, which can significantly improve the resistivity of the gap region material. This is beneficial for better preventing short circuits in the P / N region. At the same time, using oxygen-doped polycrystalline silicon to replace traditional laser physical isolation reduces one laser physical isolation process and lowers equipment investment costs.

[0091] S8. Perform chain cleaning on the back side of the silicon substrate. Specifically, apply a water film to the back surface of the silicon wafer and use an HF solution with a mass concentration of 3% to 40% to remove the PSG, BPSG layers and silicon dioxide mask layers on the front and sides.

[0092] S9. Perform tank cleaning and texturing on the silicon substrate. Specifically, place the silicon wafer in a tank cleaning machine and clean it with a 3-5% NaOH solution (containing mask protection additives) to remove the tunneling oxide / intrinsic polysilicon passivation stack on the front edge and sides. Then, use a 0.5%-0.8% NaOH solution with an additive volume concentration of 0.5-0.6% to texture the silicon substrate. The texturing is performed at a temperature of 80-90℃ for 360-450 seconds.

[0093] S10. Use an HF solution with a mass concentration of 3% to 40% to pickle the front side of the silicon substrate to remove the BPSG layer, PSG layer and silicon dioxide mask layer on the back side, and obtain the silicon wafer before coating.

[0094] In this embodiment, the preparation method further includes the following steps: S11. Using a NaOH solution with a mass concentration of 0.5% to 0.8% and an additive volume concentration of 0.5% to 0.6%, the silicon substrate is texturized. The texturing is carried out at a temperature of 80 to 85°C for 380 to 420 seconds, forming a pyramidal textured surface structure on the front side.

[0095] S12. Aluminum oxide passivation layers are deposited on the front and back sides of a silicon substrate using the ALD method. The deposition process parameters are as follows: the aluminum source and oxygen source are trimethylaluminum (TMA) and pure water, respectively, and the atomic layer deposition process temperature is 250℃~280℃.

[0096] In step S12, the aluminum oxide passivation layer is an AlOx thin film with a thickness of 4.5 nm to 6 nm.

[0097] S13. A passivation protective layer is deposited on the front and back sides of a silicon substrate using a PECVD device. The deposition process parameters for the front passivation protective layer are as follows: SiH4 flow rate of 1000 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 15000 sccm, and deposition temperature of 380℃ to 500℃. The deposition process parameters for the back passivation protective layer are as follows: SiH4 flow rate of 500 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 18000 sccm, N2O flow rate of 8000 sccm to 15000 sccm, and deposition temperature of 380℃ to 500℃.

[0098] In step S13, the front passivation protective layer is a SiNx composite film with a thickness of 70nm to 75nm and a refractive index of 2.0 to 2.15.

[0099] In step S13, the back passivation protective layer is a SiNx composite film with a thickness of 80nm to 90nm and a refractive index of 2.05 to 2.2.

[0100] S14. Prepare metal electrodes on the back side of the silicon substrate. Specifically, use screen printing to print aluminum paste or silver paste on the P region and silver paste on the N region on the back side of the silicon substrate. After sintering, form semiconductor / metal ohmic contacts on the P-type doped polycrystalline silicon passivation layer and the N-type doped polycrystalline silicon passivation layer. Finally, perform photo-injection activation on the battery at medium and low temperatures to obtain a TBC battery with the above-mentioned TBC battery structure.

[0101] Testing and grading: By testing the current-voltage characteristic curve, key parameters such as battery conversion efficiency, short-circuit current, and open-circuit voltage are obtained, and efficiency grading is completed.

[0102] A TBC battery includes the TBC battery structure described above.

[0103] Compared to conventional TBC cells (based on a two-stage LCPVD deposition method), the TBC cell of this invention exhibits superior electrical performance. Specifically, the TBC cell of this invention achieves a photoelectric conversion efficiency (Eta) of up to 26.67%, a short-circuit current of up to 14.784 A, an open-circuit voltage of 744 mV, and an impact factor of up to 84.64%. Furthermore, the key parameters of the TBC cell of this invention, such as conversion efficiency, short-circuit current, and open-circuit voltage, are comparable to those of conventional TBC cells (based on a single-stage LCPVD deposition and sintering method).

[0104] In addition, calculations show that compared with conventional routes using single-GW equipment, the fixed investment cost of this invention's technical route is reduced by more than RMB 16 million per GW. It also reduces investment in related peripheral equipment and normal operating costs, saves nearly 18% of factory space, reduces labor costs by more than 8%, reduces product rework rate by more than 0.3%, and increases yield by more than 0.5%, making it more competitive than conventional routes.

[0105] The results above show that, compared with conventional TBC batteries and their fabrication methods, the fabrication method of the TBC battery structure of this invention innovatively proposes a design for single-deposition of multilayer tunneling oxide and polycrystalline silicon layers, a stacked mask design, a new isolation method, and an efficient cleaning process. This effectively solves problems such as cumbersome fabrication processes, residual boron-doped polycrystalline silicon from laser ablation, and high investment and production costs in existing TBC battery fabrication. The optimized stacked mask structure enhances the mask blocking effect, mitigates the cross-regional interdiffusion effect of dopant elements, and reduces passivation layer damage. Stepwise cleaning removes PSG, BPSG, silicon oxide, and the polycrystalline silicon layer, completing front texturing and back PSG, BPSG, and silicon oxide layer removal. Ultimately, this achieves a new breakthrough in TBC battery technology and effective control of production costs. As a novel TBC battery route, it can bring the following unexpected technical effects: (a) It greatly simplifies the TBC cell manufacturing process by replacing the traditional two-stage deposition with a single-stage deposition of a stacked tunneling oxide layer and an intrinsic amorphous silicon structure. This simplifies the process flow (LPCVD, cleaning, and laser), reduces process contamination from secondary deposition, lowers equipment investment and manufacturing costs, and improves product yield.

[0106] (b) The SiO2 / SiNx stacked mask layer prepared by PECVD on the back side effectively blocks the interdiffusion of boron and phosphorus dopants, preventing short circuit leakage in the PN region. At the same time, oxygen-doped polysilicon is generated at the interface between SiO2 and polysilicon in the bottom layer of the mask in the Gap region, which improves the resistivity of the region.

[0107] (c) During the high-temperature treatment of boron and phosphorus diffusion, the mask SiNx is oxidized to form a BPSG layer, which is easier to clean later. The P+ and N+ regions are formed by two precise laser grooving processes. Since the laser consumes the third tunneling oxide film (SiO2) / third intrinsic polycrystalline silicon film (i-poly), the damage of the laser to the silicon substrate is reduced.

[0108] (d) Using oxygen-doped polycrystalline silicon to replace traditional laser physical isolation reduces one laser physical isolation process and lowers equipment investment costs.

[0109] (e) The chain cleaning and tank cleaning processes are adopted. The chain cleaning protects the back side and removes the PSG, BPSG and SiO2 around the front edge. The tank cleaning removes the polycrystalline silicon layer around the edge and then performs texturing on the front side. This can improve the cleaning of the LPCVD secondary deposition and the color difference of the cell appearance.

[0110] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the spirit and technical essence of the present invention. Therefore, any simple modifications, equivalent substitutions, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A TBC battery structure, characterized in that, The device includes a silicon substrate, the back side of which includes alternating P-regions and N-regions. A P-type doped polysilicon passivation layer is disposed on the P-region, and an N-type doped polysilicon passivation layer is disposed on the N-region. An isolation region is disposed between the P-regions and the N-region, and the isolation region includes an oxygen-doped polysilicon layer.

2. The TBC battery structure according to claim 1, characterized in that, The oxygen surface doping concentration in the oxygen-doped polysilicon layer is 10. 18 / cm 3 ~10 20 / cm 3 The thickness of the oxygen-doped polycrystalline silicon layer is 30 nm to 240 nm; the width of the oxygen-doped polycrystalline silicon layer is 30 μm to 1000 μm.

3. The TBC battery structure according to claim 1, characterized in that, The thickness of the P-type doped polycrystalline silicon passivation layer is 65 nm to 220 nm; the P-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first boron-doped polycrystalline silicon thin film, a second SiO2 thin film, and a second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film is lower than that in the second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film exhibits a gradient distribution; the boron doping concentration in the second boron-doped polycrystalline silicon thin film is 1 × 10⁻⁶. 19 / cm 3 ~3×10 20 / cm 3 The thickness of the first boron-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; the thickness of the second boron-doped polycrystalline silicon film is 60 nm to 160 nm. The thickness of the N-type doped polycrystalline silicon passivation layer is 65 nm to 240 nm; the N-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first phosphorus-doped polycrystalline silicon film, a second SiO2 film, and a second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film is lower than that in the second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film exhibits a gradient distribution; the phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon film is 1 × 10⁻⁶. 20 / cm 3 ~1×10 21 / cm 3 The thickness of the first phosphorus-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; and the thickness of the second phosphorus-doped polycrystalline silicon film is 60 nm to 180 nm.

4. The TBC battery structure according to any one of claims 1 to 3, characterized in that, The silicon substrate includes an N-type silicon wafer; the resistivity of the N-type silicon wafer is 1 Ω·cm to 50 Ω·cm.

5. A method for preparing a TBC battery structure, characterized in that, Includes the following steps: S1. Pre-treat the silicon substrate; S2. Tunneling oxide films and intrinsic polycrystalline silicon films are alternately deposited on the back side of a silicon substrate to form a tunneling oxide / intrinsic polycrystalline silicon passivation stack; the tunneling oxide / intrinsic polycrystalline silicon passivation stack consists of, from the inside out, a first tunneling oxide film, a first intrinsic polycrystalline silicon film, a second tunneling oxide film, a second intrinsic polycrystalline silicon film, a third tunneling oxide film, and a third intrinsic polycrystalline silicon film; S3. Sequentially deposit a silicon dioxide thin film and a silicon nitride thin film on the back side of the silicon substrate to form a silicon dioxide / silicon nitride stacked mask layer; S4. Laser grooving is performed on the back side of the silicon substrate to remove the silicon dioxide / silicon nitride stacked mask layer, the third tunneling oxide film, and the third intrinsic polycrystalline silicon film above the preset P area on the back side of the silicon wafer. S5. Boron diffusion and oxidation are performed on the back side of the silicon substrate to form a P-type doped polysilicon passivation layer and a BSG layer in the trench area. The thickness of the BSG layer above the P region is more than 80nm. The silicon nitride mask in the non-P region is oxidized and a boron doped BSG mask layer is formed simultaneously. S6. Laser grooving is performed on the back side of the silicon substrate to remove the BSG mask layer, silicon dioxide mask layer, third intrinsic polycrystalline silicon thin film, and third tunneling oxide thin film above the preset N region on the back side of the silicon wafer. S7. Phosphorus diffusion and oxidation are performed on the back side of the silicon substrate to form an N-type doped polysilicon passivation layer and a PSG layer in the trench area, and a BPSG layer is formed on the surface of the non-N region. S8. Perform chain cleaning on the back of the silicon substrate to remove the BPSG layer and silicon dioxide stacked mask layer on the front and sides. S9. Perform a tank cleaning on the silicon substrate to remove the tunneling oxide / intrinsic polysilicon passivation stack on the front edge and side. S10. Acid pickling is performed on the front side of the silicon substrate to remove the BPSG layer, PSG layer and silicon dioxide mask layer on the back side.

6. The preparation method according to claim 5, characterized in that, In step S1, the pretreatment includes pre-cleaning, alkaline texturing, polishing, post-cleaning, water washing, and drying of the silicon substrate; the alkaline solution used in the polishing process is either KOH or NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; the polishing is performed at a temperature of 30℃ to 98℃; the polishing time is 100s to 600s; the cleaning is performed in a tank cleaning machine to remove the cutting damage layer on the surface. In step S2, a tunneling oxide film and an intrinsic polycrystalline silicon film are alternately deposited on the back side of a silicon substrate using an LPCVD device, or a PECVD method combined with boron diffusion is used to alternately deposit these films. When using an LPCVD device to alternately deposit the tunneling oxide film and the intrinsic polycrystalline silicon film on the back side of the silicon substrate, the deposition process parameters for the tunneling oxide film are: the reactant gas is O2, the gas flow rate is 5000 sccm to 20000 sccm, the deposition time is 120 s to 1800 s, and the deposition temperature is 500℃ to 700℃. The deposition process parameters for the intrinsic polycrystalline silicon film are: the reactant gas is SiH4, and the gas flow rate is 200 sccm to 2000 sccm. The deposition time is 1000s–2000s, and the deposition temperature is 500℃–700℃; the thickness of the tunneling oxide / intrinsic polysilicon passivation stack is 100nm–295nm; the thickness of the first tunneling oxide film is 1nm–2.5nm; the thickness of the first intrinsic polysilicon film is 5nm–60nm; the thickness of the second tunneling oxide film is 0.3nm–2nm; the thickness of the second intrinsic polysilicon film is 80nm–200nm; the thickness of the third tunneling oxide film is 1.5nm–3nm; the thickness of the third intrinsic polysilicon film is 10nm–30nm; the first, second, and third tunneling oxide films are all SiO2 films. In step S3, a silicon dioxide thin film and a silicon nitride thin film are sequentially deposited on the back side of a silicon substrate using a PECVD equipment. The deposition process parameters for the silicon dioxide thin film are as follows: the reactant gases are SiH4 and N2O, the flow rate of SiH4 is 100 sccm to 1000 sccm, the flow rate of N2O is 3000 sccm to 12000 sccm, the RF power is 6000 W to 18000 W, and the deposition temperature is 350℃ to 550℃. The deposition process parameters for the silicon nitride thin film are as follows: the reactant gases are SiH4 and NH3, the flow rate of SiH4 is 100 sccm to 1000 sccm, the flow rate of NH3 is 3000 sccm to 12000 sccm, the RF power is 6000 W to 18000 W, and the deposition temperature is 350℃ to 550℃. The thickness of the silicon dioxide / silicon nitride stack mask layer is 60 nm to 210 nm; the thickness of the silicon dioxide thin film is 30 nm to 90 nm. The silicon nitride film has a thickness of 30 nm to 120 nm and a refractive index of 2.1 to 2.

3. In step S4, the laser grooving has a film opening linewidth of 60μm to 1000μm; In step S5, a diffusion furnace is used to perform boron diffusion and oxidation on the back side of the silicon substrate. The process parameters for boron diffusion are: temperature 960℃~1050℃, reaction source BCl3 and O2, BCl3 flow rate 200 sccm~500 sccm, O2 flow rate 10000 sccm~30000 sccm; and the thickness of the BSG mask layer is 80 nm~130 nm. In step S6, the laser grooving has a film opening linewidth of 60μm to 800μm; In step S7, phosphorus diffusion is performed on the back side of the silicon substrate using a diffusion furnace; the process parameters for phosphorus diffusion are: temperature 800℃~950℃, phosphorus source is POCl3, time is 1000s~2400s, O2 flow rate is 10000 sccm~30000 sccm; the thickness of the PSG layer is 20 nm~60 nm. In step S8, the back side of the silicon substrate is subjected to chain cleaning using an HF solution; the mass concentration of the HF solution is 3% to 40%. In step S9, the silicon substrate is cleaned in a tank using an alkaline solution; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; the alkaline solution also contains a mask protection additive. In step S10, the front side of the silicon substrate is acid-washed using an HF solution; the mass concentration of the HF solution is 3% to 40%.

7. The preparation method according to claim 5 or 6, characterized in that, It also includes the following steps: S11. Texturing the front side of the silicon substrate to form a pyramidal textured surface structure. S12. Deposit aluminum oxide passivation layers on the front and back sides of the silicon substrate; S13. Deposit a front passivation protective layer and a back passivation protective layer on the front and back sides of the silicon substrate, respectively; S14. Fabricate a metal electrode on the back side of a silicon substrate.

8. The preparation method according to claim 7, characterized in that, In step S11, an alkaline solution is used to texturize the front side of the silicon substrate; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 1% to 5%; the alkaline solution also contains a mask protection additive. In step S12, an aluminum oxide passivation layer is deposited on the front and back sides of a silicon substrate using the ALD method. The deposition process parameters for the aluminum oxide passivation layer are as follows: the aluminum source and oxygen source are trimethylaluminum and pure water, respectively, and the process temperature is 250℃~300℃. The thickness of the aluminum oxide passivation layer is 3 nm~15 nm. In step S13, a front passivation protective layer and a back passivation protective layer are deposited on the front and back sides of the silicon substrate using a PECVD equipment, respectively. The deposition process parameters for the front passivation protective layer are: SiH4 flow rate of 1000 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 15000 sccm, and deposition temperature of 380℃ to 500℃. The deposition process parameters for the back passivation protective layer are: SiH4 flow rate of 500 sccm to 3000 sccm, NH3 flow rate of 5000 sccm to 18000 sccm, and N2O flow rate of 8000 sccm. The deposition thickness is sccm to 15000 sccm, and the deposition temperature is 380℃ to 500℃; the front passivation protective layer is one of SiNx thin films, SiNOx thin films, and SiOx thin films, or a passivation film formed by stacking them; the total thickness of the front passivation protective layer is 65nm to 85nm, and the refractive index of the front passivation protective layer is 2.0 to 2.2; the back passivation protective layer is a SiNx thin film; the total thickness of the back passivation protective layer is 70nm to 90nm, and the refractive index of the back passivation protective layer is 2.0 to 2.3; In step S14, the preparation of metal electrodes on the back side of the silicon substrate includes the following steps: printing silver paste or aluminum paste on the P-region of the back side of the silicon substrate using screen printing, printing silver paste on the N-region, and sintering.

9. The preparation method according to claim 8, characterized in that, The TBC battery structure includes a silicon substrate. The back side of the silicon substrate includes alternating P-regions and N-regions. A P-type doped polycrystalline silicon passivation layer is disposed on the P-region, and an N-type doped polycrystalline silicon passivation layer is disposed on the N-region. An isolation region is disposed between the P-region and the N-region, and the isolation region includes an oxygen-doped polycrystalline silicon layer. The oxygen surface doping concentration in the oxygen-doped polycrystalline silicon layer is 10. 18 / cm 3 ~10 20 / cm 3 The thickness of the oxygen-doped polycrystalline silicon layer is 30 nm to 240 nm; the width of the oxygen-doped polycrystalline silicon layer is 30 μm to 1000 μm. The thickness of the P-type doped polycrystalline silicon passivation layer is 65 nm to 220 nm; the P-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first boron-doped polycrystalline silicon thin film, a second SiO2 thin film, and a second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film is lower than that in the second boron-doped polycrystalline silicon thin film; the boron doping concentration in the first boron-doped polycrystalline silicon thin film exhibits a gradient distribution; the boron doping concentration in the second boron-doped polycrystalline silicon thin film is 1 × 10⁻⁶. 19 / cm 3 ~3×10 20 / cm 3 The thickness of the first boron-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; the thickness of the second boron-doped polycrystalline silicon film is 60 nm to 160 nm. The thickness of the N-type doped polycrystalline silicon passivation layer is 65 nm to 240 nm; the N-type doped polycrystalline silicon passivation layer comprises, from the inside out, a first phosphorus-doped polycrystalline silicon film, a second SiO2 film, and a second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film is lower than that in the second phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon film exhibits a gradient distribution; the phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon film is 1 × 10⁻⁶. 20 / cm 3 ~1×10 21 / cm 3 The thickness of the first phosphorus-doped polycrystalline silicon film is 5 nm to 60 nm; the thickness of the second SiO2 film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 60 nm to 180 nm. The silicon substrate includes an N-type silicon wafer; the resistivity of the N-type silicon wafer is 1 Ω·cm to 50 Ω·cm.

10. A TBC battery, characterized in that, The TBC battery includes the TBC battery structure according to any one of claims 1 to 4, or the TBC battery structure prepared by the preparation method according to any one of claims 5 to 9.

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