Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate, and forming a metal layer on the substrate; sequentially forming an insulating layer and a photoresist layer on the metal layer; removing a part of the photoresist layer to expose a part of the top surface of the insulating layer; processing the insulating layer by adopting a preset modification process based on a preset modification element so as to form a modified layer in the insulating layer; the photoresist layer is removed and a dielectric layer is formed on the insulating layer. According to the preparation method of the semiconductor structure, the photoresist layer is formed on the insulating layer, part of the photoresist layer is removed, part of the top surface of the insulating layer is exposed, the insulating layer is treated by adopting the preset modification process based on the preset modification elements, so that the modified layer is formed in the insulating layer, and modification treatment on the insulating layer is realized. The etching efficiency of the modified layer in the insulating layer can be remarkably improved, so that the local over-etching phenomenon of the insulating layer is effectively avoided, the subsequent metal layer is ensured to be in good contact, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the development of semiconductor technology, the demand for improved device integration and performance is becoming increasingly prominent. In order to reduce parasitic capacitance, signal delay, and crosstalk, dielectric materials are usually filled between metal layers to reduce the dielectric constant, thereby further improving interconnect reliability and speed.

[0003] However, due to the etch loading effect, the insulating layer between the internal metal layers is prone to localized under etch phenomenon, which can cause metal layer breakage and metal interconnect failure, thus significantly reducing chip yield.

[0004] Therefore, how to reduce and avoid local over-etching of the insulating layer has become an urgent problem to be solved. Summary of the Invention

[0005] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0006] According to some embodiments, this application provides a method for fabricating a semiconductor structure, the method comprising:

[0007] Provide a substrate, and form a metal layer on the substrate;

[0008] An insulating layer and a photoresist layer are sequentially formed on a metal layer;

[0009] Remove part of the photoresist layer to expose part of the top surface of the insulating layer;

[0010] Based on preset modifying elements, the insulating layer is treated with a preset modification process to form a modified layer within the insulating layer;

[0011] Remove the photoresist layer and form a dielectric layer on the insulating layer.

[0012] In the semiconductor structure fabrication method of the above embodiments, a photoresist layer is formed on the insulating layer and a portion of the photoresist layer is removed to expose a portion of the top surface of the insulating layer. Based on preset modifying elements, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, thereby achieving modification treatment of the insulating layer. This significantly improves the etching efficiency of the modified layer within the insulating layer, effectively avoiding localized over-etching of the insulating layer, ensuring good contact of subsequent metal layers, and thus improving product yield.

[0013] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, including:

[0014] The insulating layer is treated with plasma surface treatment technology to form a modified layer within the insulating layer.

[0015] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, including:

[0016] The insulating layer is treated with ion implantation to form a modified layer within the insulating layer.

[0017] In some embodiments, the flow rate of hydrogen in the plasma surface treatment process ranges from 50 sccm to 1000 sccm.

[0018] In some embodiments, the input power range of the plasma surface treatment process includes 200W to 1000W;

[0019] In some embodiments, the process pressure range of the plasma surface treatment process includes 1.0 Torr to 6.0 Torr;

[0020] In some embodiments, the processing time of the plasma surface treatment process ranges from 10 s to 60 s.

[0021] In some embodiments, the dose range of hydrogen atoms in the ion implantation process includes 1E10 to 1E14;

[0022] In some embodiments, the implantation energy range of the ion implantation process includes 1 kV to 20 kV.

[0023] In some embodiments, the preset modifying elements further include oxygen, nitrogen, boron, phosphorus, or argon.

[0024] In some embodiments, the thickness of the modified layer is 30% to 50% of the thickness of the insulating layer.

[0025] In some embodiments, the insulating layer is made of nitrogen-doped silicon carbide.

[0026] In some embodiments, an insulating layer and a photoresist layer are sequentially formed on a metal layer, including:

[0027] An insulating layer is formed on a metal layer using a physical deposition process;

[0028] A photoresist layer is formed on the insulating layer.

[0029] According to some embodiments, this application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method in any of the above embodiments.

[0030] In the semiconductor structure of the above embodiments, the insulating layer is modified by using a preset modification process based on preset modification elements to form a modified layer within the insulating layer. This significantly improves the etching efficiency of the modified layer within the insulating layer, effectively avoiding localized over-etching of the insulating layer and ensuring good contact of subsequent metal layers, thereby improving product yield. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0032] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S10 of a semiconductor structure fabrication method according to an embodiment of this application;

[0033] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S31 of a semiconductor structure fabrication method according to an embodiment of this application;

[0034] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S32 of a semiconductor structure fabrication method according to an embodiment of this application;

[0035] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S50 of a semiconductor structure fabrication method according to an embodiment of this application;

[0036] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S70 of a semiconductor structure fabrication method according to an embodiment of this application;

[0037] Figure 7 This is a schematic cross-sectional view of the structure obtained by removing the photoresist layer in step S70 of a method for fabricating a semiconductor structure according to an embodiment of this application.

[0038] Figure 8 This is a schematic cross-sectional view of the structure obtained by forming a dielectric layer in step S70 of a method for fabricating a semiconductor structure according to an embodiment of this application.

[0039] Figure 9 This is a schematic diagram illustrating the yield of a semiconductor structure fabricated in a method for preparing a semiconductor structure according to an embodiment of this application.

[0040] Explanation of reference numerals in the attached figures: 10, substrate; 20, metal layer; 30, insulating layer; 31, modified layer; 40, photoresist layer; 50, dielectric layer. Detailed Implementation

[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0044] Furthermore, to clearly illustrate the multiple layers and regions in the accompanying drawings, the thickness of each layer and each region has been enlarged to clearly demonstrate the relative positions of the layers and the distribution of the regions. When a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, this description includes not only the case where it is "directly" above the other portion, but also the case where other layers are present in between. Moreover, it is understood that when a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, it generally refers to the side directly above the other portion.

[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0048] As semiconductor processes advance to the deep submicron scale, device integration and operating frequencies continue to increase, placing higher demands on the performance and reliability of interconnect layers. Copper interconnects, with their low resistance, have become the mainstream choice for metal linewidth and stacking. However, copper has high diffusion properties, requiring effective diffusion blocking and etching control measures in the internal metal layer structure to prevent metal contamination, interface degradation, and device performance deterioration. To reduce parasitic capacitance and minimize signal propagation delay and crosstalk, interconnect systems form multilayer dielectric structures between copper lines and low-k dielectric materials, and a specialized insulating film is introduced outside the copper diffusion barrier layer to improve damping effect and thermal stability. Insulating thin films are widely used as diffusion barrier layers and etching stop layers due to their excellent chemical stability and high etching resistance. Because the Si-C and Si-N bonds in the insulating layer have high binding energy and etching resistance under high temperature and plasma environments, the insulating thin film exhibits significant structural conformability and durability in large-size wafer and multi-hole etching processes, which is beneficial for achieving higher throughput and yield.

[0049] However, in the process flow, the thickness distribution of the insulating film on the wafer surface is not completely uniform, and the thickness uniformity fluctuates with differences in wafer radius, substrate temperature field, and plasma density distribution. Meanwhile, the etching loading effect is particularly prominent in porous etching scenarios. Differences in the utilization rate of etching gas and the concentration of active species in different regions can lead to localized under-etching, i.e., localized over-etching of the thin film, which in turn reduces the connectivity and reliability of subsequent metal interconnects. Localized under-etching not only causes localized copper layer exposure and increased copper diffusion paths, but may also generate stress concentration, microcracks, and interlayer delamination at the interface, ultimately leading to wire breaks and decreased yield. Furthermore, insufficient film thickness uniformity can also affect subsequent metal filling, copper embedding, and interfacial coupling of dielectric materials, further amplifying fluctuations in parasitic capacitance and latency.

[0050] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.

[0051] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, which includes the following steps.

[0052] Step S10: Provide a substrate and form a metal layer on the substrate;

[0053] Step S30: An insulating layer and a photoresist layer are sequentially formed on the metal layer;

[0054] Step S50: Remove part of the photoresist layer to expose part of the top surface of the insulating layer;

[0055] Step S70: Based on the preset modifying elements, the insulating layer is treated with a preset modification process to form a modified layer within the insulating layer;

[0056] Step S90: Remove the photoresist layer and form a dielectric layer on the insulating layer.

[0057] In the semiconductor structure fabrication method of the above embodiments, a photoresist layer is formed on the insulating layer and a portion of the photoresist layer is removed to expose a portion of the top surface of the insulating layer. Based on preset modifying elements, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, thereby achieving modification treatment of the insulating layer. This significantly improves the etching efficiency of the modified layer within the insulating layer, effectively avoiding localized over-etching of the insulating layer, ensuring good contact of subsequent metal layers, and thus improving product yield.

[0058] In some embodiments, step S30, forming an insulating layer and a photoresist layer sequentially on the metal layer, includes:

[0059] Step S31: An insulating layer is formed on the metal layer using a physical deposition process;

[0060] Step S32: Form a photoresist layer on the insulating layer.

[0061] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, including:

[0062] Step S71: The insulating layer is treated with plasma surface treatment process to form a modified layer within the insulating layer.

[0063] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, a preset modification process is used to treat the insulating layer to form a modified layer within the insulating layer, including:

[0064] Step S72: The insulating layer is treated with ion implantation to form a modified layer within the insulating layer.

[0065] In some embodiments, the flow rate of hydrogen in the plasma surface treatment process ranges from 50 sccm to 1000 sccm.

[0066] In some embodiments, the input power range of the plasma surface treatment process includes 200W to 1000W;

[0067] In some embodiments, the process pressure range of the plasma surface treatment process includes 1.0 Torr to 6.0 Torr;

[0068] In some embodiments, the processing time of the plasma surface treatment process ranges from 10 s to 60 s.

[0069] In some embodiments, the dose range of hydrogen atoms in the ion implantation process includes 1E10 to 1E14;

[0070] In some embodiments, the implantation energy range of the ion implantation process includes 1 kV to 20 kV.

[0071] In some embodiments, the preset modifying elements further include oxygen, nitrogen, boron, phosphorus, or argon.

[0072] In some embodiments, the thickness of the modified layer is 30% to 50% of the thickness of the insulating layer.

[0073] In some embodiments, the insulating layer is made of nitrogen-doped silicon carbide.

[0074] In the embodiments disclosed above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0075] To more clearly illustrate the semiconductor structure fabrication method provided in the above embodiments, the following is combined with... Figures 2 to 9 The method is described in detail.

[0076] like Figure 2 As shown, in step S10, a substrate 10 is provided. As an example, in this embodiment of the disclosure, the substrate 10 can be constructed from any combination of semiconductor materials, insulating materials, conductive materials, or similar materials. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon-germanium (SiGe) substrate 10, a silicon-germanium-carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0077] In step S10, an ion implantation process can be used to implant P-type ions into the substrate 10 to form a first type of doped well region (not shown). The P-type ions can be, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. Alternatively, an ion implantation process can be used to implant N-type ions into the substrate 10 to form a second type of doped well region (not shown). The N-type ions can be, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0078] In embodiments where substrate 10 includes a P-type substrate 10, the step of forming an active region (not shown) by implanting N-type ions may be included; correspondingly, in embodiments where substrate 10 includes an N-type substrate 10, the step of forming an active region (not shown) by implanting P-type ions may be included. Accordingly, the active region can be a P-type active region or an N-type active region. A P-type active region can form an N-type metal-oxide-semiconductor (NMOS) device, and an N-type active region can form a P-type metal-oxide-semiconductor (PMOS) device. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on substrate 10, therefore the type of substrate 10 should not limit the scope of protection of this disclosure.

[0079] like Figure 2 As shown, in step S10, a metal layer 20 is formed on the substrate 10;

[0080] For example, in step S10, a metal layer 20 can be formed on the substrate 10 using a process such as chemical vapor deposition or physical vapor deposition (PVD). The chemical vapor deposition process can include one or more of atmospheric-pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0081] For example, the material of metal layer 20 can be copper.

[0082] Before performing step S20, a step of cleaning the substrate 10 may be included. Cleaning removes impurities from the surface of the substrate 10, preventing them from affecting subsequent processes and thus ensuring device performance. Specifically, a cleaning solution can be used to clean the substrate 10, and the substrate 10 can be placed in a cleaning tank containing the cleaning solution for cleaning. The specific cleaning solution and cleaning process used for cleaning the substrate 10 are known to those skilled in the art and will not be described here. It should be noted that after cleaning the substrate 10, a drying step is also required. The method for drying the substrate 10 is well known to those skilled in the art and will not be described here.

[0083] like Figures 3 to 4 As shown, in step S30, an insulating layer 30 and a photoresist layer 40 are sequentially formed on the metal layer 20.

[0084] In some embodiments, step S30, which involves sequentially forming an insulating layer 30 and a photoresist layer 40 on the metal layer 20, includes steps S31 and S32.

[0085] like Figure 3 As shown, in step S31, an insulating layer 30 is formed on the metal layer 20 using a physical deposition process.

[0086] It is understandable that physical deposition (PVD) processes can typically yield high-purity, compositionally controlled thin films, effectively improving the chemical stability and structural integrity of the insulating layer 30. Furthermore, by precisely controlling parameters such as film thickness, deposition rate, substrate temperature, pressure, and target combination, a dense and uniform insulating layer 30 can be obtained, effectively suppressing the diffusion of the metal layer 20 and improving interface density, thereby reducing interface stress and adhesion problems. Moreover, the insulating layer 30 formed using physical deposition facilitates a smooth and low-stress interface with the metal layer 20 and the subsequent dielectric layer 50, helping to reduce interface cracking and adhesion issues.

[0087] In some embodiments, the insulating layer 30 is made of nitrogen-doped silicon carbide.

[0088] like Figure 4 As shown, in step S32, a photoresist layer 40 is formed on the insulating layer 30.

[0089] For example, a photoresist material layer can be coated on the top surface of the insulating layer 30 to form a photoresist layer 40. The photoresist can be a positive photoresist or a negative photoresist.

[0090] like Figure 5 As shown, in step S50, a portion of the photoresist layer 40 is removed to expose a portion of the top surface of the insulating layer 30;

[0091] For example, in step S50, a patterned mask can be placed on the photoresist, and through a series of steps such as exposure and development, part of the photoresist layer 40 is removed to expose part of the top surface of the insulating layer 30, thereby forming a patterned photoresist layer 40. The patterned photoresist layer 40 has an opening pattern that defines the position and shape of the modified area, and the development method can be positive development or negative development.

[0092] It is understood that the patterned mask in step S50 can be the same mask used to form the metal interconnect structure in subsequent processes, without the need to use a new mask, thus not burdening the process and saving mask space and reducing process costs.

[0093] like Figure 6 As shown, in step S70, based on preset modifying elements, the insulating layer 30 is treated with a preset modification process to form a modified layer 31 within the insulating layer 30.

[0094] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, the insulating layer 30 is treated with a preset modification process to form a modified layer 31 within the insulating layer 30, including:

[0095] like Figure 6 As shown, in step S71, the insulating layer 30 is treated with a plasma surface treatment process to form a modified layer 31 within the insulating layer 30.

[0096] It is understood that in embodiments where the insulating layer 30 is made of nitrogen-doped silicon carbide, the implantation of hydrogen can weaken the Si-C and Si-N bonds in the nitrogen-doped silicon carbide film, making the insulating layer 30 easier to break during subsequent etching, thereby increasing the etching rate of the insulating layer 30 and effectively avoiding local over-etching of the insulating layer 30.

[0097] In some embodiments, the hydrogen flow rate in the plasma surface treatment process ranges from 50 sccm to 1000 sccm. For example, the hydrogen flow rate in the plasma surface treatment process is 50 sccm, 75 sccm, 100 sccm, 150 sccm, 200 sccm, 500 sccm, 750 sccm, or 1000 sccm, etc.

[0098] In some embodiments, the input power range of the plasma surface treatment process includes 200W to 1000W. For example, the input power of the plasma surface treatment process can be 200, 300W, 400W, 500W, 600W, 700W, 800W, 900W, or 1000W, etc.

[0099] In some embodiments, the process pressure range of the plasma surface treatment process includes 1.0 Torr to 6.0 Torr. For example, the process pressure of the plasma surface treatment process can be 1.0 Torr, 2.0 Torr, 3.0 Torr, 4.0 Torr, 5.0 Torr, or 6.0 Torr, etc.

[0100] In some embodiments, the processing time of the plasma surface treatment process ranges from 10s to 60s. For example, the processing time of the plasma surface treatment process can be 10s, 20s, 30s, 40s, 50s, or 60s, etc.

[0101] In some embodiments, the preset modifying element is hydrogen; based on the preset modifying element, the insulating layer 30 is treated with a preset modification process to form a modified layer 31 within the insulating layer 30, including:

[0102] like Figure 6 As shown, in step S72, the insulating layer 30 is treated with an ion implantation process to form a modified layer 31 within the insulating layer 30.

[0103] It is understood that in embodiments where the insulating layer 30 is made of nitrogen-doped silicon carbide, the implantation of hydrogen can weaken the Si-C and Si-N bonds in the nitrogen-doped silicon carbide film, making the insulating layer 30 easier to break during subsequent etching, thereby increasing the etching rate of the insulating layer 30 and effectively avoiding local over-etching of the insulating layer 30.

[0104] In some embodiments, the dose of hydrogen atoms in the ion implantation process ranges from 1E10 to 1E14. For example, the dose of hydrogen atoms in the ion implantation process can be 1E10 or 1E14, etc.

[0105] In some embodiments, the implantation energy range of the ion implantation process includes 1 kV to 20 kV. For example, the implantation energy of the ion implantation process can be 1 kV, 2 kV, 5 kV, 10 kV, 15 kV, or 20 kV, etc.

[0106] In some embodiments, the preset modifying elements further include oxygen, nitrogen, boron, phosphorus, or argon.

[0107] In some embodiments, the thickness of the modified layer 31 is 30% to 50% of the thickness of the insulating layer 30. It is understood that the insulating layer 30, as an etching stop layer, needs to be thick enough to provide stable termination conditions during etching, but not so thick as to increase stress, affect thermal management, or obscure the underlying structure. Setting the thickness of the modified layer 31 to 30% to 50% of the insulating layer 30 can minimize localized over-etching of the insulating layer 30 while ensuring its modification effect, thereby reducing the risk of metal exposure and wire breakage. Furthermore, without sacrificing the etching stop effect of the insulating layer 30, the impact on the overall dielectric constant, thermal diffusion, and stress distribution is minimized. If the modified layer 31 is too thin, it will be difficult to uniformly bear stress and resist interface peeling; if it is too thick, it may become a stress source or a hotspot that triggers interlayer delamination. Therefore, the thickness of the modified layer 31, which is 30% to 50% of the thickness of the insulating layer 30, can provide sufficient mechanical buffering, reduce interface stress concentration, and thus maintain a stable etching stop effect under different wafer batches, hole densities and plasma power, while improving process repeatability and yield tolerance.

[0108] like Figure 7 and Figure 8 As shown, in step S90, the photoresist layer 40 is removed, and a dielectric layer 50 is formed on the insulating layer 30.

[0109] In some embodiments, such as Figure 8 As shown, in step S90, a dielectric layer 50 can be formed on the insulating layer 30 using a physical deposition process.

[0110] It is understandable that forming the dielectric layer 50 on the insulating layer 30 using a physical deposition process can effectively improve the chemical stability and structural integrity of the dielectric layer 50. Furthermore, by precisely controlling parameters such as film thickness, deposition rate, substrate temperature, pressure, and target combination, a dense and uniform dielectric layer 50 can be obtained, which is beneficial for achieving a smooth and low-stress interface between the dielectric layer 50 and the insulating layer 30, and helps reduce interface cracking and adhesion problems.

[0111] For example, after each semiconductor layer is formed, a preset cleaning process can be performed. The preset cleaning process can include wet cleaning process and dry cleaning process. The wet cleaning process uses specific chemical solutions and deionized water to clean the wafer surface without damage. Wet cleaning mainly includes RCA cleaning method, dilution chemical method, IMEC cleaning method or single wafer cleaning method, etc. For example, the single wafer cleaning method not only has a better cleaning effect, but also reduces the consumption of chemicals and increases the cost-effectiveness of wafers by recycling chemical solutions and deionized water during the cleaning process.

[0112] like Figure 9As shown in the experiment, the applicant demonstrated that when using nitrogen-doped silicon carbide to make the insulating layer 30, applying a plasma surface treatment process based on hydrogen to the insulating layer 30 to form a modified layer 31 within the insulating layer 30 can significantly improve the etching efficiency of the modified layer 31 within the insulating layer 30. This effectively avoids localized over-etching of the insulating layer 30, ensuring good contact of the subsequent metal layer 20. Thus, the product defect rate can be reduced from 5% to below 1%, effectively improving product yield.

[0113] In the semiconductor structure fabrication method of the above embodiment, a photoresist layer 40 is formed on the insulating layer 30 and a portion of the photoresist layer 40 is removed to expose a portion of the top surface of the insulating layer 30. Based on preset modifying elements, a preset modification process is used to treat the insulating layer 30 to form a modified layer 31 within the insulating layer 30, thereby achieving modification treatment of the insulating layer 30. This significantly improves the etching efficiency of the modified layer 31 within the insulating layer 30, effectively avoiding localized over-etching of the insulating layer 30, ensuring good contact of the subsequent metal layer 20, and thus improving product yield.

[0114] Please see Figure 8 According to some embodiments, this application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method in any of the above embodiments.

[0115] In the semiconductor structure of the above embodiments, the insulating layer is modified by using a preset modification process based on preset modification elements to form a modified layer within the insulating layer. This significantly improves the etching efficiency of the modified layer within the insulating layer, effectively avoiding localized over-etching of the insulating layer and ensuring good contact of subsequent metal layers, thereby improving product yield.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a metal layer is formed on the substrate; An insulating layer and a photoresist layer are sequentially formed on the metal layer; Remove a portion of the photoresist layer to expose a portion of the top surface of the insulating layer; Based on preset modifying elements, the insulating layer is treated with a preset modification process to form a modified layer within the insulating layer; Remove the photoresist layer and form a dielectric layer on the insulating layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The preset modification element is hydrogen. The step of treating the insulating layer with a preset modification process based on preset modification elements to form a modified layer within the insulating layer includes: The insulating layer is treated with a plasma surface treatment process to form a modified layer within the insulating layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The preset modification element is hydrogen. The step of treating the insulating layer with a preset modification process based on preset modification elements to form a modified layer within the insulating layer includes: The insulating layer is treated with an ion implantation process to form a modified layer within the insulating layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The parameters of the plasma surface treatment process include at least one of the following characteristics: The hydrogen flow rate range in the plasma surface treatment process includes 50 sccm to 1000 sccm; The input power range of the plasma surface treatment process includes 200W to 1000W; The process pressure range of the plasma surface treatment process includes 1.0 Torr to 6.0 Torr; The processing time range of the plasma surface treatment process is from 10s to 60s.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The parameters of the ion implantation process include at least one of the following characteristics: The dose range of hydrogen atoms in the ion implantation process includes 1E10 to 1E14; The implantation energy range of the ion implantation process includes 1 kV to 20 kV.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The preset modifying elements also include oxygen, nitrogen, boron, phosphorus, or argon.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the modified layer is 30% to 50% of the thickness of the insulating layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The insulating layer is made of nitrogen-doped silicon carbide.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of sequentially forming an insulating layer and a photoresist layer on the metal layer includes: An insulating layer is formed on the metal layer using a physical deposition process; A photoresist layer is formed on the insulating layer.

10. A semiconductor structure, characterized in that, It is prepared by the method for preparing the semiconductor structure as described in any one of claims 1-9.

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