Shared phase locked loop (PLL) circuit for multiple transmit chains

Abstract

Aspects described herein include apparatuses and methods for phase-locked loop (PLL) output sharing between multiple communication chains in a wireless communication device. In one aspect, an apparatus includes: a phase-locked loop (PLL) circuit having a shared PLL output; a radar signal generation circuit; a first transmit chain coupled to the shared PLL output and the radar signal generation circuit; and a second transmit chain coupled to the shared PLL output and the radar signal generation circuit.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices and wireless communications. For example, aspects of this disclosure relate to transmit chain circuits having multiple transmit chains. Some aspects are specifically used to generate multiple orthogonal millimeter-wave radar transmits. Background Technology

[0002] Wireless communication devices and technologies are becoming increasingly prevalent. Wireless communication devices typically transmit and receive communication signals. The radio frequency front-end (RFFE) module is the wireless communication device that powers the wireless signal transmission and also manages the reception of wireless signals from the antenna. With the increasing prevalence of wireless communication technologies, the increasing throughput of communication systems, and the growing complexity of power management for wireless devices, RFFE modules are becoming a significant component of wireless devices. Limiting power usage and managing power efficiency are important goals in device design, especially for mobile devices. Additionally, some of these systems can integrate millimeter-wave technology for communication and / or radar applications. Summary of the Invention

[0003] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which alone uniquely accounts for the desired properties described herein. Certain prominent features are described herein without limiting the scope of the appended claims.

[0004] In some aspects, a method is provided. This method includes: generating a first radar signal using a radar signal generation circuit and a first transmission chain coupled to a shared PLL circuit; and generating a second radar signal using the same radar signal generation circuit and a second transmission chain coupled to the shared PLL circuit.

[0005] In another aspect, an apparatus for wireless communication is provided. The apparatus includes: components for generating a first radar signal using a radar signal generation circuit and a first transmission chain coupled to a shared PLL circuit; and components for generating a second radar signal using the radar signal generation circuit and a second transmission chain coupled to the shared PLL circuit.

[0006] In another aspect, a wireless communication device is provided. The device includes: a phase-locked loop (PLL) circuit having a shared PLL output; a radar signal generation circuit; a first transmission chain coupled to the shared PLL output and the radar signal generation circuit; and a second transmission chain coupled to the shared PLL output and the radar signal generation circuit.

[0007] Some of these aspects are configured such that a shared PLL output is coupled to a mixer in the first transmit chain via a local oscillator (LO) circuit. Some of these aspects are configured such that a shared PLL output is coupled to a mixer in the second transmit chain via an LO circuit and a first divider circuit.

[0008] Some of these aspects are configured with a third transmit chain, which is coupled to the shared PLL output via an LO circuit and a second divider circuit independent of the first divider circuit.

[0009] Some of these aspects are configured such that the first and second transmission chains include a shared PLL output, wherein the PLL circuitry is configured to generate a shared transmission signal using frequency modulated continuous wave (FMCW) modulation inputs, wherein the transmission circuitry of the second transmission chain is coupled to the shared PLL output via a frequency divider circuitry, and wherein the transmission circuitry of the first transmission chain is coupled to the shared PLL output.

[0010] Some of these aspects are configured with a third transmission chain, which is coupled to a shared PLL output via a second frequency divider circuit independent of the first frequency divider circuit. Some of these aspects are configured such that the transmission circuit of the first transmission chain is configured to output a first radar transmission at a shared frequency of the shared transmission signal, and the transmission circuit of the second transmission chain is configured to output a second radar transmission at a second frequency shifted from the shared frequency by the frequency divider circuit.

[0011] Some of these aspects are configured such that the first and second transmit chains include a shared mixer, wherein a shared PLL output is coupled to the LO input of the shared mixer, and wherein the transmit circuitry of the second transmit chain is coupled to the output of the shared mixer via a frequency divider circuit. Some of these aspects are configured such that the transmit circuitry of the first transmit chain is independent of the transmit circuitry of the second transmit chain and is coupled to the output of the shared mixer without an intermediate frequency divider circuit. Some of these aspects are configured such that the radar signal generation circuitry includes a shared frequency modulated continuous wave-intermediate frequency (FMCW-IF) signal generation circuitry coupled to the signal input of the shared mixer. Some of these aspects are configured such that the first frequency divider circuitry includes a programmable frequency divider.

[0012] Some of these aspects are configured such that the first and second transmit chains share a frequency modulated continuous wave-intermediate frequency (FMCW-IF) circuit and an IQ generation circuit coupled to the FMCW-IF circuit, wherein a first output of the IQ generation circuit is coupled to the transmit circuit of the first transmit chain via a first mixer of the first transmit chain, and a second or branched output of the IQ generation circuit is coupled to the transmit circuit of the second transmit chain via a second mixer of the second transmit chain.

[0013] Some of these aspects are configured such that the device is configured to concurrently transmit multiple radar signals at different corresponding frequencies via a first transmission chain and a second transmission chain.

[0014] Some of these aspects are configured such that the first and second transmit chains share a frequency-modulated continuous wave-intermediate frequency (FMCW-IF) circuit. Some of these aspects are configured such that a first output of the FMCW-IF circuit is coupled to the transmit circuit of the first transmit chain via a first mixer of the first transmit chain, and a second OR branch output of the FMCW-IF circuit is coupled to the transmit circuit of the second transmit chain via a second mixer of the second transmit chain. Some of these aspects are configured such that a second OR branch output of the FMCW-IF circuit is coupled to the second mixer via a frequency adjustment circuit. Some of these aspects are configured such that the frequency adjustment circuit includes interference reduction circuitry. Some of these aspects are configured such that the frequency adjustment circuit includes a frequency offset circuit.

[0015] Some of these aspects are configured such that a first transmission chain generates a first signal, and a second transmission chain generates a second signal orthogonal to the first signal. Some of these aspects are configured such that the first signal is a first pseudo-random (PN) shaped signal, and the second signal is a second PN shaped signal orthogonal to the first PN shaped signal.

[0016] Some of these aspects are configured such that a first transmission chain and a second transmission chain are configured for transmission in a first transmission direction, wherein the chirp pattern of the transmission signal for the first transmission chain is orthogonal to the chirp pattern of the transmission signal for the second transmission chain.

[0017] Some of these aspects are configured such that a third transmission chain and a fourth transmission chain are configured for transmission in a second transmission direction orthogonal to a first transmission direction, and wherein the chirp pattern of the transmission signal for the third transmission chain is orthogonal to the chirp pattern of the transmission signal for the fourth transmission chain.

[0018] Some of these aspects are configured with a shared receive path and processing circuitry configured to perform source separation on the received signal to identify individual return chirp signals from a first transmit chain and a second transmit chain. Some of these aspects are configured such that the processing circuitry is configured to use a trained source separation machine learning algorithm to identify individual return chirp signals. Some of these aspects are configured such that the trained source separation machine learning algorithm uses one or more of the following to identify individual return chirp signals: signal level, signal index, signal slope direction, and signal frequency domain.

[0019] Some of these aspects are configured such that a first transmit chain is disposed in a first radio frequency front-end (RFFE) module, and a second transmit chain is disposed in a second RFFE module. Some of these aspects are configured such that the first RFFE module includes a first antenna coupled to the first transmit chain, wherein the first antenna covers a first spatial location, and the second RFFE module includes a second antenna coupled to the second transmit chain, wherein the second antenna covers a second spatial location different from the first spatial location.

[0020] In some aspects, the apparatus described above can function in a system including a mobile device having a camera for capturing one or more images. In some aspects, the apparatus described above may include a display screen for displaying one or more images or an interface display. In some aspects, additional wireless communication circuitry is provided. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used independently to determine the scope of the claimed subject matter. This subject matter should be understood with reference to the appropriate portions of the specification throughout, any or all of the drawings, and each claim.

[0021] The foregoing, as well as other features and embodiments, will become more apparent from the following description, claims and drawings. Attached Figure Description

[0022] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter characters, such as "102a" or "102b", the letter characters distinguish two similar parts or elements in the same drawing. When the aim is to have the reference numerals cover all parts with the same reference numerals in all drawings, the letter characters of the reference numerals may be omitted.

[0023] Figure 1 This is a diagram illustrating a wireless communication system that communicates with a wireless device that can be implemented according to the aspects described herein.

[0024] Figure 2 This is a block diagram illustrating an apparatus according to various aspects described herein, the apparatus including a subsystem for supporting multiple quadrature transmissions utilizing a shared phase-locked loop (PLL) circuit.

[0025] Figure 3 This is a schematic diagram illustrating elements of a specific implementation of a system according to the aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit.

[0026] Figure 4 This is a schematic diagram illustrating elements of a specific implementation of a system according to the aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit.

[0027] Figure 5 This is a schematic diagram illustrating elements of a specific implementation of a system according to the aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit.

[0028] Figure 6 This is a schematic diagram illustrating elements of a specific implementation of a system according to the aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit.

[0029] Figure 7 This is a schematic diagram illustrating elements of a specific implementation of a system according to the aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit.

[0030] Figure 8A Details of the orthogonal radar signals received by the device according to the aspects described herein are illustrated.

[0031] Figure 8B Details of a system for separating orthogonal radar signals, based on various aspects described herein, are illustrated.

[0032] Figure 9 This is a flowchart illustrating various aspects of a method for generating orthogonal transmission signals according to the aspects described herein.

[0033] Figure 10 This is a functional block diagram of an apparatus according to some aspects of the present disclosure, the apparatus including multiple transmit chains having shared PLL circuitry.

[0034] Figure 11 These are illustrations of environments including electronic devices and base stations that can be used with various aspects of this disclosure.

[0035] Figure 12 This is an illustration of an electronic device that can be used with various aspects of this disclosure.

[0036] Figure 13A These are illustrations of various aspects of an RF front-end described herein, which is suitable for use in a specific implementation having a shared PLL circuit for multiple transmit paths.

[0037] Figure 13B Elements of an RF chain according to some aspects described herein are illustrated. Detailed Implementation

[0038] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of exemplary aspects and specific embodiments, and is not intended to represent the only specific embodiments in which the invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of exemplary aspects and specific embodiments. In some instances, some devices are shown in block diagram form. Drawing elements common in the following drawings may be identified using the same reference numerals.

[0039] The development of wireless communication infrastructure, such as the 3GPP 5G millimeter-wave (mmW) systems, has increased the importance of the radio frequency (RF) front-end (RFFE). For example, the 5G standard for cellular communications involves increased complexity in frequency combinations and communication throughput options. Furthermore, as communication systems expand to higher frequencies (including millimeter-wave (mmW) frequencies), additional functionalities can be included in such RFFEs for applications such as radar for local object detection, 3D mapping, localization, gesture detection, and other similar applications.

[0040] The aspects described herein include an architecture for supporting multiple RFFE radar transmission subsystems. Each such subsystem may include transmission chains, where some parts of different chains are shared (e.g., phase-locked loop circuitry), while others are separate. Some aspects of this architecture can operate to enable different radar transmissions with unique combinations of characteristics, including bandwidth and carrier frequency. Such characteristics can allow for improved range and wider sliding resolution, while reducing power consumption by sharing common modules. As described herein, a single chain is a separate circuit for transmitting radar signals. A single chain may include multiple paths of signals for phased array operation, such that, as described herein, individual signals destined for individual elements of the phased array are not separate chains, but rather part of a chain within the phased array. In some aspects, separate chains are configured to transmit radar signals simultaneously.

[0041] Additionally, pseudo-random (PN) shaping of radar transmissions can be provided at different transmission chains to improve orthogonality and simplify source separation processing in the receiver circuitry. A trained machine learning processing system at the receiver circuitry can also be used to perform source separation. This source separation offers benefits, particularly in the context of continuous and / or simultaneous transmission of radar signals from separate transmission chains.

[0042] Further details regarding the aspects described herein are provided with reference to the following figures.

[0043] Figure 1This is a diagram illustrating wireless device 110 communicating with wireless communication system 120. According to aspects described herein, the wireless device may include electronic equipment having wireless communication capabilities enabled by RFFE circuitry along with other wireless communication elements. According to aspects described herein, devices within system 120 (such as wireless device 110) may use multiple radar subsystems or modules with shared elements.

[0044] The wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. The communication elements of the wireless device 110 used to implement mmW and non-mmW communication according to any such communication standard can be supported by various designs of transceivers, such as those using chained signal routing. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Generally, a wireless communication system may include any number of base stations and any set of network entities.

[0045] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet computer, or other such mobile device (e.g., a device integrated with a display). Other examples of wireless device 110 include wireless modems, personal digital assistants (PDAs), handheld devices, laptops, smartbooks, netbooks, tablet computers, cordless phones, medical devices, devices configured (e.g., via the Internet of Things) to connect to one or more other devices, automotive or other motor vehicle equipment, wireless local loop (WLL) stations, Bluetooth devices, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., broadcast station 134) and / or communicate with satellites (e.g., satellites 150, etc., in one or more Global Navigation Satellite Systems (GNSS)). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0046] The wireless communication system 120 may also include a wireless device 160. In an exemplary embodiment, the wireless device 160 may be a wireless access point, or another wireless communication device that includes or is a part of a wireless local area network (WLAN). In an exemplary embodiment, the wireless device 110 may be configured as a customer premises equipment (CPE) that can communicate with a base station 130 and another wireless device 110 or other devices in the wireless communication system 120. In some embodiments, the CPE may be configured to communicate with the wireless device 160 using WAN signaling and to interleave with the base station 130 based on this communication, rather than the wireless device 160 communicating directly with the base station 130. In an exemplary embodiment where the wireless device 160 is configured to communicate using WLAN signaling, the WLAN signal may include WiFi or other communication signals.

[0047] Figure 2 This is a block diagram illustrating a wireless device 200 in which various aspects of the present disclosure may be implemented. Wireless device 200 may be a communication device, such as wireless device 110, etc. Figure 11 The illustrated electronic device 1102, such as Figure 12 The illustrated electronic device 1202, or any device described herein, or other such device. As illustrated, the wireless device 200 includes multiple radar subsystems 230, 240, and 250. Each of the radar subsystems 230, 240, and 250 has an associated transmission chain. In some examples, one or more of the radar subsystems 230, 240, and 250 are encapsulated in a corresponding module, such as including an associated transmission chain and an antenna array. In some such examples, the transmission chain (or multiple transmission chains) is implemented in an RF integrated circuit (RFIC). Several aspects described herein are discussed in the context of mmW communication and mmW transmission chains. Based on the details provided herein, any frequency suitable for a particular radar application can be used. In some aspects, the radar module may cover FR1, FR2, and / or FR3, depending on the resource configuration of the RF blocks in the device. In some aspects, the radar module may cover frequencies below 6 GHz. In some aspects, it may cover 24.25 GHz–52.6 GHz and / or 6 GHz–24.25 GHz. In other respects, other frequency ranges can be covered. Wireless device 200 uses subsystems 230, 240, and 250 to perform simultaneous radar signal transmission. Different radar signal transmissions are generated using different characteristics that allow one or more receivers to distinguish the returned signals based on these different characteristics (e.g., matching the details of the signal at a single receiver with the associated transmission chain).

[0048] Three subsystems 230, 240, and 250 are shown as having individual associated directivity. Subsystem 230 is associated with a first transmission direction 231, subsystem 240 with a second transmission direction 241, and subsystem 250 with a third transmission direction 251. Although three subsystems with three associated transmission directions are shown, the device can have any number of associated transmission directions and any number of subsystems, for example, enabling the receiver to separate signals received from different transmission links, or the signals to be sufficiently spatially separated (e.g., it is unlikely that a return signal from transmission direction 251 will be received at the receiver of subsystem 240 sensed in transmission direction 241). In some examples, the radar subsystem is configured to transmit in more than one direction (e.g., two substantially orthogonal directions).

[0049] In addition to spatially separating transmitted signals using the transmission directionality of each of radar subsystems 230, 240, and 250, each subsystem 230, 240, and 250 may also include multiple transmission chains, wherein each transmission chain of each subsystem generates a transmitted signal with discriminative characteristics. For example, radar subsystem 240 may generate two transmitted signals 242 having different combinations of bandwidth and / or carrier frequency characteristics, and / or may have pseudo-random chirp signal shaping to generate orthogonal chirp signals.

[0050] As illustrated, subsystem 230 can generate multiple transmitted signals 232 in the transmission direction 231, subsystem 240 can generate multiple transmitted signals 242 in the transmission direction 241, and subsystem 250 can generate multiple transmitted signals 252 in the transmission direction 251. Therefore, the transmitted signals from different subsystems 230, 240, and 250 are spatially separated, and the transmitted signals from each subsystem have different characteristics and / or signal chirping. However, not every radar subsystem in the wireless device 200 needs to generate multiple signals with different characteristics, and any of subsystems 230, 240, and 250 can omit this functionality.

[0051] Different specific implementations of device 200 may include various subsystems having any number of transmission chains. Subsystem 230 may include multiple mmW transmission chains, including a first mmW transmission chain and a second mmW transmission chain to generate a transmission signal 232 in a first transmission direction 231, wherein the chirp pattern of the transmission signal for the first mmW transmission chain is orthogonal to the chirp pattern of the transmission signal for the second mmW transmission chain. Subsystem 240 may include a third mmW transmission chain and a fourth transmission chain, both of which are configured for transmission in a second transmission direction 241 orthogonal to the first transmission direction, wherein the chirp pattern of the transmission signal for the third mmW transmission chain is orthogonal to the chirp pattern of the transmission signal for the fourth mmW transmission chain. The chirp pattern of the transmission signal 242 for subsystem 240 may be similar to the chirp pattern of signal 232, or they may be different, depending on the design and spatial separation of transmission directions 231 and 241. If all transmissions are orthogonally chirped, overlap between the transmission direction and the expected return signal can be tolerated to some extent, and the return signal can be separated according to the source used by processing the return signal (e.g., individual return chirped signals can be identified from a single received signal by the PN chirped envelope and / or any other distinguishing characteristic). Although the above example describes a finite number of subsystems and transmission chains for each subsystem, any number of subsystems and transmission chains can be used in different specific implementations (e.g., the transmitted signals have different characteristics that can be separated by receive processing).

[0052] The return signals transmitted by the radar from each subsystem 230, 240, and 250 are spatially separated from transmissions from another subsystem 230, 240, and 250, which may otherwise be similar. The return signals from different transmission chains, as well as combinations of transmission signals 232, 242, and 252, can be separated based on characteristics and / or PN chirp shaping. For example, a trained machine learning system can be used to perform this separation. Additional details of such operations are described below relative to... Figure 8A and Figure 8B To describe.

[0053] Figure 3 This is a schematic diagram illustrating elements of a specific implementation of a system 300 according to various aspects described herein, the system having multiple transmission chains supported by a shared PLL circuit 301.

[0054] In system 300, three mmW transmission chains are illustrated. All three transmission chains include a shared circuit 306, which... Figure 3The system includes a shared frequency modulated continuous wave (FMCW) intermediate frequency (IF) circuit 308. The first transmission chain includes a shared circuit 306 and a separate circuit 310. The separate circuit 310 includes an up-conversion circuit 312 (e.g., a mixer) and a transmission circuit 314. The up-conversion circuit 312 up-converts the shared transmission signal from the FMCW-IF circuit to the transmission frequency. According to the aspects described herein, the transmission circuit 314 may include filters, phase shifters, amplifiers, circuitry for applying shaping functions, antennas, or any other such elements to support the transmission of mmW radar signals. While the aspects described herein are in the context of FMCW, other radar signals and radar technologies may be used according to the specific implementations described herein.

[0055] Similar to the first transmission chain, the second transmission chain includes a shared circuit 306 and a separate circuit 320. The separate circuit 320 includes multiple elements, including an up-conversion circuit 322 and a transmission circuit 324. The third transmission chain includes a shared circuit 306 and a separate circuit 330. The separate circuit 330 includes multiple elements, including an up-conversion circuit 332 and a transmission circuit 334. The up-conversion circuits 322 and 332 up-convert the shared transmission signal from the FMCW-IF circuit to the transmission frequency. According to various aspects described herein, the transmission circuits 324 and 334 may include filters, phase shifters, amplifiers, circuitry for applying shaping functions, antennas, or any other such elements to support the transmission of mmW radar signals. In some examples, the shared circuit 306 is configured to provide a baseband FMCW signal, and the up-conversion circuits 312, 322, and 332 are configured to directly up-convert the baseband FMCW signal to the transmission frequency.

[0056] System 300 additionally includes a shared phase-locked loop (PLL) circuit 301, which has a shared PLL output section 301A, with separate circuits 310 for the first mmW transmission chain, 320 for the second mmW transmission chain, and 330 for the third mmW transmission chain each coupled to the shared PLL output section 301A. Figure 3 In the example, the shared PLL output 301A is coupled to each of the mmW transmit chains via the local oscillator (LO) circuit 303.

[0057] A separate circuit 320 of the second mmW transmit chain is additionally coupled to the shared PLL circuit 301 via a first divider circuit 329. The first and second mmW transmit chains share a shared mmW transmit signal from the FMCW-IF circuit 308. The first divider circuit 329 modifies (e.g., divides) the frequency of the signal supplied from the LO circuit 303 to the upconverter circuit 322 such that the transmit signal generated by the second mmW transmit chain (e.g., from the shared transmit signal mixed with the LO signal input to the upconverter circuit 322) will be different from the transmit signal generated by the first mmW transmit chain (e.g., from the shared transmit signal mixed with the LO signal input to the upconverter circuit 312) (e.g., having at least one different characteristic). As described herein, the divider circuit (such as the first divider circuit 329) may be a programmable divider circuit. Alternatively, the divider circuit may be fixed according to the specific application of a particular design. For example, the divider circuitry for one path may be fixed to a different value than the divider circuitry for another path (e.g., in some mmW applications, the value for the first path (e.g., first divider circuitry 329) is 2 and the value for the second path (e.g., divider circuitry 339) is 3, or the value for one path is 60 and the value for another path is 30). In other respects, the divider circuitry may be identical for multiple paths, or it may be programmably configured for one or more paths.

[0058] Figure 3 Additionally, a third mmW transmission chain is included, which is configured to generate an output transmission signal having at least one characteristic different from that of the first and second transmission chains due to the frequency divider circuit 339. For example, when the shared mmW transmission signal received at the upconversion circuit 332 is mixed with the LO signal modified by the frequency divider circuit 339, the output transmission signal from the third mmW transmission chain has a different frequency characteristic than the output signals from the first and second mmW transmission chains.

[0059] Additionally, as described above, the transmitting circuits 314, 324, and 334 may include circuitry for PN shaping for each corresponding mmW transmit output. This PN shaping, along with frequency modification, can generate a signal in the shared direction that can be separated by the receiver's processing circuitry when the return pulse from the transmit output is received as a single signal (e.g., on a single shared receive antenna).

[0060] Figure 3 The three mmW transmit channels can be used to generate transmit signals (e.g., Figure 2Signals 232, 242, and 252. In some respects, all signals from these three channels share a common direction. In other respects, these signals may have different associated directions, and additional characteristics are used to distinguish them when return signals transmitted from different directions are detected by the same receiver. In some respects, additional copies of separate circuits 310, 320, and 330 can be added to provide transmission output for different directions (e.g., transmission directions 231, 241, and 251, or directions orthogonal to the plane of the wireless device 200, such as entering or leaving a page to move away from the back cover or screen of the wireless device 200). For example, nine transmission channels can be used, three of which are for... Figure 2 Signals are provided in each of the transmission directions 231, 241, and 251. In some aspects, each packet of the three channels may have a separate FMCW-IF circuit 308, PLL circuit 301, and LO circuit 303. In other aspects, all nine transmission channels may share the same FMCW-IF circuit 308. Similarly, in some aspects, a transmission chain in each transmission direction may share a frequency divider circuit 329, and a transmission chain in each transmission direction may share a frequency divider circuit 339.

[0061] As described in further detail below, an RF chain may include a distributed amplifier coupled to a Tx antenna, a LO circuit, and an Rx low-noise amplifier coupled to an Rx antenna. In some aspects, the intermediate frequency (IF) signal may be shared as a common signal (e.g., to other circuitry within the transceiver chip), and different chains may be distributed within a specific RF transceiver of a common chip or across chips, for example, within the respective IC or chip, as may be implemented in the respective subsystems 230, 240, 250. In some aspects, shared PLL and / or LO circuitry may be available in each specific RF transceiver. In some aspects with common circuitry spanning multiple integrated circuit chips, the PLL and / or LO circuitry may be shared within the IF transceiver or, similar to a clock signal, routed from the transceiver chip including the RF chain to other transceivers (e.g., chips or ICs) (e.g., by routing from one RF transceiver to other RF transceivers).

[0062] As described above, such combinations of components achieve reduced power dissipation, while different mmW transmit chains provide different combinations of transmit characteristics (e.g., direction, frequency, PN envelope, etc.). The provided combinations enable complex radar systems with multiple simultaneous transmit pulses and efficient receiver sensing, where the return signal can be matched to the transmitted signal based on its characteristics, thereby minimizing cross-coupling and facilitating signal decoupling. Examples of mmW transmit chains are provided in some examples above and below; however, one or more transmit chains can be configured for another frequency, such as sub-THz, FR3, sub-6GHz, etc. Furthermore, while examples of transmit circuitry are provided herein, similar configurations can be implemented for receive circuitry, for example, by replacing the amplifier used for transmit with an amplifier used for receive, and by reversing the flow of the radar signal.

[0063] Figure 4 This is a schematic diagram illustrating elements of a specific implementation of system 400 according to various aspects described herein, having multiple transmit chains supported by a shared PLL circuit 401. Similar to system 300, system 400 has three mmW transmit chains, each with a shared circuit 406. However, the shared circuit 406 differs from the shared circuit 306 in that an FMCW modulation (FMCW-MOD) circuit 408 provides an input to the PLL circuit 401, causing the shared PLL output 401A to provide a shared transmit frequency signal (e.g., instead of...). Figure 3 The shared IF signal is up-converted by a separate up-conversion circuit. Figure 3 There are LO circuits between the shared PLL circuit and the individual circuits of each chain.

[0064] The separate circuit 410 of the first mmW transmission chain directly receives the shared transmission signal and uses the first transmission circuit 414 to output the first mmW transmission. The second mmW transmission chain has a separate circuit 420, which includes a frequency divider circuit 429 and a transmission circuit 424. In some respects, the frequency divider circuit 429 may be configured with a separate circuit 410, and in other respects, the frequency divider circuit 429 may be separated as a design choice (e.g., to keep the frequency divider circuit 429 or similar circuitry very close to the upconverter). Unlike using an adjusted LO during upconversion to generate a second output signal with a different frequency than the first output signal of the first mmW transmission chain, the frequency divider circuit 429 directly modifies the frequency of the transmission signal of the second mmW transmission chain. In other respects, split outputs may be used. Similarly, the third mmW transmission chain includes a separate circuit 430, which includes a frequency divider circuit 439 and a transmission circuit 434. As described above, the system 400 is capable of generating output transmissions from different mmW transmission chains with different frequency characteristics. Additionally, as described above, transmitting circuits 414, 424, and 434 can provide additional distinguishing characteristics for different output transmissions, such as PN chirped modulation, and / or can be configured similarly to transmitting circuits 314, 324, and 334. Furthermore, as mentioned above, additional mmW transmissions can be configured for the device by replicating some or all of the components of the illustrated mmW transmission chain. Frequency divider circuits 429 and 439 can be programmable frequency divider circuits or can be fixed. For example, frequency divider circuit 429 can be configured for a 2-fold division, and frequency divider circuit 439 can be configured for a 3-fold division.

[0065] Figure 5 This is a schematic diagram illustrating elements of a specific implementation of system 500 according to various aspects described herein, the system having multiple transmit chains supported by a shared PLL circuit 501. System 500 can be considered as... Figure 3 and Figure 4 The intermediate architecture between the architectures. Similar to systems 300 and 400, system 500 presents three mmW transmit chains, each including a shared circuit 506. However, the shared circuit 506 includes an FMCW-IF circuit 508 (e.g., similar to...). Figure 3The shared upconverter circuit 501 (e.g., a shared mixer) is connected to the FMCW-IF circuit 508 and the shared upconverter circuit 512. A shared IF signal is output from the FMCW-IF circuit and input to the shared upconverter circuit 512. Similarly, similar to system 300, the shared PLL circuit 501 has a shared PLL output 501A that supports the shared LO circuit 503. A transmission frequency signal is generated by mixing the IF signal from the FMCW-IF circuit 508 with the LO signal from the LO circuit 503 at the upconverter circuit 512. The transmission frequency signal is output from the upconverter circuit 512 to separate circuits 510, 520, and 530 for three different mmW transmission chains.

[0066] Similar to system 400, the variation in output transmission frequency is provided by a frequency divider circuit. The frequency divider circuit 529 of the second mmW transmission chain provides the adjusted transmission signal to the transmission circuit 524 of the separate circuit 520. The frequency divider circuit 539 of the third mmW transmission chain provides the adjusted transmission signal to the transmission circuit 534 of the separate circuit 530. Transmission circuits 514, 524, and 534 then generate output transmissions with different frequency characteristics. Transmission circuits 514, 524, and 534 can be configured in a similar manner to transmission circuits 314, 324, and 334. As described above, additional discrimination characteristics can be applied depending on the radar system configuration to allow for efficient reception processing of the returned signals, where the transmission characteristics are used for source separation when processing simultaneous returned signals from multiple mmW transmission chains at the receiver. The frequency divider circuits 529 and 539 can be programmable frequency divider circuits or they can be fixed. For example, the frequency divider circuit 529 can be a first programmable frequency divider, and the frequency divider circuit 539 can be a second programmable frequency divider; the latter can be set to the same or different values, or it can be a frequency divider with a fixed division ratio.

[0067] Figure 6 This is a schematic diagram illustrating elements of a specific implementation of system 600 according to various aspects described herein, having multiple transmit chains supported by a shared PLL circuit 601. System 600 illustrates two separate mmW transmit chains. In system 600, the two separate mmW transmit chains have different IQ characteristics, rather than the adjusted frequency characteristics as in systems 300, 400, and 500 described above.

[0068] In system 600, a first mmW transmit chain includes a shared circuit 606, which includes an FMCW-IF circuit 608 and an IQ generation circuit 609. The IQ generation circuit provides a separate IQ transmit signal to a separate circuit 610 of the first mmW transmit chain. A second mmW transmit chain includes the shared circuit 606 and a separate circuit 620. The second mmW transmit chain receives an alternative signal from the IQ generation circuit 609. A shared PLL circuit 601, having a shared PLL output section 601A, drives an LO circuit 603, which provides a shared LO signal to the upconversion circuits of the two different mmW transmit chains. The upconversion circuit 612 of the first mmW transmit chain receives the shared LO signal from the LO circuit 603 and a separate signal from the IQ generation circuit 609 to generate an output signal for the transmit circuit 614. The upconversion circuit 622 of the second mmW transmit chain receives the shared LO signal from the LO circuit 603 and a separate signal from the IQ generation circuit 609 to generate an output signal for the transmit circuit 624. The individual portions of the IQ output provide different characteristics for the transmitted signal, so that these characteristics can be identified if a return signal is simultaneously received in the receiver as described above. Transmitting circuits 614 and 624 can be configured in a similar manner to transmitting circuits 314 and 324.

[0069] Furthermore, although system 600 is shown as independent of systems 300, 400, and 500, the frequency tuning for different mmW transmit chains in systems 300, 400, or 500 can be combined with IQ separation system 600 to provide additional characteristics for different mmW transmit chains in a single device. For example, two additional transmit chains can be added. Figure 6 This architecture couples the shared circuit 606 to the third and fourth mmW transmit chains, and also uses the same PLL circuit 601 and LO circuit 603, but adds a divider circuit between the LO circuit 603 and the upconversion circuits of the third and fourth mmW transmit chains. Each of the third and fourth transmit chains can share the output of the IQ generation circuit 609 with the other chain, or a separate output from the IQ generation circuit 609 can be coupled to each chain. This architecture provides distinctiveness for each transmit chain, allowing return signals captured in a single simultaneous receiver signal to be separated by processing based on the transmit characteristics of the different mmW transmit chains.

[0070] Figure 7 This is a schematic diagram illustrating elements of a specific implementation of system 700 according to various aspects described herein, having multiple transmit chains supported by a shared PLL circuit 701. Like system 600, system 700 provides additional mechanisms for providing distinguishable characteristics to the mmW transmit chains within the system.

[0071] exist Figure 7In this system 700, the shared circuit 706 includes an FMCW-IF circuit 708, and the separate circuit 710 for the first mmW transmission channel includes an up-conversion circuit 712 and a transmission circuit 714. A shared PLL circuit 701 with a shared PLL output section 701A is used in the system 700 with a shared LO circuit 703. The second mmW transmission chain also includes a separate circuit 720 with an up-conversion circuit 722 and a transmission circuit 724. However, the separate circuit 720 for the second mmW transmission chain includes a frequency offset circuit 745. The frequency offset circuit 745 includes a mixer 747 and an amplifier 749, both of which can be used to provide a shifted frequency characteristic of the transmitted signal in the second mmW transmission chain, and to adjust the associated frequency characteristics of the transmitted signal output from the second mmW transmission signal. Figure 7 In the illustrated example, circuit 745 is configured to shift the frequency of the signal in the second mmW transmission chain by an amount equal to the bandwidth of the FMCW signal. Other configurations can also be implemented, for example, to shift the frequency of the signal in the second mmW transmission chain by a larger amount. In some specific implementations, the frequency shift circuit can be used for interference reduction to specifically target particular interference in the design, as well as to achieve error reduction and performance improvement. As described above with respect to system 600, frequency shift circuit 745 can be combined with elements of any other system described herein to provide different transmission characteristics that can be identified when the receiver processes the returned signal. Transmission circuits 714, 724 can be configured in a similar manner to transmission circuits 314, 324. Figure 3 and Figure 7 In the example, IF circuits 308 and 708 can be configured to provide (FMCW) radar signals at two outputs, or the shared output can be split into two signals.

[0072] Figure 8AFigure 801 illustrates details of orthogonal radar signals received by the device according to various aspects described herein. Figure 801 illustrates various aspects of the signal at the receiver when multiple return signals from simultaneous transmissions are sensed. An example of Figure 801 illustrates details of a system operating at a resolution frequency value of approximately 14.68 Hz and a time resolution value of 100 ms. Figure 801 illustrates the received power over time. Within the received data shown in Figure 801, return signals from a first transmission 880 and a second transmission 890 can be identified. The return signal from the first transmission 880 has a downward sloping characteristic 882 within the identified time period, and the return signal from the second transmission 890 has an upward sloping characteristic 892 within the same time period. Such characteristics can be identified by processing at the receiver to match return signals from a specific mmW transmission chain. Additionally, in some aspects, such slope directions can be used by a trained source separation machine learning system using machine learning algorithms to identify individual return signals. Machine learning algorithms can utilize not only this slope direction characteristic but also other characteristics such as signal level (e.g., power level), signal index, and signal frequency domain. In some respects, the two distinct signals are generated from different sources to allow for parallel detection. These sources are configured differently (e.g., one rising, one falling), and the rising and falling slope characteristics of the two transmitted signals are reflected in the returned signal, aiding in the separation of the returned signal.

[0073] Figure 8BDetails of a system 800 for separating orthogonal radar signals according to aspects described herein, and details of machine learning circuitry for use in a receiver according to aspects described herein, are illustrated. Signal 802 may be a returned signal received from the radar at a receiving system of a single subsystem (e.g., subsystems 230, 240, 250) (e.g., including both a returned signal from a first transmitter 880 and a returned signal from a second transmitter 890). In some aspects, signal 802 is a down-converted signal generated from a transmitted frequency (e.g., mmW, below 6 GHz, etc.). Analog-to-digital converter circuitry 806 provides the digital signal, along with any other input 808, to feature extraction circuitry 810. Other inputs 808 may be control inputs configured to identify or select features to be extracted from the digital version of signal 802 output by ADC 806. In some aspects, other inputs may be sensor signals such as angle of arrival (AoA) or angle of departure (AoD), acceleration signals, velocity signals, signal levels, slope direction of chip signals from the Tx path, module ID signals, etc. The time-slicing circuit 812 divides the information from signal 802 and input 808 into dynamic time slices and uses this information to create discrete inputs to a machine learning network 820 (e.g., the machine learning network can use a trained machine learning algorithm to identify portions of signals originating from different mmW transmission chains with different characteristics), which provides output 830. Additional or alternative strategies for separating received (e.g., reflected) radar signals, such as strategies that do not require machine learning, can be implemented.

[0074] ADC circuit 806 can be used to manage data bandwidth to align incoming data with the operating rate of network 820. Feature extraction circuit 810 can then accept state tracking data matched to the operating rate of network 820 using time-slicing circuit 812. The rhythmic state tracking data is then provided to network 820 for machine learning analysis and control selection of a given time-slice of the returned signal, which may include radar reflections from multiple radar transmitters. Target data can be used to train or calibrate network 820 to generate a control signal at output 830, thereby tracking the desired signal based on the characteristics of the transmitted signal and PN shaping. The control signal generated by output 830 can be tailored for system applications such as object or obstacle detection, channel estimation for wireless communication, map generation, smart transmission, vehicle radar, gesture detection, etc.

[0075] Figure 9This is a flowchart illustrating an example of the operation of method 900 according to various aspects described herein, for operating an apparatus comprising one or more radar subsystems having multiple transmission chains having shared elements. The blocks in method 900 may be performed in the order shown or not, and in some embodiments, may be performed at least partially in parallel.

[0076] Method 900 includes block 902, which describes generating a first radar signal using radar signal generation circuitry and a first transmission chain coupled to a shared PLL circuitry.

[0077] Method 900 also includes block 904, which describes the generation of a second radar signal using radar signal generation circuitry and a second transmission chain coupled to a shared PLL circuitry.

[0078] Some specific implementations of method 900 may include additional steps, intermediate steps, and / or repetitive steps. For example, in some aspects, method 900 further includes receiving a first return radar signal and a second return radar signal as a joint received signal on a receiving path, and performing source separation on the joint received signal using a trained source separation machine learning algorithm to identify individual return signals and separate them into a first return radar signal associated with the first radar signal and a second return radar signal associated with the second radar signal. Other aspects of this specific implementation of method 900 include that the trained source separation machine learning algorithm uses one or more of the following to identify individual return signals: signal level, signal index, signal slope direction, and signal frequency domain.

[0079] Further operations of method 900 may include operations based on any information associated with a shared PLL for a wireless communication device provided herein.

[0080] Figure 10 This is a functional block diagram of device 1000, which includes an architecture for transmitting multiple radar signals using a transmission chain having shared elements. Device 1000 includes a component 1002 for generating a first radar signal using a radar signal generation circuit and a first transmission chain coupled to a shared PLL circuit, and a component 1004 for generating a second radar signal using a radar signal generation circuit and a second transmission chain coupled to a shared PLL circuit.

[0081] Figure 11This is a diagram illustrating an exemplary environment 1100 including electronic device 1102 and base station 1104. According to the examples described herein, the electronic device may include a transceiver having multiple transmission chains (e.g., wireless transceiver 1122 of electronic device 1102) sharing common elements. In some aspects, any element of a system (such as the system in environment 1100) may include a transceiver according to the aspects described herein. In environment 1100, electronic device 1102 communicates with base station 1104 via wireless communication link 1106 (wireless link 1106). In such examples, electronic device 1102 is depicted as a smartphone. However, electronic device 1102 may be implemented as any suitable computing or other electronic device, such as a cellular base station, broadband router, access point, cellular or mobile phone, gaming device, navigation device, media device, laptop computer, desktop computer, tablet computer, server, network attached storage (NAS) device, smart appliance, vehicle-based communication system, Internet of Things (IoT) device, etc.

[0082] Base station 1104 communicates with electronic device 1102 via wireless link 1106, which can be implemented as any suitable type of wireless link. Although depicted as a base station tower of a cellular radio network, base station 1104 can represent or be implemented as another device, such as a satellite, cable television headend, terrestrial television broadcasting tower, access point, peer-to-peer device, mesh network node, router, fiber optic line, or generally another electronic device. Therefore, electronic device 1102 can communicate with base station 1104 or another device via wired connection, wireless connection, or a combination thereof.

[0083] Wireless link 1106 may include a downlink transmitting data or control information from base station 1104 to electronic device 1102, and an uplink transmitting other data or control information from electronic device 1102 to base station 1104. Wireless link 1106 may use any suitable communication protocol or standard, such as 3GPP LTE, 3GPP 5GNR, IEEE 802.11, IEEE 802.16, Bluetooth, etc. ™ (etc.) to achieve this.

[0084] Electronic device 1102 includes processor 1108 and computer-readable storage medium 1110 (CRM 1110). Processor 1108 may include any type of processor, such as an application processor or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored in CRM 1110. CRM 1110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., magnetic disk or magnetic tape), etc. In the context of this disclosure, CRM 1110 is implemented to store instructions 1112, data 1114, and other information of electronic device 1102, and therefore does not include transiently propagated signals or carrier waves.

[0085] Electronic device 1102 may also include input / output port 1116 (I / O port 1116) or display 1118. I / O port 1116 enables data exchange or interaction with other devices, networks, or users. I / O port 1116 may include serial ports (e.g., Universal Serial Bus (USB) ports), parallel ports, audio ports, infrared (IR) ports, and so on. Display 1118 may be implemented as a screen or projection that displays graphics of electronic device 1102, such as one or more graphic images, such as user interfaces associated with an operating system, program, or application. Alternatively or otherwise, display 1118 may be implemented as a display port or virtual interface through which the graphical content of electronic device 1102 is conveyed or presented.

[0086] For communication purposes, electronic device 1102 also includes a modem 1120, a wireless transceiver 1122, and at least one antenna 1130. According to the aspects described herein, the wireless transceiver 1122 includes a subsystem 1124 having a shared PLL for multiple transmit chains. Figure 11 In the example, the PLL is located within a module, subsystem, or IC. In other respects, a PLL can be shared by a chain of single modules, subsystems, or ICs, or it can be linked between different ICs, for example, relative to... Figure 13BAs described. Such transmission chains can be used to transmit radar signals and / or communication signals. In some examples, communication signals are processed by a portion of transceiver 1122 that is not within subsystem 1124, or is shared with subsystem 1124 but does not have all the functionality of the shared PLL system described above. Wireless transceiver 1122 uses RF wireless signals to provide connectivity to the corresponding network and other electronic devices connected thereto. Additionally or alternatively, electronic device 1102 may include a wired transceiver (such as an Ethernet or fiber optic interface) for communication over a personal or local network, intranet, or the Internet. Wireless transceiver 1122 facilitates communication on any suitable type of wireless network, such as wireless local area network (LAN) (WLAN) (such as Wi-Fi or Bluetooth), peer-to-peer (P2P) network, mesh network, cellular network (e.g., 3GPP2, 4G LTE, 5G NR, or other cellular networks), wireless wide area network (WWAN) (e.g., based on 3GPP2, 4G LTE, 5G NR, etc.), navigation network (e.g., North American Global Positioning System (GPS) or another Satellite Positioning System (SPS)), and / or wireless personal area network (WPAN). In the context of exemplary environment 1100, wireless transceiver 1122 enables electronic device 1102 to communicate with base station 1104 and the network connected thereto. Other figures referenced herein may relate to other wireless networks.

[0087] Modem 1120 (such as a baseband modem) may be implemented as a system-on-a-chip (SoC) that provides a digital communication interface for data, voice, messaging, and other applications of electronic device 1102. In some aspects, such a modem may include the components described above (e.g., feature extraction circuitry 810, AI / ML network 820, output 830, etc.). Other specific implementations may include other elements as described herein. Modem 1120 may also include baseband circuitry to perform high-rate sampling processes, which may include analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), gain correction, tilt correction, frequency conversion, etc. Modem 1120 may also include logic performing in-phase / quadrature (I / Q) operations, such as synthesis, encoding, modulation, demodulation, and decoding. More generally, modem 1120 may be implemented as a digital signal processor (DSP) or a processor configured to perform signal processing to support communication via one or more networks. Alternatively, ADC or DAC operations may be performed by a separate component or another exemplified component (such as wireless transceiver 1122).

[0088] Wireless transceiver 1122 may include circuitry, logic, and other hardware for transmitting or receiving wireless signals for at least one communication frequency band. In operation, wireless transceiver 1122 may implement at least one radio frequency transceiver unit to process data and / or signals associated with communication data from electronic device 1102 via antenna 1130. Generally, wireless transceiver 1122 may include filters, switches, amplifiers, etc., for routing and processing signals transmitted or received via antenna 1130. Generally, wireless transceiver 1122 includes multiple transceiver units (e.g., for different wireless protocols such as WLAN and WWAN, or for supporting different frequency bands or combinations of frequency bands).

[0089] In one example, the filters, switches, amplifiers, mixers, etc., of the wireless transceiver 1122 may include at least one single-ended amplifier, a switching circuit, at least one transformer, at least one differential amplifier, and at least one mixer. In some embodiments, the single-ended amplifier, which amplifies the signal strength, is coupled to antenna 1130. Therefore, in addition to increasing signal strength, the single-ended amplifier can also couple wireless signals to or from antenna 1130. In some embodiments, the switching circuit can switchably couple each transformer in a set of transformers to the single-ended amplifier. This set of transformers provides physical or electrical isolation between the single-ended amplifier and other circuitry of the wireless transceiver 1122. The set of transformers also regulates the signal propagating through it. The outputs of the transformers can be coupled to one or more mixers.

[0090] Some examples may use a differential amplifier at the output of the transformer before the signal is input to the mixer. In such examples, the differential amplifier (similar to a single-ended amplifier) ​​amplifies the strength of the propagating signal. The wireless transceiver may also use a synthesized signal and a mixer to perform frequency conversion. The mixer may include an upconverter and / or a downconverter that performs frequency conversion in a single conversion step or through multiple conversion steps. The wireless transceiver 1122 may also include logic (not shown) that performs in-phase / quadrature (I / Q) operations using a synthesized signal, such as synthesis, encoding, modulation, demodulation, and decoding.

[0091] In some cases, components of the wireless transceiver 1122 or its transceiver unit are implemented as separate receiver and transmitter entities. Additionally or alternatively, the wireless transceiver 1122 may be implemented using multiple or different parts to achieve corresponding receive and transmit operations (e.g., using separate transmit and receive chains). The above describes an example specific implementation of the transceiver unit. Furthermore, different wireless protocols such as WWAN and WLAN may be implemented on separate chips or as separate systems-on-a-chip (SoCs). Thus, blocks such as modem 1120 and transceiver 1122 can represent more than one modem 1120 or transceiver implemented together on separate chips or separate SoCs.

[0092] The apparatus for implementing the circuit described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RF IC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR) or a corresponding mmW element, (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handheld device or mobile unit, (vii) and so on.

[0093] Figure 12 This is an illustration of an exemplary electronic device 1202, which includes a transceiver 1206 that may include and / or implement multiple transmit chains with shared elements as described herein. As shown, in addition to an integrated circuit 1210, the electronic device 1202 also includes an antenna 1204, a transceiver 1206, and a user input / output (I / O) interface 1208. Illustrated examples of the integrated circuit 1210 or its core include a microprocessor 1212, a graphics processing unit (GPU) 1214, a memory array 1216, and a modem 1218. Each component is operatively coupled to another component, such as the GPU 1214, which is operatively coupled to the user I / O interface 1208.

[0094] Electronic device 1202 can be a mobile or battery-powered device or a stationary device designed to be powered by the power grid. Examples of electronic device 1202 include server computers, network switches or routers, data center blades, personal computers, desktop computers, laptop or notebook computers, tablet computers, smartphones, entertainment devices, or wearable electronic devices such as smartwatches, smart glasses, or clothing items. Electronic device 1202 can also be a device or part thereof with embedded electronics. Examples of electronic device 1202 with embedded electronics include passenger vehicles, industrial equipment, refrigerators or other household appliances, unmanned aerial vehicles or other unmanned aerial vehicles (UAVs), or power tools.

[0095] For a wirelessly capable electronic device, electronic device 1202 includes an antenna 1204 coupled to transceiver 1206 to enable the reception or transmission of one or more wireless signals. Integrated circuit 1210 may be coupled to transceiver 1206 to enable integrated circuit 1210 to access the received wireless signals or provide wireless signals for transmission via antenna 1204. The illustrated electronic device 1202 also includes at least one user I / O interface 1208. Examples of user I / O interfaces 1208 include a keyboard, mouse, microphone, touchscreen, camera, accelerometer, haptic mechanism, speaker, display screen, or projector.

[0096] Integrated circuit 1210 may include one or more instances of, for example, microprocessor 1212, GPU 1214, memory array 1216, modem 1218, etc. Microprocessor 1212 may be used as a central processing unit (CPU) or other general-purpose processor. Some microprocessors include different components, such as multiple processing cores, which can be individually powered on or off. GPU 1214 may be particularly well-suited for processing visually relevant data for display, such as video data images. GPU 1214 may be completely or partially powered off if the visually relevant data is not rendered or otherwise processed. Memory array 1216 stores data for microprocessor 1212 or GPU 1214. Exemplary types of memory used for memory array 1216 include random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM); flash memory; etc. Memory array 1216 may be powered off entirely or piecewise if a program does not access the data stored in the memory. Modem 1218 demodulates signals to extract encoded information or modulates signals to encode information into the signals. If there is no information to decode from inbound communications or to encode for outbound communications, modem 1218 can be left idle to reduce power consumption. Integrated circuit 1210 may include additional or alternative components in addition to those shown, such as I / O interfaces, sensors (such as accelerometers), another part of a transceiver or receiver chain, custom or hard-coded processors (such as application-specific integrated circuits (ASICs)), and so on.

[0097] Integrated circuit 1210 may also include a system-on-a-chip (SoC). A SoC can integrate a sufficient number of components of different types to enable the SoC to provide computing functionality, such as in a laptop computer, mobile phone, or other electronic device, using at least one chip. Components of a SoC or integrated circuit 1210 are often referred to as cores or circuit blocks. Examples of cores or circuit blocks include... Figure 12 In addition to those illustrated herein, it also includes voltage regulators, main memory or cache memory blocks, memory controllers, general-purpose processors, encryption processors, video or image processors, vector processors, radio components, interface or communication subsystems, wireless controllers, or display controllers. Any of these cores or circuit blocks (such as a central processing unit or multimedia processor) may also include multiple internal cores or circuit blocks.

[0098] Figure 13A An example of a transceiver 1320 having a transmitter 1330 and a receiver 1350 is shown. According to the aspects described herein, the transmitter 1330 may include multiple transmission chains (e.g., in addition to the illustrated transmission chains), wherein each transmission chain includes elements for generating the different characteristics described above. The receiver 1350 may include, as... Figure 8BThe illustrated processing circuitry is used to identify individual return signals from different transmit chains according to the aspects described herein. According to the aspects described herein, receiver 1350 may include any Rx chain and may be integrated with various Tx chain systems in transmitter 1330. In various specific implementations, Rx chains and Tx chains may be merged or integrated with AI / ML network 820.

[0099] Generally, the regulation of the signals in transmitter 1330 and receiver 1350 can be performed by one or more stages such as amplifiers, filters, up-converters, and down-converters. These circuit blocks can be connected with... Figure 13A The configurations shown are arranged differently. Furthermore, Figure 13A Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 1330 and receiver 1350. Unless otherwise indicated, Figure 13A Any signal in any of the other diagrams in the accompanying drawings may be a single-ended signal or a differential signal. Figure 13A Some circuit blocks in the code can also be omitted.

[0100] exist Figure 13A In the example shown, wireless device 1300 typically includes a transceiver 1320 and a data processor 1310. Data processor 1310 may include a processor 1396 operatively coupled to memory 1398. Memory 1398 may be configured to store data and program code and may typically include analog and / or digital processing components. Transceiver 1320 includes a transmitter 1330 and a receiver 1350 supporting bidirectional communication. Generally, wireless device 1300 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 1320 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0101] The transmitter or receiver can be implemented using a superheterodyne architecture or a direct frequency conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband; for example, for a receiver, this might involve a stage from RF to intermediate frequency (IF) and then another stage from IF to baseband. This configuration can be used to generate signals relative to... Figure 3 , Figure 5 , Figure 6 , Figure 7 The example described is the IF signal. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 13A The example shown illustrates a single frequency converter (1340, 1360) for both transmit and receive functions, but a series of mixers could be used.

[0102] In the transmission path, data processor 1310 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 1330. In an exemplary embodiment, data processor 1310 includes digital-to-analog converters (DACs) 1314a and 1314b for converting digital signals generated by data processor 1310 into I analog output signals and Q analog output signals (e.g., I output current and Q output current) for further processing. In other embodiments, DACs 1314a and 1314b are included in transceiver 1320, and data processor 1310 provides data (e.g., for I and Q) digitally to transceiver 1320.

[0103] Within transmitter 1330, baseband (e.g., low-pass) filters 1332a and 1332b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies caused by the preceding digital-to-analog conversion. Amplifiers (Amps) 1334a and 1334b amplify the signals from baseband filters 1332a and 1332b, respectively, and provide the I baseband and Q baseband signals. Upconverter 1340, with upconverters 1341a and 1341b, utilizes the I TX LO and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1390 to upconvert the I baseband and Q baseband signals, and provides the upconverted signals. Filter 1342 filters the upconverted signals to remove unwanted images caused by frequency upconversion and noise in the receive band. Distributed amplifier 1344 amplifies the signal from filter 1342 to obtain the desired output power level and provides the transmit RF signal. The RF signal is routed via a duplexer or switch 1346 and transmitted via antenna 1348. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that components of the transceiver can be configured to utilize polarity modulation.

[0104] In the receiving path, antenna 1348 receives the communication signal and provides the received RF signal, which is routed through a duplexer or switch 1346 and provided to a low-noise amplifier (LNA) 1352. Switch 1346 is designed to operate at a specific RX and TX duplexer frequency interval, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1352 and filtered by filter 1354 to obtain the desired RF input signal. Downconverters 1361a and 1361b in downconverter 1360 mix the output of filter 1354 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 1380 to generate I baseband and Q baseband signals. The I-baseband signal and Q-baseband signal are amplified by amplifiers 1362a and 1362b and further filtered by baseband (e.g., low-pass) filters 1364a and 1364b to obtain the I-analog input signal and Q-analog input signal, which are provided to the data processor 1310. In the illustrated exemplary embodiment, the data processor 1310 includes analog-to-digital converters (ADCs) 1316a and 1316b for converting the analog input signals into digital signals to be further processed by the data processor 1310. In some embodiments, ADCs 1316a and 1316b are included in transceiver 1320 and provide data digitally to the data processor 1310.

[0105] exist Figure 13A In this configuration, TX LO signal generator 1390 generates I TX LO and Q TX LO signals for up-conversion, while RX LO signal generator 1380 generates I RX LO and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 1392 receives timing information from data processor 1310 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 1390. Similarly, PLL 1382 receives timing information from data processor 1310 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 1380. PLL 1392 may be selectively coupled to the input of modulation circuitry (e.g., 408) and distributed amplifier 1344. In other examples, a PLL independent of PLL 1392 is included in transmitter 1330 and, as relative to... Figure 4 The configuration is as described in the example.

[0106] Figure 13AThe transceiver 1320 is functionally illustrated in the document, and the illustrated configuration may or may not represent the physical device configuration in certain specific implementations. For example, as described above, the transceiver 1320 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 1320 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, the distributed amplifier 1344, filter 1342, and switch 1346 may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver 1320 may be implemented in a single transceiver chip.

[0107] The distributed amplifier 1344 may include one or more stages, such as driver stages, power amplifier stages, or other components that can be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the distributed amplifier 1344 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0108] In some aspects of using a superheterodyne architecture, the distributed amplifier 1344 and LNA 1352 (and in some examples, filters 1342 and / or 1354) can be implemented separately from other components in the transmitter 1330 and receiver 1350. While wireless device 1300 describes one example of a device, it will be apparent that the aspects described herein can be implemented in other architectures (e.g., superheterodyne architectures), and the described power envelope tracking system is not limited to such... Figure 13A The example architecture of the power amplifier is shown in the example architecture.

[0109] Figure 13B An RF chain 1480, which can be implemented in several ways, is illustrated. For example, the RF chain 1480 may be located between a distributed amplifier 1344, an LNA 1352, and a switch 1346. The RF chain 1480 is part of an RF transceiver that generates the transmitted signal. Figure 13BAs described, the Rf chain 1480 may include LO circuitry 1484, Tx antenna 1348A, and Rx antenna 1348B. In some aspects, the intermediate frequency (IF) signal 1485 may be shared as a common signal (e.g., shared with other circuitry in the transceiver chip), and different chains (e.g., besides RF chain 1480) may be distributed across specific RF transceivers (e.g., distributed across different chips or ICs). In some aspects, the PLL and / or LO circuitry 1484 may be used in each specific RF transceiver. In some aspects with common circuitry spanning multiple integrated circuit chips, the PLL and / or LO circuitry 1484 may be shared within the IF transceiver, or, similar to a clock signal, routed from the transceiver chip including RF chain 1480 to other transceivers (e.g., other chips or ICs) (e.g., via routing from one RF transceiver to another).

[0110] Examples not considered as limitations include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, smart glasses, augmented reality (AR) glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components such as in-vehicle main units, avionics systems, drones, and multi-rotor aircraft.

[0111] Claims using language such as "at least one processor, the at least one processor being configured to," "at least one processor being configured to," "one or more processors, the one or more processors being configured to," or "one or more processors being configured to," indicate that one or more processors (in any combination) are capable of performing associated operations. For example, a claim using language stating "at least one processor, the at least one processor being configured to: X, Y, and Z" means that a single processor can be used to perform operations X, Y, and Z; or that multiple processors are each assigned a specific subset of tasks of operations X, Y, and Z, such that the multiple processors together perform X, Y, and Z; or that a group of multiple processors work together to perform operations X, Y, and Z. In another example, a claim using language stating "at least one processor, the at least one processor being configured to: X, Y, and Z" may mean that any single processor can perform only at least one subset of operations X, Y, and Z.

[0112] When referring to one or more elements that perform functions (e.g., steps of a method), one element may perform all functions, or more than one element may jointly perform these functions. When more than one element jointly performs these functions, each function does not need to be performed by every single element (e.g., different functions may be performed by different elements), and / or each function does not need to be performed by only one element as a whole (e.g., different elements may perform different sub-functions of a function). Similarly, when referring to one or more elements configured to cause another element (e.g., a device) to perform functions, one element may be configured to cause another element to perform all functions, or more than one element may be jointly configured to cause another element to perform these functions.

[0113] When referring to an entity that performs or is configured to perform functions (e.g., steps of a method) (e.g., any entity or device described herein), the entity may be configured to cause one or more elements (individually or collectively) to perform those functions. One or more components of the entity may include at least one memory, at least one processor, at least one communication interface, another component configured to perform one or more of those functions, and / or any combination thereof. When referring to an entity that performs functions, the entity may be configured to cause one component to perform all functions, or to cause more than one component to perform those functions collectively. When the entity is configured to cause more than one component to perform those functions collectively, each function does not need to be performed by every single component (e.g., different functions may be performed by different components), and / or each function does not need to be performed by only one component as a whole (e.g., different components may perform different sub-functions of a function).

[0114] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention, as defined in the appended claims.

[0115] The exemplary aspects of this disclosure include, but are not limited to:

[0116] Aspect 1. An apparatus comprising: a phase-locked loop (PLL) circuit having a shared PLL output; a radar signal generation circuit; a first transmission chain coupled to the shared PLL output and the radar signal generation circuit; and a second transmission chain coupled to the shared PLL output and the radar signal generation circuit.

[0117] Aspect 2. The apparatus according to aspect 1, wherein the shared PLL output is coupled to the mixer of the first transmit chain via a local oscillator (LO) circuit.

[0118] Aspect 3. The apparatus according to aspect 2, wherein the shared PLL output is coupled to the mixer of the second transmit chain via the LO circuit and the first divider circuit.

[0119] Aspect 4. The apparatus according to aspect 3, further comprising: a third transmission chain coupled to the shared PLL output via the LO circuit and a second frequency divider circuit independent of the first frequency divider circuit.

[0120] Aspect 5. The apparatus according to aspect 3, wherein the first frequency divider circuit includes a programmable frequency divider.

[0121] Aspect 6. The apparatus according to any one of Aspects 1 to 5, wherein the first transmission chain and the second transmission chain include the shared PLL output; wherein the PLL circuit is configured to generate a shared transmission signal using a frequency modulated continuous wave (FMCW) modulated input; wherein the transmission circuit of the second transmission chain is coupled to the shared PLL output via a frequency divider circuit; and wherein the transmission circuit of the first transmission chain is coupled to the shared PLL output.

[0122] Aspect 7. The apparatus according to aspect 6, further comprising: a third transmission chain coupled to the shared PLL output via a second frequency divider circuit independent of the first frequency divider circuit.

[0123] Aspect 8. The apparatus according to aspect 6, wherein the transmitting circuit of the first transmitting chain is configured to output a first radar transmission at a shared frequency of the shared transmitting signal; and wherein the transmitting circuit of the second transmitting chain is configured to output a second radar transmission at a second frequency shifted from the shared frequency by the frequency divider circuit.

[0124] Aspect 9. The apparatus according to any one of Aspects 1 to 8, wherein the first transmission chain and the second transmission chain include a shared mixer; wherein the output of the shared PLL is coupled to the LO input of the shared mixer; and wherein the transmission circuit of the second transmission chain is coupled to the output of the shared mixer via a frequency divider circuit.

[0125] Aspect 10. The apparatus according to aspect 9, wherein the transmitting circuit of the first transmitting chain is independent of the transmitting circuit of the second transmitting chain and is coupled to the output of the shared mixer without intermediate frequency divider circuitry.

[0126] Aspect 11. The apparatus according to aspect 9, wherein the radar signal generation circuit includes a shared frequency modulated continuous wave-intermediate frequency (FMCW-IF) signal generation circuit coupled to the signal input section of the shared mixer.

[0127] Aspect 12. The apparatus according to any one of Aspects 1 to 11, wherein the first transmission chain and the second transmission chain share a frequency modulated continuous wave-intermediate frequency (FMCW-IF) circuit and an IQ generation circuit coupled to the FMCW-IF circuit; wherein a first output of the IQ generation circuit is coupled to the transmission circuit of the first transmission chain via a first mixer of the first transmission chain; wherein a second or branched output of the IQ generation circuit is coupled to the transmission circuit of the second transmission chain via a second mixer of the second transmission chain.

[0128] Aspect 13. The apparatus according to any one of Aspects 1 to 12, wherein the apparatus is configured to concurrently transmit a plurality of radar signals at different corresponding frequencies via the first transmission chain and the second transmission chain.

[0129] Aspect 14. The apparatus according to any one of Aspects 1 to 13, wherein the first transmission chain and the second transmission chain share a frequency-modulated continuous wave-intermediate frequency (FMCW-IF) circuit.

[0130] Aspect 15. The apparatus according to aspect 14, wherein a first output of the FMCW-IF circuit is coupled to a transmitting circuit of the first transmitting chain via a first mixer of the first transmitting chain; wherein a second or split output of the FMCW-IF circuit is coupled to a transmitting circuit of the second transmitting chain via a second mixer of the second transmitting chain.

[0131] Aspect 16. The apparatus according to aspect 15, wherein the second OR branch output of the FMCW-IF circuit is coupled to the second mixer via a frequency adjustment circuit.

[0132] Aspect 17. The apparatus according to aspect 16, wherein the frequency adjustment circuit includes an interference reduction circuit.

[0133] Aspect 18. The apparatus according to aspect 16, wherein the frequency adjustment circuit includes a frequency offset circuit.

[0134] Aspect 19. The apparatus according to any one of Aspects 1 to 18, wherein the first transmission chain generates a first signal, and wherein the second transmission chain generates a second signal orthogonal to the first signal.

[0135] Aspect 20. The apparatus according to aspect 19, wherein the first signal is a first pseudo-random (PN) forming signal, and wherein the second signal is a second PN forming signal orthogonal to the first PN forming signal.

[0136] Aspect 21. The apparatus according to any one of Aspects 1 to 20, wherein the first transmission chain and the second transmission chain are configured for transmission in a first transmission direction; wherein the chirp pattern of the transmission signal for the first transmission chain is orthogonal to the chirp pattern of the transmission signal for the second transmission chain.

[0137] Aspect 22. The apparatus according to aspect 21, wherein a third transmission chain and a fourth transmission chain are configured for transmission in a second transmission direction orthogonal to the first transmission direction; and wherein the chirp pattern of the transmission signal for the third transmission chain is orthogonal to the chirp pattern of the transmission signal for the fourth transmission chain.

[0138] Aspect 23. The apparatus according to any one of Aspects 1 to 22, the apparatus further comprising a shared receiving path; and processing circuitry configured to perform source separation on the received signals to identify separate return chirp signals from the first transmitting chain and the second transmitting chain.

[0139] Aspect 24. The apparatus according to any one of aspects 1 to 23, wherein the processing circuitry is configured to identify the individual return chirp signals using a trained source separation machine learning algorithm.

[0140] Aspect 25. The apparatus according to aspect 24, wherein the trained source separation machine learning algorithm uses one or more of signal level, signal index, signal slope direction, and signal frequency domain to identify the individual return chirp signal.

[0141] Aspect 26. The apparatus according to any one of Aspects 1 to 25, wherein the first transmission chain is disposed in a first radio frequency front-end (RFFE) module; and wherein the second transmission chain is disposed in a second RFFE module.

[0142] Aspect 27. The apparatus according to aspect 26, wherein the first RFFE module includes a first antenna coupled to the first transmit chain, wherein the first antenna covers a first spatial location; wherein the second RFFE module includes a second antenna coupled to the second transmit chain, wherein the second antenna covers a second spatial location different from the first spatial location.

[0143] Aspect 28. A method comprising: generating a first radar signal using a radar signal generation circuit and a first transmission chain coupled to a shared PLL circuit; and generating a second radar signal using the radar signal generation circuit and a second transmission chain coupled to the shared PLL circuit.

[0144] Aspect 29. The method according to aspect 28, the method further comprising: receiving a first return radar signal and a second return radar signal as a joint received signal on a receiving path; performing source separation on the joint received signal using a trained source separation machine learning algorithm to identify the individual return signals and separate them into a first return radar signal associated with the first radar signal and a second return radar signal associated with the second radar signal.

[0145] Aspect 30. The method according to any one of Aspects 28 to 29, wherein the trained source separation machine learning algorithm uses one or more of signal level, signal index, signal slope direction, and signal frequency domain to identify the individual return signal.

[0146] Aspect 31: An apparatus comprising components for performing operations according to any one of aspects 1 to 29 above.

[0147] Aspect 32: A non-transitory computer-readable storage medium comprising instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to perform any one of aspects 1 to 29 above.

[0148] Aspect 33: A method of operating any apparatus according to any of the foregoing aspects to perform wireless communication using a shared PLL.

Claims

1. An apparatus, the apparatus comprising: A phase-locked loop (PLL) circuit, wherein the PLL circuit has a shared PLL output section; Radar signal generation circuit; A first transmission chain, which is coupled to the shared PLL output and the radar signal generation circuit; and The second transmission chain is coupled to the shared PLL output and the radar signal generation circuit.

2. The apparatus of claim 1, wherein the shared PLL output is coupled to the mixer of the first transmit chain via a local oscillator (LO) circuit.

3. The apparatus of claim 2, wherein the shared PLL output is coupled to the mixer of the second transmit chain via the LO circuit and the first divider circuit.

4. The apparatus according to claim 3, further comprising: The third transmission chain is coupled to the shared PLL output via the LO circuit and a second frequency divider circuit independent of the first frequency divider circuit.

5. The apparatus according to claim 1, wherein the first transmission chain and the second transmission chain include the shared PLL output unit; The PLL circuit is configured to use frequency modulated continuous wave (FMCW) modulation input to generate a shared transmit signal; The transmitting circuit of the second transmitting chain is coupled to the shared PLL output section via a frequency divider circuit; and The transmitting circuit of the first transmitting chain is coupled to the shared PLL output section.

6. The apparatus according to claim 3, further comprising: A third transmission chain is coupled to the shared PLL output via a second frequency divider circuit independent of the first frequency divider circuit.

7. The apparatus of claim 5, wherein the transmitting circuit of the first transmitting chain is configured to output a first radar transmission at a shared frequency of the shared transmitting signal; and The transmitting circuit of the second transmitting chain is configured to output a second radar transmission at a second frequency shifted from the shared frequency by the frequency divider circuit.

8. The apparatus of claim 1, wherein the first transmission chain and the second transmission chain comprise a shared mixer; The shared PLL output is coupled to the LO input of the shared mixer; and The transmitting circuit of the second transmitting chain is coupled to the output of the shared mixer via a frequency divider circuit.

9. The apparatus of claim 8, wherein the transmitting circuit of the first transmitting chain is independent of the transmitting circuit of the second transmitting chain and is coupled to the output of the shared mixer without intermediate frequency divider circuitry.

10. The apparatus of claim 8, wherein the radar signal generation circuit includes a shared frequency modulated continuous wave-intermediate frequency (FMCW-IF) signal generation circuit coupled to the signal input section of the shared mixer.

11. The apparatus of claim 3, wherein the first frequency divider circuit comprises a programmable frequency divider.

12. The apparatus of claim 1, wherein the first transmission chain and the second transmission chain share a frequency modulated continuous wave-intermediate frequency (FMCW-IF) circuit and an IQ generation circuit coupled to the FMCW-IF circuit; The first output of the IQ generation circuit is coupled to the transmission circuit of the first transmission chain via the first mixer of the first transmission chain. The second output of the IQ generation circuit is coupled to the transmission circuit of the second transmission chain via the second mixer of the second transmission chain.

13. The apparatus of claim 1, wherein the apparatus is configured to concurrently transmit a plurality of radar signals at different corresponding frequencies via the first transmission chain and the second transmission chain.

14. The apparatus of claim 1, wherein the first transmission chain and the second transmission chain share a frequency-modulated continuous wave-intermediate frequency (FMCW-IF) circuit.

15. The apparatus of claim 14, wherein the first output of the FMCW-IF circuit is coupled to the transmission circuit of the first transmission chain via a first mixer of the first transmission chain; The second or branch output of the FMCW-IF circuit is coupled to the transmission circuit of the second transmission chain via the second mixer of the second transmission chain.

16. The apparatus of claim 15, wherein the second OR branch output of the FMCW-IF circuit is coupled to the second mixer via a frequency adjustment circuit.

17. The apparatus of claim 16, wherein the frequency adjustment circuit includes an interference reduction circuit.

18. The apparatus of claim 16, wherein the frequency adjustment circuit includes a frequency offset circuit.

19. The apparatus of claim 1, wherein the first transmission chain generates a first signal, and wherein the second transmission chain generates a second signal orthogonal to the first signal.

20. The apparatus of claim 19, wherein the first signal is a first pseudo-random (PN) forming signal, and wherein the second signal is a second PN forming signal orthogonal to the first PN forming signal.

21. The apparatus according to claim 1, The first transmission chain and the second transmission chain are configured for transmission in the first transmission direction; The chirp pattern of the transmission signal used in the first transmission chain is orthogonal to the chirp pattern of the transmission signal used in the second transmission chain.

22. The apparatus of claim 21, wherein the third transmission chain and the fourth transmission chain are configured for transmission in a second transmission direction orthogonal to the first transmission direction; and The chirp pattern of the transmission signal used in the third transmission chain is orthogonal to the chirp pattern of the transmission signal used in the fourth transmission chain.

23. The apparatus of claim 1, further comprising a shared receiving path; and The processing circuit is configured to perform source separation on the received signal to identify separate return chirp signals from the first transmission chain and the second transmission chain.

24. The apparatus of claim 23, wherein the processing circuitry is configured to use a trained source separation machine learning algorithm to identify the individual return chirp signals.

25. The apparatus of claim 24, wherein the trained source separation machine learning algorithm uses one or more of signal level, signal index, signal slope direction, and signal frequency domain to identify the individual return chirp signal.

26. The apparatus of claim 1, wherein the first transmission chain is disposed in the first radio frequency front-end (RFFE) module; and The second transmission chain is set in the second RFFE module.

27. The apparatus of claim 26, wherein the first RFFE module includes a first antenna coupled to the first transmit chain, wherein the first antenna covers a first spatial location; The second RFFE module includes a second antenna coupled to the second transmit chain, wherein the second antenna covers a second spatial location different from the first spatial location.

28. A method, the method comprising: The first radar signal is generated using a radar signal generation circuit and a first transmission chain coupled to a shared phase-locked loop (PLL) circuit; as well as The second radar signal is generated using the radar signal generation circuit and a second transmission chain coupled to the shared PLL circuit.

29. The method according to claim 28, further comprising: The first and second returned radar signals are received along the receiving path as a joint received signal; The joint received signal is source-separated using a trained source separation machine learning algorithm to identify the individual return signals and separate them into a first return radar signal associated with the first radar signal and a second return radar signal associated with the second radar signal.

30. The method of claim 29, wherein the trained source separation machine learning algorithm uses one or more of signal level, signal index, signal slope direction, and signal frequency domain to identify the individual return signal.

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