Thermal mitigation of SOC using memory access latency

Abstract

Aspects relate to using memory access latency to mitigate thermal excess in a system-on-chip (SOC). An apparatus includes a processing core, a memory, and a thermal monitor configured to determine a thermal state of the processing core. A memory controller is coupled to the processing core, the thermal monitor, and the memory, and the memory controller is configured to provide access to the memory to the processing core, the memory controller further configured to delay access to the memory in response to the thermal state.

Description

Cross-reference to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 473,948, filed September 25, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] All aspects of this disclosure relate to thermal mitigation for integrated circuits (e.g., system-on-chip (SoC)), and specifically to thermal mitigation by affecting latency in memory access. Background Technology

[0003] The amount of heat generated by semiconductors (e.g., processors, sensors, or memory) is proportional to the switching activity and density of switches on the semiconductor. Switching activity refers to the frequency at which the states of switches (e.g., transistors and diodes) change. Switch density refers to the number of switches in an active state per unit area of ​​the semiconductor. Switching activity is related to the clock frequency applied to the switches and the duty cycle of the switches. High-performance semiconductors operate at higher clock frequencies with more transistors per die. This makes the die more prone to overheating. Compact and portable form factors make it more difficult to provide cooling for high-performance dies. In some cases, operating speed is constrained to ensure the die does not overheat.

[0004] Switching activity is affected by the number of switches simultaneously active and the switching frequency of the integrated circuit. Thermal mitigation typically involves placing portions of the integrated circuit into idle or sleep states and reducing the frequency of the input clock driving the switches. These thermal mitigation measures also degrade the performance of the integrated circuit.

[0005] A System-on-a-Chip (SoC) can include multiple components, including integrated circuits such as sensors, modems, processors, memory, and output circuitry. SoCs typically have protection against overheating and shutdown. For critical or high-reliability applications, SoC components operate at lower power and lower frequencies to prevent overheating and avoid shutdown. Lower power and frequency also increase the lifespan of the SoC's integrated circuits. Summary of the Invention

[0006] The following content presents an overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] An apparatus includes a processing core; a memory; a thermal monitor configured to determine the thermal state of the processing core; and a memory controller coupled to the processing core and the memory, and configured to provide the processing core with access to the memory, the memory controller also being configured to delay access to the memory in response to the thermal state.

[0008] In another example, one approach includes determining the thermal state of the processing core; and in response to the thermal state, delaying the processing core's access to memory coupled to the processing core via a memory controller.

[0009] In another example, a non-transitory computer-readable medium has instructions stored therein for causing a processor to perform the operations described above.

[0010] In another example, an apparatus includes components for determining the thermal state of a processing core; and components for delaying access by the processing core to memory coupled to the processing core via a memory controller in response to the thermal state.

[0011] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0012] Figure 1 A diagram illustrating thermal mitigation using a thermal monitor and a memory controller according to various aspects of this disclosure is provided.

[0013] Figure 2 Examples of memory operation command grouping structures and threshold tables according to various aspects of this disclosure are provided.

[0014] Figure 3 A flowchart illustrating the operation of a thermal monitor for thermal mitigation in a calculation system according to various aspects of this disclosure is provided.

[0015] Figure 4 A block diagram illustrating an example hardware implementation of a device for heat mitigation using a thermal monitor, according to various aspects of this disclosure, is shown.

[0016] Figure 5 A flowchart illustrating a method for thermal mitigation using a memory controller according to various aspects of this disclosure is provided. Detailed Implementation

[0017] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0018] As described herein, thermal mitigation can be applied to a processor by delaying memory access in response to the thermal state from a thermal monitor. One or more thermal sensors detect the temperature of one or more processing cores. A thermal monitor coupled to the thermal sensors determines the thermal state of the processing core, and the memory controller subsequently delays memory access in response to the thermal state. Forcing memory access delay reduces the effective switching frequency of the processing core, thereby reducing the heat generated by the processing core.

[0019] For example, when a processor uses memory (such as cache or other local volatile memory), various processor instructions can depend on read or write operations to that memory. When an instruction requires a value, or even an instruction from memory, execution continues until the value has been fetched from memory. For other instructions, a read from memory must be completed before proceeding to ensure the latest value is stored for use by other instructions. Therefore, slow memory forces the processor to wait for memory access. This waiting reduces the heat generated by the processor.

[0020] Figure 1 This is a diagram of a portion of a computing system 100 with a thermal monitor 126. The computing system is presented as having a specific SoC architecture, but any other computing system architecture can be used, such as that suitable for embedded systems, portable systems, IoT systems, desktop systems, server systems, or storage systems, etc. The SoC may have more components than shown. The SoC may be formed as one or more dies coupled together via a package substrate or any other suitable means. Although this description is presented in the context of an SoC, the techniques and processes described herein can be applied to systems with multiple discrete components that are individually packaged, powered, and housed.

[0021] Heat is generated by the switching activity in the system's processing cores 112, 114, and 116. While this description focuses primarily on processing cores 112, 114, and 116, similar structures and techniques will also address excessive heat in the memory devices, external interfaces, and other components of system 100. The heat generated in the processing cores is determined at least in part by the operating voltage and switching frequency of the switches (e.g., transistors) in the processing cores 112, 114, and 116. Resistive, capacitive, and inductive elements generate additional heat, but this heat also varies substantially with voltage and switching frequency.

[0022] Memory transaction latency is added to memory controller 106 by tunable delay element 128. This added memory transaction latency acts as a thermal mitigation mechanism that does not require any changes to voltage or switching frequency. As shown, memory 102 is coupled to memory interface 104, such as a physical memory interface, which is coupled to memory controller 106. Memory controller 106 is shown coupled to interconnect controller 108. Interconnect controller 108 is shown coupled to processing cores 112, 114, 116, and may also be coupled to other components (not shown). Interconnect controller 108 is configured to allow processing cores 112, 114, 116, and other components to access memory 102 via memory controller 106. Memory controller 106 drives read and write transactions, as well as diagnostic and maintenance transactions, to memory 102 via memory interface 104.

[0023] This description is presented in the context of Dynamic Random Access Memory (DRAM). In some respects, DRAM is easily controlled outside the processing core due to the nature of its protocols and memory interface 104. Many computing systems place large blocks of instructions and intermediate values ​​in DRAM, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Therefore, latency in reading from or writing to DRAM can directly lead to latency in the processing core that issues read or write commands. The techniques and structures described herein can also be applied to other types of memory as alternatives to and / or complements to DRAM, whether for the same, similar, or different purposes. Such memories include Static Random Access Memory (SRAM), Solid State Drive Memory (SSD), cache memory, mass storage, volatile memory, non-volatile memory, etc.

[0024] Interconnect controller 108 may also be coupled to other devices 110, including various other types of memory mentioned above. Second bus interface 130 may also be coupled to processing cores 112, 114, 116 to provide an interface to other devices 132, such as communication interfaces, sensors, actuators, user interfaces, other memories, etc. In some examples, multiple bus interfaces may exist. In some examples, the interconnect controller may be a single interface. The illustrated components represent only a portion of the possible components of computing system 100 and may represent only a subsystem or the entire SoC. Memory 102 may reside on the same die as memory interface 104 and memory controller 106 (e.g., as a memory subsystem). Memory 102 may reside on the same die or a different die as interconnect controller 108 and processing cores 112, 114, 116.

[0025] In this example, processing cores 112, 114, and 116 of computing system 100 concurrently share memory 102. More or fewer processing cores may exist, and other components may also concurrently share memory 102. The round-trip latency of memory 102, via interconnect controller 108, significantly affects the turnaround time of many tasks executed in processing cores 112, 114, and 116. This dependence on memory response time can be used to regulate the switching activity of one or more of the processing cores 112, 114, and 116. The switching activity is regulated in response to the temperature of one or more of the processing cores 112, 114, and 116.

[0026] As shown in the figure, a first processing core 112 has a first thermal sensor 118. A second processing core 114 has a second thermal sensor 120, and a third processing core 116 has a third thermal sensor 122. A thermal sensor refers to one or more thermal sensors located in one or more locations within a respective processing core, thermally coupled to one or more regions of the respective processing core to generate a thermal signal, such as a variable voltage, indicating the temperature of the respective processing core. Thermal signals from multiple sensors can be averaged or aggregated for each processing core in any of a variety of different ways. The thermal signals can be analog or digital to suit different specific implementations. In some examples, thermal sensors 118, 120, and 122 may be included in processing cores 112, 114, and 116 for other purposes, and such existing current thermal sensors can also be used in the structures and techniques described herein.

[0027] Thermal sensors 118, 120, and 122 are coupled to sensor interface 124 to receive bare thermal signals or aggregated thermal signals. Sensor interface 124 is coupled to thermal monitor 126, which analyzes the thermal signals and determines an appropriate delay. Thermal monitor 126 is coupled to tunable delay element 128, which is coupled to memory controller 106 to command a delay in response to the thermal monitor. In some examples, thermal monitor 126 and tunable delay element 128 may be incorporated into interconnect controller 108 to determine whether to delay memory controller 106's access to memory 102.

[0028] In some examples, thermal monitor 126 aggregates the highest temperatures from thermal sensors 118, 120, and 122 and compares the aggregated highest temperatures to stored thresholds to determine the highest thermal state of processing cores 112, 114, and 116. In some examples, thermal monitor 126 averages the temperatures and compares the average to stored thresholds to determine the thermal state of processing cores 112, 114, and 116. Other techniques may also be used to determine the thermal state. In some examples, the thermal state is determined independently for each processing core, and actions are taken independently for each processing core. In some examples, the thermal states of each processing core are combined to form the overall thermal state to be applied together to all processing cores in processing cores 112, 114, and 116.

[0029] Once the thermal state of cores 112, 114, and 116 is determined by thermal monitor 126, for example, through a temperature threshold violation, a delay command can be generated and transmitted to memory controller 106 via tunable delay element (TDE) 128. The delay command can be a binary signal to optionally enable or disable delayed access to memory 102. In some examples, the delay command has multiple levels to indicate the severity of the threshold violation to tunable delay element 128. The TDE is coupled to the memory subsystem to control the response latency of read and write transactions by adding latency to read and write transactions. For multi-level commands, TDE 128 can add more or less latency in response to which of the multiple levels in the command.

[0030] The added latency can take the form of adding a latency state or wait state to a transaction between memory controller 106 and memory 102. In some examples, latency can be added by adding instructions other than read and write transactions to the memory controller. In some examples, latency can be added by adding instructions with no operation (e.g., no operands, NOP, or other inactive instructions) to the memory bus between memory interface 104 and memory 102.

[0031] The delay prevents the corresponding processing core from acting on values ​​from or to memory during the duration of the delay. This allows for a significant reduction in the switching frequency of the portion of the processing core that is driving memory access. By reducing the switching frequency, the temperature of the affected portion of the processing core is reduced. The magnitude or duration of the delay can be controlled by thermal monitor 126, thereby regulating the temperature of system 100 by reducing switching activity. Since the more active portions of the processing core are more likely to access memory more frequently, delaying memory access tends to have the greatest impact on the most active portions of the processing core. This makes the temperature reduction maximum where it is most needed. Temperature regulation can be performed by the thermal monitor without affecting the core's clock frequency or the power supply voltage of the computing system.

[0032] As described in this article, memory read and write latency can be modified in response to temperature, even if the clock frequency and voltage remain unchanged. Thermal monitors use system memory transaction latency to provide thermal mitigation.

[0033] exist Figure 1 The example illustrates a memory subsystem comprising a memory 102 with registers for storing data, a memory interface 104 physically connected to the addressed registers, and a memory controller 106 driving all transactions via the memory interface. The techniques and structures described herein can be adapted to other memory configurations with different components connected to an interconnect controller 108. In some configurations, the memory controller 106 and memory interface 104 may be absent or incorporated into the memory 102 or implemented by the interconnect controller 108. The TDE 128 can be adapted to other memory configurations and can be incorporated into the thermal monitor 126 or adapted to operate on the interconnect controller 108 instead of the memory controller. The TDE 128 and thermal monitor 126 can be implemented as a discrete state machine or as part of another system (e.g., the interconnect controller 108).

[0034] Figure 2 Examples of memory transaction commands, NOP commands, and latency threshold tables are provided. In some specific implementations, memory transactions from the memory controller have a grouping configuration, which has, for example... Figure 2 The structure is shown in Table 202. This table has a header row 212 and a data row 214 for illustrative purposes. Memory transaction packets do not require a header row. The values ​​in data row 214 are shown as an example of the structure, not actual values. The payload is the data to be written to memory at the target address and has the length provided in the length field. This example memory transaction packet has a status as a request and an operation code for read or write.

[0035] Table 204 is an example of a delayed command. Thermal states are examples of different thermal states indicated by the thermal monitor to the memory controller. A delayed command may have a structure similar to that in Table 202, with the same header line 216 for illustrative purposes, and with modifications to some or all of the data lines 218. The destination address is irrelevant, but the operation code is a no-operation (NOP), and the payload is blank or a dummy bit. The length may match the payload or a default value.

[0036] Table 206 is a table of thresholds that a thermal monitor can use to determine the thermal state of the processing core. Header row 222 indicates different temperature thresholds as example thresholds in the left column. While the threshold is indicated as temperature, this can be adapted to the output of the sensor interface and can be a voltage, or any analog or multi-bit value indicating temperature but not the actual temperature. When the temperature is below a first minimum threshold (e.g., 70°C), the thermal monitor does not function to delay memory access. This can be indicated by a no-delay command (e.g., OFF or 00), or by no action and no command, or in any other suitable manner.

[0037] When the temperature exceeds a first threshold (e.g., 70°C), the thermal monitor can activate first-level thermal mitigation by delaying access in response to a delayed command. This command is indicated as ON or 01, but can be any suitable command or operation. In some examples, the thermal monitor has two levels: ON and OFF. If the temperature continues to rise and exceeds another threshold, different thermal mitigation can be applied, or the system can be shut down to prevent damage. Figure 2 Table 206 shows that the Dynamic Clock and Voltage Scaling (DCVS) system can be activated when the temperature exceeds a fourth threshold (e.g., 105°C). The DCVS system can operate independently of the thermal monitor and without relation to or connection to the TDE. In Table 206, this is indicated by the same command (e.g., 11) used for exceeding the third threshold (e.g., 90°C) and the fourth threshold (e.g., 105°C).

[0038] For a two-bit command structure from the thermal monitor to the TDE, two additional thresholds can be accommodated. Exceeding the second threshold, indicated as 75°C, results in a second-level delay command, such as 10. Exceeding the third threshold, indicated as 90°C, results in a third-level delay command, such as 11. Each delay command causes a wait state to be added to the memory command, and each additional level results in an additional wait state. The first level causes the addition of one wait state. This can be done by adding a NOP command as shown in Table 204 or by any other suitable method. The second level causes two wait states to be added to each memory transaction, and the third level causes four wait states to be added. The number of wait states and the specific implementation of the delays (whether through wait states, dummy commands, or another type of delay) can be adapted to suit different computing systems and memory architectures. Although two-bit commands are shown, more bits and thresholds can exist. The command structure can be adapted to suitable protocols, for example, as a grouping with additional information or with hardware lines with pins or traces.

[0039] Thermal mitigation can be configured as an additional layer to reduce the need for DCVS or similar systems by selecting a threshold from a threshold table. Furthermore, thermal mitigation can be used when a DCVS system is not present and no part of its operation depends on a DCVS system. By implementing thermal mitigation before enabling DCVS, the need to enable DCVS is reduced. In one example, the DCVS system reduces the voltage applied to the processing core in response to a first thermal state. The memory controller delays memory access in response to a second thermal state. The second thermal state corresponds to a temperature lower than the first thermal state (e.g., 130°C) (e.g., 125°C).

[0040] As an example, some systems allow operation up to a specific temperature, such as 125°C, without any thermal mitigation. When the temperature exceeds, for example, 125°C, a software shutdown is triggered, and at, for example, 130°C, a hardware shutdown is initiated. Sudden shutdowns can have negative consequences and can be avoided by applying memory access delays as thermal mitigation. Advanced driver assistance systems (ADAS) with such software and hardware shutdowns and without DCVS have been proposed. For in-vehicle infotainment (IVI) systems that include DCVS, using DCVS and disabling certain operations triggers software mitigation at lower temperatures. Above, for example, 125°C, system functionality becomes very limited. Thermal mitigation by delaying memory access allows some of the shutdowns to be avoided.

[0041] Figure 3This is a flowchart 300 illustrating the process of operating a thermal monitor for thermal mitigation in a computing system. The process begins upon system startup. At 302, the system is initialized and operating normally, ensuring that memory controller access to memory is not delayed. At 304, the thermal monitor monitors the temperature of the processing cores. The temperature is received as a thermal signal from a sensor interface or otherwise. At 306, the thermal monitor aggregates the monitored temperatures to determine the thermal state of the processing cores. An aggregated thermal state may exist for all processing cores in a combined processing core configuration. In some examples, each processing core has one thermal state, in which case execution is performed for each core. Figure 3 The process. The thermal state can be the temperature shown in Table 206, or it can be another form. The thermal state indicates the aggregate temperature of all thermally coupled thermal sensors in the thermally coupled thermal sensor, and may not indicate the actual physical temperature of the processing core at any particular location.

[0042] At 308, the thermal state at 306 is compared to a first threshold. If the thermal state does not exceed the first threshold, the process returns to monitoring the temperature at 304. The thermal monitor selects either zero latency or no latency. At 316, no thermal mitigation is applied, memory access is not delayed, and any previously added latency is removed. If the thermal state exceeds the first threshold, at 310, the thermal state is compared to a second threshold. If it does not exceed the second threshold, at 312, a first-level latency command is generated based on the thermal state between the first and second thresholds. The thermal monitor selects a first latency amount. This is indicated as latency amount "1" in Table 206. In systems with only one threshold, the test at 310 is not performed, and a first-level latency command is generated at 312. In either case, the process returns to 304 to monitor the temperature. This results in the removal of access latency when the thermal state drops below the first threshold.

[0043] If the thermal state exceeds the second threshold at 310, a second-level delay command is generated at 314, and the process returns to monitoring the temperature at 304. The thermal monitor selects a second delay amount. This is indicated as delay amount "2" in Table 206. Table 206 shows a third-level threshold, which can be added to process flow chart 300 as another test in the same manner as the second test 314. Additional thresholds can also be added to suit a specific computing system.

[0044] Figure 4A block diagram illustrating an example of a hardware implementation of device 400, such as user equipment, portable devices, notebook computers, tablet computers, computers, servers, routers, memory arrays, or any other suitable device having one or more integrated circuits with processing cores for accessing memory. In this example, the device includes a processing system 420 having one or more processing cores 402, as described above. According to various aspects of this disclosure, the processing system 420 may be used to implement elements or any portion of elements or any combination of elements. Examples of processing cores 402 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuitry, and other suitable hardware configured to access shared memory via an interconnect controller. In various examples, device 400 may be configured to perform any one or more of the functions described herein.

[0045] In this example, a bus architecture (typically represented by bus 426) can be used to implement the processing system 420. Bus 426 may include any number of interconnect buses and bridges, depending on the specific application of the processing system 420 and the overall design constraints. Bus 426 communicatively couples together various circuits including a thermal sensor array 421 thermally coupled to the processing core 402, one or more system memories (typically represented by system memory 408), an interconnect controller 404, memory 432, and a computer-readable medium (typically represented by computer-readable medium 406) storing instructions thereon.

[0046] Bus 426 may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further. Bus interface 410 provides an interface between bus 426 and communication interface 412. Communication interface 412 provides components for communicating with various other devices over a wireless or wired transmission medium via, for example, wireless or wired connections. In some examples, a wireless device may include two or more interfaces, each configured to communicate over the same or different media. Communication interface 412 provides a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same device or other external devices) via an internal bus or external transmission medium such as Ethernet cable, USB cable, Wi-Fi, Bluetooth, NFC, and other connectors.

[0047] Bus interface 410 also provides an interface between bus 426 and user interface 430. Depending on the nature of the device, user interface 430 may include a local or remote interface (e.g., keypad, display, speaker, microphone, joystick). Of course, such a user interface is optional and may be omitted in some examples, such as Internet of Things (IoT) devices.

[0048] Processing core 402 is responsible for performing the functions of device 400. The configuration and use of processing core 402 depend on the purpose and function of the device. More or fewer cores may exist. In addition to a general-purpose core, one or more cores may be dedicated to specific functions, such as image processing, graphics rendering, audio recording, transcoding and rendering, communication processing including encoding and decoding, positioning and motion determination, digital signal processing, artificial intelligence, etc. One or more cores may also be configured for system management, security, and other functions. Processing core 402 uses memory 432 via interconnect controller 404 and memory controller 434 to support one or more of these functions to support the operation of device 400. Interconnect controller 404 is responsible for managing access to memory 432 via memory controller 434, which can be implemented via bus 426, including the execution of software stored on computer-readable medium 406. When executed by interconnect controller 404, the software causes interconnect controller 404 to perform the various functions described below for thermal mitigation. In this example, thermal monitoring circuitry 440 is incorporated into interconnect controller 404. In some examples, the thermal monitor is a discrete and separate unit. The computer-readable medium 406, the interconnect controller 404, and the memory 432 may also be used to store data manipulated by the processing system 420 during software execution.

[0049] Interconnect controller 404 may be part of one or more processing cores in processing core 402 and operates by means of a processor core that executes software stored in computer-readable medium 406. In some examples, interconnect controller 404 may execute software stored on computer-readable medium 406 independently of processing core 402 within processing system 420 (as shown) using its own processing resources. Software should be broadly interpreted as instructions, instruction set, code, code segment, program code, program, subroutine, software module, application, software application, software package, routine, subroutine, object, executable file, thread of execution, procedure, function, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or others. Software may reside on computer-readable medium 406. Interconnect controller 404 may be implemented in hardware, firmware, state machine, or other devices without requiring instructions in computer-readable medium 406.

[0050] Computer-readable medium 406 may be a non-transitory computer-readable medium. As examples, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes), optical disks (e.g., compact discs (CDs) or digital multi-purpose discs (DVDs)), smart cards, flash memory devices (e.g., cards, sticks, or key drives), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable medium for storing software or instructions that can be accessed and read by a computer. Computer-readable medium 406 may reside in processing system 420, be located outside processing system 420, or be distributed across multiple entities including processing system 420. Those skilled in the art will recognize that how best to implement the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0051] Device 400 may be configured to perform any one or more of the operations described herein. In some aspects of this disclosure, such as the interconnect controller 404 utilized in device 400, circuitry configured for various functions may be included.

[0052] Interconnect controller 404 is coupled to system memory 408 via bus 426. System memory 408 may include parameters and configuration values, which may be initial settings, operating system settings, or application settings for configuring the threshold table 448 described above. The threshold table 448 used by interconnect controller 404 may be in interconnect controller 404, computer-readable medium 406, system memory 408, delay circuitry 442, comparison logic (not shown), or another device.

[0053] The interconnect controller 404 may include thermal monitoring circuitry 440 configured to determine the thermal state of the processing core. Thermal monitoring circuitry 440 may include one or more hardware components that provide the physical structure for performing various processes related to determining the thermal state of the processing core. Thermal monitoring circuitry 440 may include functionality of components for determining the thermal state of the processing core. Thermal monitoring circuitry 440 may also be configured to execute thermal monitoring instructions 460 included on a computer-readable medium 406 to implement the thermal monitor described herein.

[0054] Interconnect controller 404 may include delay circuitry 442, also referred to herein as comparison logic, configured to generate delay commands by comparing a thermal state with thresholds in threshold table 448, as discussed herein. The delay circuitry may include components that generate delay commands in response to comparisons with thresholds in threshold table 448 of the memory controller to indicate the functionality of a thermal state. Delay circuitry 442 may also be configured to execute delay instructions 462 included on computer-readable medium 406 to implement one or more of the functions described herein.

[0055] Interconnect controller 404 may include memory transaction circuitry 444 configured to delay access to memory in response to a delay command. Memory transaction circuitry 444 may include functionality, such as components, for delaying access to memory in response to a delay command. Memory transaction circuitry 444 may also be configured to execute memory transaction instructions 464 included on computer-readable medium 406 to implement one or more of the functions described herein.

[0056] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various process technologies, such as complementary metal-oxide-semiconductor (CMOS), NMOS, PMOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0057] Figure 5 This is a flowchart of the process using a mapping table for delayed memory access. After the start, at block 502, the process includes determining the thermal state of the processing core. A thermal sensor can generate a thermal signal, such as a voltage, indicating the temperature of the processing core. The thermal sensor can be coupled to a thermal monitor configured to determine the thermal state. The thermal monitor determines the thermal state by comparing the thermal signal to a threshold.

[0058] At block 504, the process includes delaying access by the processing core to memory coupled to the processing core via the memory controller in response to a thermal state. In some aspects, the process includes a thermal monitor generating a delay command to the memory controller in response to a thermal state. In some aspects, a tunable delay element is coupled to the memory controller to delay access in response to the delay command, for example, by adding an instruction that is not currently in operation to the memory bus in response to a thermal state.

[0059] In one aspect, delayed access is achieved by adding a delayed state to read and write transactions from the processing core. In another aspect, delayed access is achieved by adding an instruction with no operation to the memory bus. Other components for delayed access may be used alternatively or additionally.

[0060] As used herein, “or” is intended to be interpreted as inclusive unless otherwise explicitly stated. For example, “a or b” could include only a, only b, or a combination of a and b. As used herein, the phrase “at least one of” or “one or more of” refers to any combination of these items, including a single member. For example, “at least one of a, b, or c” is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0061] The various exemplary components, logic elements, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific embodiments disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of its functionality and exemplified in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0062] The various exemplary logic blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic element, discrete hardware component, or any combination thereof. The general-purpose processor can be a microprocessor, and the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0063] In one or more exemplary aspects, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code stored on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0064] Various modifications to the specific embodiments described herein will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0065] Additionally, the various features described in this specification in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Thus, although features may be described above as functioning in a particular combination, and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may involve sub-combinations or variations of sub-combinations.

[0066] Similarly, although operations are depicted in a specific order in the diagrams, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the accompanying drawings may schematically depict one or more example processes in the form of flowcharts or flow diagrams. However, other operations not depicted may be incorporated into the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In some environments, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the specific implementations described above should not be construed as requiring such separation in all implementations, but rather should be understood as meaning that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0067] The following provides an overview of various embodiments of this disclosure.

[0068] Example 1: An apparatus comprising: a processing core; a memory; a thermal monitor configured to determine the thermal state of the processing core; and a memory controller coupled to the processing core, the thermal monitor, and the memory, and configured to provide the processing core with access to the memory, the memory controller further configured to delay access to the memory in response to the thermal state.

[0069] Example 2: According to the apparatus of Example 1, the apparatus further includes a memory interface located between the processing core and the memory controller, and wherein the thermal monitor is integrated with the memory interface.

[0070] Example 3: The apparatus according to Example 1 or 2, wherein the thermal monitor receives a thermal signal indicating the temperature of the processing core, wherein the thermal monitor compares the thermal signal with a threshold, and wherein the thermal monitor generates a delay command in response to the thermal signal exceeding the threshold.

[0071] Example 4: An apparatus according to any one or more of the above embodiments, wherein the memory controller delays access by adding a delay state to read and write transactions from the processing core.

[0072] Example 5: An apparatus according to any one or more of the above embodiments, wherein the memory controller delays access by adding a wait state to read and write transactions from the processing core.

[0073] Example 6: An apparatus according to any one or more of the above embodiments, wherein the memory controller delays access by adding instructions other than read and write transactions from the processing core.

[0074] Example 7: According to any one or more of the above embodiments, the apparatus further includes a memory bus located between the memory controller and the memory, and wherein a tunable delay element is coupled to the memory controller to add an inactive instruction to the memory bus in response to the thermal state.

[0075] Example 8: The apparatus according to any one or more of the above embodiments, wherein the thermal monitor uses the thermal state to select one of a plurality of delay quantities.

[0076] Example 9: An apparatus according to any one or more of the above embodiments, the apparatus comprising: a second processing core coupled to the memory controller for accessing the memory, wherein a thermal monitor determines the thermal state of the second processing core, and wherein the thermal controller delays access to the memory in part in response to averaging the thermal state of the first processing core and the thermal state of the second processing core.

[0077] Example 10: An apparatus according to any one or more of the above embodiments, the apparatus comprising: a second processing core coupled to the memory controller for accessing the memory, wherein a thermal monitor determines the thermal state of the second processing core, and wherein the thermal controller partially responds to aggregating the thermal state of the first processing core and the thermal state of the second processing core to determine a maximum thermal state to delay access to the memory.

[0078] Example 11: The apparatus according to any one or more of the above embodiments, wherein the memory is a random access memory.

[0079] Example 12: According to any one or more of the above embodiments, the apparatus further includes a dynamic clock and voltage scaling system coupled to the processing core, wherein the dynamic clock and voltage scaling system reduces the voltage applied to the processing core in response to a first thermal state, and wherein the memory controller delays access to the memory in response to a second thermal state, wherein the second thermal state corresponds to a temperature lower than the first thermal state.

[0080] Example 13: An apparatus according to any one or more of the above embodiments, the apparatus including a thermal sensor thermally coupled to the processing core and configured to generate a thermal signal to the thermal monitor, wherein the thermal monitor is coupled to the thermal sensor to receive the thermal signal and determine the thermal state in response to the thermal signal.

[0081] Example 14: The apparatus according to Example 13, wherein the thermal sensor provides a voltage to the thermal monitor, and wherein the thermal monitor uses the voltage to determine the thermal state.

[0082] Example 15: A method comprising: determining a thermal state of a processing core; and, in response to the thermal state, delaying access by the processing core to memory coupled to the processing core via the memory controller.

[0083] Example 16: The method according to Example 15, the method includes: receiving a thermal signal indicating the temperature of the processing core; and comparing the thermal signal with a threshold, wherein determining the thermal state includes comparing the thermal signal with the threshold.

[0084] Example 17: The method according to Example 15 or 16, wherein delayed access includes adding a delayed state to read and write transactions from the processing core.

[0085] Example 18: The method according to any one or more of Examples 15 to 17, wherein delayed access includes adding an instruction that is not in operation to the memory bus.

[0086] Example 19: An apparatus comprising: a component for determining a thermal state of a processing core; and a component for delaying access by the processing core to a memory coupled to the processing core via the memory controller in response to the thermal state.

[0087] Example 20: The apparatus according to Example 19, wherein the component for delayed access adds a delayed state to read and write transactions from the processing core...

Claims

1. An apparatus, the apparatus comprising: Processing core; Memory; A thermal monitor configured to determine the thermal state of the processing core; as well as A memory controller coupled to the processing core, the thermal monitor, and the memory, and configured to provide the processing core with access to the memory, and further configured to delay access to the memory in response to the thermal state.

2. The apparatus of claim 1, further comprising a memory interface located between the processing core and the memory controller, wherein the thermal monitor is integrated with the memory interface.

3. The apparatus of claim 1, wherein the thermal monitor receives a thermal signal indicating the temperature of the processing core, wherein the thermal monitor compares the thermal signal with a threshold, and wherein the thermal monitor generates a delay command in response to the thermal signal exceeding the threshold.

4. The apparatus of claim 1, wherein the memory controller delays access by adding a delay state to read and write transactions from the processing core.

5. The apparatus of claim 1, wherein the memory controller delays access by adding a wait state to read and write transactions from the processing core.

6. The apparatus of claim 1, wherein the memory controller delays access by adding instructions other than read and write transactions from the processing core.

7. The apparatus according to claim 1, further comprising: A memory bus, located between the memory controller and the memory; as well as A tunable delay element coupled to the memory controller to add an inactive instruction to the memory bus in response to the thermal state.

8. The apparatus of claim 1, wherein the thermal monitor uses the thermal state to select one of a plurality of delay quantities.

9. The apparatus according to claim 1, wherein the apparatus comprises: A second processing core, coupled to the memory controller for accessing the memory. The thermal monitor determines the thermal state of the second processing core, and The thermal controller partially delays access to the memory in response to averaging the thermal states of the first processing core and the second processing core.

10. The apparatus of claim 1, wherein the apparatus comprises: A second processing core, coupled to the memory controller for accessing the memory. The thermal monitor determines the thermal state of the second processing core, and The thermal controller partially responds to aggregating the thermal states of the first processing core and the second processing core to determine the highest thermal state in order to delay access to the memory.

11. The apparatus of claim 1, wherein the memory is a random access memory.

12. The apparatus of claim 1, further comprising a dynamic clock and voltage scaling system coupled to the processing core, wherein the dynamic clock and voltage scaling system reduces the voltage applied to the processing core in response to a first thermal state, and wherein the memory controller delays access to the memory in response to a second thermal state, wherein the second thermal state corresponds to a temperature lower than the first thermal state.

13. The apparatus of claim 1, the apparatus comprising a thermal sensor thermally coupled to the processing core and configured to generate a thermal signal to the thermal monitor, wherein the thermal monitor is coupled to the thermal sensor to receive the thermal signal and determine the thermal state in response to the thermal signal.

14. The apparatus of claim 13, wherein the thermal sensor provides a voltage to the thermal monitor, and wherein the thermal monitor uses the voltage to determine the thermal state.

15. A method comprising: Determine the thermal state of the processing core; as well as In response to the thermal state, the processing core's access to the memory coupled to the processing core via the memory controller is delayed.

16. The method of claim 15, wherein the method comprises: Receive a thermal signal from a thermal sensor indicating the temperature of the processing core. Determining the thermal state includes comparing the thermal signal with a threshold.

17. The method of claim 15, wherein delayed access includes adding a delayed state to read and write transactions from the processing core.

18. The method of claim 15, wherein delayed access comprises adding an instruction that is not in operation to the memory bus.

19. An apparatus comprising: Components used to determine the thermal state of the processing core; as well as A component used to delay the processing core's access to the memory coupled to the processing core via the memory controller in response to the thermal state.

20. The apparatus of claim 19, wherein the component for delayed access adds a delayed state to read and write transactions from the processing core.

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